Lines Matching +full:axi +full:- +full:ethernet +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
20 #define XAE_HDR_SIZE 14 /* Size of Ethernet header */
21 #define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */
22 #define XAE_MTU 1500 /* Max MTU of an Ethernet frame */
35 #define XAE_OPTION_JUMBO BIT(1)
73 /* Axi DMA Register definitions */
129 #define XAXIDMA_DFT_RX_THRESHOLD 1
148 /* Axi Ethernet registers definition */
151 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
164 #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
176 #define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */
180 #define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */
181 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
182 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
188 /* Bit Masks for Axi Ethernet RAF register */
207 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
209 /* Transmit inter-frame gap adjustment value */
212 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
232 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
234 #define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */
236 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
238 #define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */
240 /* Bit masks for Axi Ethernet RCW1 register */
243 /* In-Band FCS enable (FCS not stripped) */
256 /* Bit masks for Axi Ethernet TC register */
259 /* In-Band FCS enable (FCS not generated) */
263 /* Inter-frame gap adjustment enable */
266 /* Bit masks for Axi Ethernet FCC register */
270 /* Bit masks for Axi Ethernet EMMC register */
282 /* Bit masks for Axi Ethernet PHYC register */
285 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
294 /* Bit masks for Axi Ethernet ability register */
301 #define XAE_ABILITY_100M BIT(1)
304 /* Bit masks for Axi Ethernet MDIO interface MC register */
308 /* Bit masks for Axi Ethernet MDIO interface MCR register */
320 /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
323 /* Bit masks for Axi Ethernet UAW1 register */
329 /* Bit masks for Axi Ethernet FMC register */
335 /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
337 #define XAE_PHY_TYPE_GMII 1
346 /* Axi Ethernet Synthesis features */
348 #define XAE_FEATURE_PARTIAL_TX_CSUM BIT(1)
366 /* enum temac_stat - TEMAC statistics counters
422 * struct axidma_bd - Axi Dma buffer descriptor layout
432 * @app1: MM2S/S2MM User Application Field 1.
440 u32 next_msb; /* high 32 bits for IP >= v7.1, reserved on older IP */
442 u32 phys_msb; /* for IP >= v7.1, reserved for older IP */
458 * struct skbuf_dma_descriptor - skb for each dma descriptor
466 struct scatterlist sgl[MAX_SKB_FRAGS + 1];
474 * struct axienet_local - axienet private per device data
482 * @axi_clk: AXI4-Lite bus clock
483 * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
513 * @hw_last_counter: Last-seen value of each statistic counter
521 * @dma_err_task: Work structure to process Axi DMA errors
526 * @eth_irq: Ethernet core IRQ number
527 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
629 * struct axienet_option - Used to set axi ethernet hardware options
641 * axienet_ior - Memory mapped Axi Ethernet register read
643 * @offset: Address offset from the base address of Axi Ethernet core
645 * Return: The contents of the Axi Ethernet register
651 return ioread32(lp->regs + offset); in axienet_ior()
661 if (lp->mii_bus) in axienet_lock_mii()
662 mutex_lock(&lp->mii_bus->mdio_lock); in axienet_lock_mii()
667 if (lp->mii_bus) in axienet_unlock_mii()
668 mutex_unlock(&lp->mii_bus->mdio_lock); in axienet_unlock_mii()
672 * axienet_iow - Memory mapped Axi Ethernet register write
674 * @offset: Address offset from the base address of Axi Ethernet core
675 * @value: Value to be written into the Axi Ethernet register
677 * This function writes the desired value into the corresponding Axi Ethernet
683 iowrite32(value, lp->regs + offset); in axienet_iow()
687 * axienet_dma_out32 - Memory mapped Axi DMA register write.
689 * @reg: Address offset from the base address of the Axi DMA core
690 * @value: Value to be written into the Axi DMA register
692 * This function writes the desired value into the corresponding Axi DMA
699 iowrite32(value, lp->dma_regs + reg); in axienet_dma_out32()
704 * axienet_dma_out64 - Memory mapped Axi DMA register write.
706 * @reg: Address offset from the base address of the Axi DMA core
707 * @value: Value to be written into the Axi DMA register
709 * This function writes the desired value into the corresponding Axi DMA
715 iowrite64(value, lp->dma_regs + reg); in axienet_dma_out64()
721 if (lp->features & XAE_FEATURE_DMA_64BIT) in axienet_dma_out_addr()