Lines Matching +full:axi4 +full:- +full:lite

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
151 #define XAE_IFGP_OFFSET		0x00000008 /* Tx Inter-frame gap adjustment*/
181 #define XAE_AM0_OFFSET		0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
182 #define XAE_AM1_OFFSET		0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
209 /* Transmit inter-frame gap adjustment value */
243 /* In-Band FCS enable (FCS not stripped) */
259 /* In-Band FCS enable (FCS not generated) */
263 /* Inter-frame gap adjustment enable */
285 #define XAE_PHYC_RGMIIHD_MASK		0x00000002 /* RGMII Half-duplex */
366 /* enum temac_stat - TEMAC statistics counters
422  * struct axidma_bd - Axi Dma buffer descriptor layout
458  * struct skbuf_dma_descriptor - skb for each dma descriptor
474  * struct axienet_local - axienet private per device data
482  * @axi_clk:	AXI4-Lite bus clock
483  * @misc_clks:	Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
513  * @hw_last_counter: Last-seen value of each statistic counter
527  * @phy_mode:	Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
629  * struct axienet_option - Used to set axi ethernet hardware options
641  * axienet_ior - Memory mapped Axi Ethernet register read
651 	return ioread32(lp->regs + offset);  in axienet_ior()
661 	if (lp->mii_bus)  in axienet_lock_mii()
662 		mutex_lock(&lp->mii_bus->mdio_lock);  in axienet_lock_mii()
667 	if (lp->mii_bus)  in axienet_unlock_mii()
668 		mutex_unlock(&lp->mii_bus->mdio_lock);  in axienet_unlock_mii()
672  * axienet_iow - Memory mapped Axi Ethernet register write
683 	iowrite32(value, lp->regs + offset);  in axienet_iow()
687  * axienet_dma_out32 - Memory mapped Axi DMA register write.
699 	iowrite32(value, lp->dma_regs + reg);  in axienet_dma_out32()
704  * axienet_dma_out64 - Memory mapped Axi DMA register write.
715 	iowrite64(value, lp->dma_regs + reg);  in axienet_dma_out64()
721 	if (lp->features & XAE_FEATURE_DMA_64BIT)  in axienet_dma_out_addr()