Lines Matching +full:0 +full:xc80
40 #define TLAN_IGNORE 0
47 } while (0)
49 #define TLAN_DEBUG_GNRL 0x0001
50 #define TLAN_DEBUG_TX 0x0002
51 #define TLAN_DEBUG_RX 0x0004
52 #define TLAN_DEBUG_LIST 0x0008
53 #define TLAN_DEBUG_PROBE 0x0010
65 #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012
66 #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030
68 #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013
71 #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012
74 #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014
85 #define TLAN_ADAPTER_NONE 0x00000000
86 #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001
87 #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002
88 #define TLAN_ADAPTER_USE_INTERN_10 0x00000004
89 #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008
91 #define TLAN_SPEED_DEFAULT 0
95 #define TLAN_DUPLEX_DEFAULT 0
106 #define EISA_ID 0xc80 /* EISA ID Registers */
107 #define EISA_ID0 0xc80 /* EISA ID Register 0 */
108 #define EISA_ID1 0xc81 /* EISA ID Register 1 */
109 #define EISA_ID2 0xc82 /* EISA ID Register 2 */
110 #define EISA_ID3 0xc83 /* EISA ID Register 3 */
111 #define EISA_CR 0xc84 /* EISA Control Register */
112 #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */
113 #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */
114 #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */
115 #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */
116 #define EISA_APROM 0xc90 /* Ethernet Address PROM */
126 #define TLAN_LAST_BUFFER 0x80000000
127 #define TLAN_CSTAT_UNUSED 0x8000
128 #define TLAN_CSTAT_FRM_CMP 0x4000
129 #define TLAN_CSTAT_READY 0x3000
130 #define TLAN_CSTAT_EOC 0x0800
131 #define TLAN_CSTAT_RX_ERROR 0x0400
132 #define TLAN_CSTAT_PASS_CRC 0x0200
133 #define TLAN_CSTAT_DP_PR 0x0100
160 #define TLAN_PHY_MAX_ADDR 0x1F
161 #define TLAN_PHY_NONE 0x20
239 #define TLAN_EEPROM_ACK 0
251 #define TLAN_HOST_CMD 0x00
252 #define TLAN_HC_GO 0x80000000
253 #define TLAN_HC_STOP 0x40000000
254 #define TLAN_HC_ACK 0x20000000
255 #define TLAN_HC_CS_MASK 0x1FE00000
256 #define TLAN_HC_EOC 0x00100000
257 #define TLAN_HC_RT 0x00080000
258 #define TLAN_HC_NES 0x00040000
259 #define TLAN_HC_AD_RST 0x00008000
260 #define TLAN_HC_LD_TMR 0x00004000
261 #define TLAN_HC_LD_THR 0x00002000
262 #define TLAN_HC_REQ_INT 0x00001000
263 #define TLAN_HC_INT_OFF 0x00000800
264 #define TLAN_HC_INT_ON 0x00000400
265 #define TLAN_HC_AC_MASK 0x000000FF
266 #define TLAN_CH_PARM 0x04
267 #define TLAN_DIO_ADR 0x08
268 #define TLAN_DA_ADR_INC 0x8000
269 #define TLAN_DA_RAM_ADR 0x4000
270 #define TLAN_HOST_INT 0x0A
271 #define TLAN_HI_IV_MASK 0x1FE0
272 #define TLAN_HI_IT_MASK 0x001C
273 #define TLAN_DIO_DATA 0x0C
278 #define TLAN_NET_CMD 0x00
279 #define TLAN_NET_CMD_NRESET 0x80
280 #define TLAN_NET_CMD_NWRAP 0x40
281 #define TLAN_NET_CMD_CSF 0x20
282 #define TLAN_NET_CMD_CAF 0x10
283 #define TLAN_NET_CMD_NOBRX 0x08
284 #define TLAN_NET_CMD_DUPLEX 0x04
285 #define TLAN_NET_CMD_TRFRAM 0x02
286 #define TLAN_NET_CMD_TXPACE 0x01
287 #define TLAN_NET_SIO 0x01
288 #define TLAN_NET_SIO_MINTEN 0x80
289 #define TLAN_NET_SIO_ECLOK 0x40
290 #define TLAN_NET_SIO_ETXEN 0x20
291 #define TLAN_NET_SIO_EDATA 0x10
292 #define TLAN_NET_SIO_NMRST 0x08
293 #define TLAN_NET_SIO_MCLK 0x04
294 #define TLAN_NET_SIO_MTXEN 0x02
295 #define TLAN_NET_SIO_MDATA 0x01
296 #define TLAN_NET_STS 0x02
297 #define TLAN_NET_STS_MIRQ 0x80
298 #define TLAN_NET_STS_HBEAT 0x40
299 #define TLAN_NET_STS_TXSTOP 0x20
300 #define TLAN_NET_STS_RXSTOP 0x10
301 #define TLAN_NET_STS_RSRVD 0x0F
302 #define TLAN_NET_MASK 0x03
303 #define TLAN_NET_MASK_MASK7 0x80
304 #define TLAN_NET_MASK_MASK6 0x40
305 #define TLAN_NET_MASK_MASK5 0x20
306 #define TLAN_NET_MASK_MASK4 0x10
307 #define TLAN_NET_MASK_RSRVD 0x0F
308 #define TLAN_NET_CONFIG 0x04
309 #define TLAN_NET_CFG_RCLK 0x8000
310 #define TLAN_NET_CFG_TCLK 0x4000
311 #define TLAN_NET_CFG_BIT 0x2000
312 #define TLAN_NET_CFG_RXCRC 0x1000
313 #define TLAN_NET_CFG_PEF 0x0800
314 #define TLAN_NET_CFG_1FRAG 0x0400
315 #define TLAN_NET_CFG_1CHAN 0x0200
316 #define TLAN_NET_CFG_MTEST 0x0100
317 #define TLAN_NET_CFG_PHY_EN 0x0080
318 #define TLAN_NET_CFG_MSMASK 0x007F
319 #define TLAN_MAN_TEST 0x06
320 #define TLAN_DEF_VENDOR_ID 0x08
321 #define TLAN_DEF_DEVICE_ID 0x0A
322 #define TLAN_DEF_REVISION 0x0C
323 #define TLAN_DEF_SUBCLASS 0x0D
324 #define TLAN_DEF_MIN_LAT 0x0E
325 #define TLAN_DEF_MAX_LAT 0x0F
326 #define TLAN_AREG_0 0x10
327 #define TLAN_AREG_1 0x16
328 #define TLAN_AREG_2 0x1C
329 #define TLAN_AREG_3 0x22
330 #define TLAN_HASH_1 0x28
331 #define TLAN_HASH_2 0x2C
332 #define TLAN_GOOD_TX_FRMS 0x30
333 #define TLAN_TX_UNDERUNS 0x33
334 #define TLAN_GOOD_RX_FRMS 0x34
335 #define TLAN_RX_OVERRUNS 0x37
336 #define TLAN_DEFERRED_TX 0x38
337 #define TLAN_CRC_ERRORS 0x3A
338 #define TLAN_CODE_ERRORS 0x3B
339 #define TLAN_MULTICOL_FRMS 0x3C
340 #define TLAN_SINGLECOL_FRMS 0x3E
341 #define TLAN_EXCESSCOL_FRMS 0x40
342 #define TLAN_LATE_COLS 0x41
343 #define TLAN_CARRIER_LOSS 0x42
344 #define TLAN_ACOMMIT 0x43
345 #define TLAN_LED_REG 0x44
346 #define TLAN_LED_ACT 0x10
347 #define TLAN_LED_LINK 0x01
348 #define TLAN_BSIZE_REG 0x45
349 #define TLAN_MAX_RX 0x46
350 #define TLAN_INT_DIS 0x48
351 #define TLAN_ID_TX_EOC 0x04
352 #define TLAN_ID_RX_EOF 0x02
353 #define TLAN_ID_RX_EOC 0x01
361 #define TLAN_INT_NONE 0x0000
362 #define TLAN_INT_TX_EOF 0x0001
363 #define TLAN_INT_STAT_OVERFLOW 0x0002
364 #define TLAN_INT_RX_EOF 0x0003
365 #define TLAN_INT_DUMMY 0x0004
366 #define TLAN_INT_TX_EOC 0x0005
367 #define TLAN_INT_STATUS_CHECK 0x0006
368 #define TLAN_INT_RX_EOC 0x0007
376 #define MII_GEN_CTL 0x00
377 #define MII_GC_RESET 0x8000
378 #define MII_GC_LOOPBK 0x4000
379 #define MII_GC_SPEEDSEL 0x2000
380 #define MII_GC_AUTOENB 0x1000
381 #define MII_GC_PDOWN 0x0800
382 #define MII_GC_ISOLATE 0x0400
383 #define MII_GC_AUTORSRT 0x0200
384 #define MII_GC_DUPLEX 0x0100
385 #define MII_GC_COLTEST 0x0080
386 #define MII_GC_RESERVED 0x007F
387 #define MII_GEN_STS 0x01
388 #define MII_GS_100BT4 0x8000
389 #define MII_GS_100BTXFD 0x4000
390 #define MII_GS_100BTXHD 0x2000
391 #define MII_GS_10BTFD 0x1000
392 #define MII_GS_10BTHD 0x0800
393 #define MII_GS_RESERVED 0x07C0
394 #define MII_GS_AUTOCMPLT 0x0020
395 #define MII_GS_RFLT 0x0010
396 #define MII_GS_AUTONEG 0x0008
397 #define MII_GS_LINK 0x0004
398 #define MII_GS_JABBER 0x0002
399 #define MII_GS_EXTCAP 0x0001
400 #define MII_GEN_ID_HI 0x02
401 #define MII_GEN_ID_LO 0x03
402 #define MII_GIL_OUI 0xFC00
403 #define MII_GIL_MODEL 0x03F0
404 #define MII_GIL_REVISION 0x000F
405 #define MII_AN_ADV 0x04
406 #define MII_AN_LPA 0x05
407 #define MII_AN_EXP 0x06
411 #define TLAN_TLPHY_ID 0x10
412 #define TLAN_TLPHY_CTL 0x11
413 #define TLAN_TC_IGLINK 0x8000
414 #define TLAN_TC_SWAPOL 0x4000
415 #define TLAN_TC_AUISEL 0x2000
416 #define TLAN_TC_SQEEN 0x1000
417 #define TLAN_TC_MTEST 0x0800
418 #define TLAN_TC_RESERVED 0x07F8
419 #define TLAN_TC_NFEW 0x0004
420 #define TLAN_TC_INTEN 0x0002
421 #define TLAN_TC_TINT 0x0001
422 #define TLAN_TLPHY_STS 0x12
423 #define TLAN_TS_MINT 0x8000
424 #define TLAN_TS_PHOK 0x4000
425 #define TLAN_TS_POLOK 0x2000
426 #define TLAN_TS_TPENERGY 0x1000
427 #define TLAN_TS_RESERVED 0x0FFF
428 #define TLAN_TLPHY_PAR 0x19
429 #define TLAN_PHY_CIM_STAT 0x0020
430 #define TLAN_PHY_SPEED_100 0x0040
431 #define TLAN_PHY_DUPLEX_FULL 0x0080
432 #define TLAN_PHY_AN_EN_STAT 0x0400
435 #define NAT_SEM_ID1 0x2000
436 #define NAT_SEM_ID2 0x5C01
437 #define LEVEL1_ID1 0x7810
438 #define LEVEL1_ID2 0x0000
440 #define CIRC_INC(a, b) if (++a >= b) a = 0
447 return inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)); in tlan_dio_read8()
457 return inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2)); in tlan_dio_read16()
477 outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3)); in tlan_dio_write8()
487 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); in tlan_dio_write16()
497 outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); in tlan_dio_write32()
517 * hash = XOR8(DA(a,0), DA(a, 6), DA(a,12), DA(a,18), DA(a,24),
535 hash = (a[0]^a[3]); /* & 077 */ in tlan_hash_func()
536 hash ^= ((a[0]^a[3])>>6); /* & 003 */ in tlan_hash_func()