Lines Matching +full:0 +full:x001b
21 #define FW_LINK_SPEED_1G (0x00)
22 #define FW_LINK_SPEED_100M (0x01)
23 #define FW_LINK_SPEED_10M (0x02)
24 #define FW_LINK_SPEED_HD (0x80)
29 #define FDB_AGEING_TIMEOUT_OFFSET 0x0014
32 #define HOST_PORT_DF_VLAN_OFFSET 0x001C
38 #define P1_PORT_DF_VLAN_OFFSET 0x0020
44 #define P2_PORT_DF_VLAN_OFFSET 0x0024
49 /* VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000 */
50 #define VLAN_STATIC_REG_TABLE_OFFSET 0x0100
56 #define PORT_DESC0_HI 0x2104
59 #define PORT_DESC0_LO 0x2F6C
62 #define PORT_DESC1_HI 0x3DD4
65 #define PORT_DESC1_LO 0x4C3C
68 #define HOST_DESC0_HI 0x5AA4
71 #define HOST_DESC0_LO 0x5F0C
74 #define HOST_DESC1_HI 0x6374
77 #define HOST_DESC1_LO 0x67DC
80 #define HOST_SPPD0 0x7AAC
83 #define HOST_SPPD1 0x7EAC
86 #define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC
89 #define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET 0x83F4
92 #define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8
95 #define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET 0x83FC
98 #define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C
101 #define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440
104 #define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444
107 #define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C
110 #define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450
113 #define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET 0x8454
116 #define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET 0x8458
119 #define TIMESYNC_FW_SIG_PNFW_OFFSET 0x845C
122 #define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460
125 #define TAS_CONFIG_CHANGE_TIME 0x000C
128 #define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014
131 #define TAS_CONFIG_PENDING 0x0018
134 #define TAS_CONFIG_CHANGE 0x0019
137 #define TAS_ADMIN_LIST_LENGTH 0x001A
140 #define TAS_ACTIVE_LIST_INDEX 0x001B
143 #define TAS_ADMIN_CYCLE_TIME 0x001C
146 #define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020
149 #define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024
155 #define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026
161 #define SPL_PKT_DEFAULT_PRIORITY 0x0028
164 #define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029
167 #define QUEUE_NUM_UNTAGGED 0x002A
170 #define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C
175 #define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034
178 #define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C
181 #define PORT_LINK_SPEED_OFFSET 0x00A8
184 #define TAS_GATE_MASK_LIST0 0x0100
187 #define TAS_GATE_MASK_LIST1 0x0350
190 #define PRE_EMPTION_ENABLE_TX 0x05A0
193 #define PRE_EMPTION_ACTIVE_TX 0x05A1
196 #define PRE_EMPTION_ENABLE_VERIFY 0x05A2
199 #define PRE_EMPTION_VERIFY_STATUS 0x05A3
202 #define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4
205 #define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6
208 #define PRE_EMPTION_VERIFY_TIME 0x05A8
211 #define MGR_R30_CMD_OFFSET 0x05AC
214 #define BUFFER_POOL_0_ADDR_OFFSET 0x05BC
217 #define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684
220 #define FDB_CMD_BUFFER 0x0894
223 #define TAS_QUEUE_MAX_SDU_LIST 0x08FA
226 #define HD_RAND_SEED_OFFSET 0x0934
229 #define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x0940
232 #define PA_STAT_32b_START_OFFSET 0x0080