21 #define MII_RT_TX_IPG_100M	0x17
22 #define MII_RT_TX_IPG_1G	0xb
23 #define MII_RT_TX_IPG_100M_SR1	0x166
24 #define MII_RT_TX_IPG_1G_SR1	0x1a
27 #define	ICSSG_QUEUE_OFFSET		0xd00
28 #define	ICSSG_QUEUE_PEEK_OFFSET		0xe00
29 #define	ICSSG_QUEUE_CNT_OFFSET		0xe40
30 #define	ICSSG_QUEUE_RESET_OFFSET	0xf40
66 #define FDB_GEN_CFG1		0x60
70 #define FDB_GEN_CFG2		0x64
74 #define FDB_PRU0_EN		BIT(0)
95 		{ PORT_HI_Q_SLICE0, PORT_DESC0_HI, 0x200000, 0 },
96 		{ PORT_LO_Q_SLICE0, PORT_DESC0_LO, 0, 0 },
97 		{ HOST_HI_Q_SLICE0, HOST_DESC0_HI, 0x200000, 0 },
98 		{ HOST_LO_Q_SLICE0, HOST_DESC0_LO, 0, 0 },
99 		{ HOST_SPL_Q_SLICE0, HOST_SPPD0, 0x400000, 1 },
102 		{ PORT_HI_Q_SLICE1, PORT_DESC1_HI, 0xa00000, 0 },
103 		{ PORT_LO_Q_SLICE1, PORT_DESC1_LO, 0x800000, 0 },
104 		{ HOST_HI_Q_SLICE1, HOST_DESC1_HI, 0xa00000, 0 },
105 		{ HOST_LO_Q_SLICE1, HOST_DESC1_LO, 0x800000, 0 },
106 		{ HOST_SPL_Q_SLICE1, HOST_SPPD1, 0xc00000, 1 },
134 	regmap_write(mii_rt, pcnt_reg, 0x1);  in icssg_config_mii_init_fw_offload()
162 	regmap_write(mii_rt, pcnt_reg, 0x1);  in icssg_config_mii_init()
170 	int queue = 0, i, j;  in icssg_miig_queues_init()
177 	for (i = 0; i < ICSSG_NUM_TX_QUEUES; i++) {  in icssg_miig_queues_init()
185 	for (i = 0; i < ICSSG_NUM_OTHER_QUEUES; i++) {  in icssg_miig_queues_init()
194 	for (j = 0; j < ICSSG_NUM_OTHER_QUEUES; j++) {  in icssg_miig_queues_init()
208 		for (i = 0; i < num_pds; i++) {  in icssg_miig_queues_init()
209 			memset(pd, 0, pd_size);  in icssg_miig_queues_init()
211 			pdword[0] &= ICSSG_FLAG_MASK;  in icssg_miig_queues_init()
212 			pdword[0] |= mp->flags;  in icssg_miig_queues_init()
237 		/* Firmware hardcodes IPG for SR1.0 */  in icssg_config_ipg()
260 	for (i = 0; i < 4; i++)  in emac_r30_cmd_init()
272 	for (i = 0; i < 4; i++) {  in emac_r30_is_done()
275 			return 0;  in emac_r30_is_done()
300 	/* workaround for f/w bug. bpool 0 needs to be initialized */  in prueth_fw_offload_buffer_setup()
301 	for (i = 0; i <  PRUETH_NUM_BUF_POOLS; i++) {  in prueth_fw_offload_buffer_setup()
321 			writel(0, &bpool_cfg[i].addr);  in prueth_fw_offload_buffer_setup()
322 			writel(0, &bpool_cfg[i].len);  in prueth_fw_offload_buffer_setup()
332 	for (i = 0; i < 3; i++)  in prueth_fw_offload_buffer_setup()
338 	return 0;  in prueth_fw_offload_buffer_setup()
364 	/* workaround for f/w bug. bpool 0 needs to be initilalized */  in prueth_emac_buffer_setup()
365 	writel(addr, &bpool_cfg[0].addr);  in prueth_emac_buffer_setup()
366 	writel(0, &bpool_cfg[0].len);  in prueth_emac_buffer_setup()
383 	for (i = 0; i < 3; i++)  in prueth_emac_buffer_setup()
391 	for (i = 0; i < 3; i++)  in prueth_emac_buffer_setup()
397 	return 0;  in prueth_emac_buffer_setup()
403 	 * back to the emac mode, the host mac address has to be set as 0.  in icssg_init_emac_mode()
407 	u8 mac[ETH_ALEN] = { 0 };  in icssg_init_emac_mode()
416 	for (i = 0; i < SZ_4K - 1; i++) {  in icssg_init_emac_mode()
418 		prueth->vlan_tbl[i].fid_c1 = 0;  in icssg_init_emac_mode()
437 	for (i = 0; i < SZ_4K - 1; i++) {  in icssg_init_fw_offload_mode()
439 		prueth->vlan_tbl[i].fid_c1 = 0;  in icssg_init_fw_offload_mode()
454 	memset_io(config, 0, TAS_GATE_MASK_LIST0);  in icssg_config()
481 	/* set C28 to 0x100 */  in icssg_config()
482 	pru_rproc_set_ctable(prueth->pru[slice], PRU_C28, 0x100 << 8);  in icssg_config()
483 	pru_rproc_set_ctable(prueth->rtu[slice], PRU_C28, 0x100 << 8);  in icssg_config()
484 	pru_rproc_set_ctable(prueth->txpru[slice], PRU_C28, 0x100 << 8);  in icssg_config()
488 	writew(0, &flow_cfg->mgm_base_flow);  in icssg_config()
489 	writeb(0, config + SPL_PKT_DEFAULT_PRIORITY);  in icssg_config()
490 	writeb(0, config + QUEUE_NUM_UNTAGGED);  in icssg_config()
501 	return 0;  in icssg_config()
507 	{{0xffff0004, 0xffff0100, 0xffff0004, EMAC_NONE}},	/* EMAC_PORT_DISABLE */
508 	{{0xfffb0040, 0xfeff0200, 0xfeff0200, EMAC_NONE}},	/* EMAC_PORT_BLOCK */
509 	{{0xffbb0000, 0xfcff0000, 0xdcfb0000, EMAC_NONE}},	/* EMAC_PORT_FORWARD */
510 	{{0xffbb0000, 0xfcff0000, 0xfcff2000, EMAC_NONE}},	/* EMAC_PORT_FORWARD_WO_LEARNING */
511 	{{0xffff0001, EMAC_NONE,  EMAC_NONE, EMAC_NONE}},	/* ACCEPT ALL */
512 	{{0xfffe0002, EMAC_NONE,  EMAC_NONE, EMAC_NONE}},	/* ACCEPT TAGGED */
513 	{{0xfffc0000, EMAC_NONE,  EMAC_NONE, EMAC_NONE}},	/* ACCEPT UNTAGGED and PRIO */
514 	{{EMAC_NONE,  0xffff0020, EMAC_NONE, EMAC_NONE}},	/* TAS Trigger List change */
515 	{{EMAC_NONE,  0xdfff1000, EMAC_NONE, EMAC_NONE}},	/* TAS set state ENABLE*/
516 	{{EMAC_NONE,  0xefff2000, EMAC_NONE, EMAC_NONE}},	/* TAS set state RESET*/
517 	{{EMAC_NONE,  0xcfff0000, EMAC_NONE, EMAC_NONE}},	/* TAS set state DISABLE*/
518 	{{EMAC_NONE,  EMAC_NONE,  0xffff0400, EMAC_NONE}},	/* UC flooding ENABLE*/
519 	{{EMAC_NONE,  EMAC_NONE,  0xfbff0000, EMAC_NONE}},	/* UC flooding DISABLE*/
520 	{{EMAC_NONE,  EMAC_NONE,  0xffff0800, EMAC_NONE}},	/* MC flooding ENABLE*/
521 	{{EMAC_NONE,  EMAC_NONE,  0xf7ff0000, EMAC_NONE}},	/* MC flooding DISABLE*/
522 	{{EMAC_NONE,  0xffff4000, EMAC_NONE, EMAC_NONE}},	/* Preemption on Tx ENABLE*/
523 	{{EMAC_NONE,  0xbfff0000, EMAC_NONE, EMAC_NONE}},	/* Preemption on Tx DISABLE*/
524 	{{0xffff0010,  EMAC_NONE, 0xffff0010, EMAC_NONE}},	/* VLAN AWARE*/
525 	{{0xffef0000,  EMAC_NONE, 0xffef0000, EMAC_NONE}},	/* VLAN UNWARE*/
526 	{{0xffff2000, EMAC_NONE, EMAC_NONE, EMAC_NONE}},	/* HSR_RX_OFFLOAD_ENABLE */
527 	{{0xdfff0000, EMAC_NONE, EMAC_NONE, EMAC_NONE}}		/* HSR_RX_OFFLOAD_DISABLE */
535 	int done = 0;  in icssg_set_port_state()
548 	for (i = 0; i < 4; i++)  in icssg_set_port_state()
610 	addr = icssg_queue_pop(prueth, slice == 0 ?  in icssg_send_fdb_msg()
612 	if (addr < 0)  in icssg_send_fdb_msg()
619 	icssg_queue_push(prueth, slice == 0 ?  in icssg_send_fdb_msg()
621 	ret = read_poll_timeout(icssg_queue_pop, addr, addr >= 0,  in icssg_send_fdb_msg()
622 				2000, 20000000, false, prueth, slice == 0 ?  in icssg_send_fdb_msg()
631 	icssg_queue_push(prueth, slice == 0 ?  in icssg_send_fdb_msg()
634 	return 0;  in icssg_send_fdb_msg()
649 	mac_fid[ETH_ALEN + 1] = 0;  in icssg_fdb_setup()
651 	fdb_slot = bitrev32(crc32_le(0, mac_fid, 8)) & PRUETH_SWITCH_FDB_MASK;  in icssg_fdb_setup()
659 	memcpy(&fdb_cmd->cmd_args[0], addr, 4);  in icssg_fdb_setup()
669 	struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 };  in icssg_fdb_add_del()
670 	struct mgmt_cmd fdb_cmd = { 0 };  in icssg_fdb_add_del()
685 		return 0;  in icssg_fdb_add_del()
694 	struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 };  in icssg_fdb_lookup()
695 	struct mgmt_cmd fdb_cmd = { 0 };  in icssg_fdb_lookup()
711 	for (i = 0; i < 4; i++) {  in icssg_fdb_lookup()
717 	return 0;  in icssg_fdb_lookup()
770 	pvid = (u32 __force)cpu_to_be32((ETH_P_8021Q << 16) | (vid & 0xff));  in icssg_set_pvid()
783 	struct mgmt_cmd_rsp fdb_cmd_rsp = { 0 };  in emac_fdb_flow_id_updated()
785 	struct mgmt_cmd fdb_cmd = { 0 };  in emac_fdb_flow_id_updated()
791 	fdb_cmd.param  = 0;  in emac_fdb_flow_id_updated()
794 	fdb_cmd.cmd_args[0] = 0;  in emac_fdb_flow_id_updated()
801 	return fdb_cmd_rsp.status == 1 ? 0 : -EINVAL;  in emac_fdb_flow_id_updated()