28 	tn40_write_reg(priv, TN40_REG_IMR, 0);  in tn40_disable_interrupts()
39 	memset(f, 0, sizeof(struct tn40_fifo));  in tn40_fifo_alloc()
53 	f->rptr = 0;  in tn40_fifo_alloc()
54 	f->wptr = 0;  in tn40_fifo_alloc()
60 	return 0;  in tn40_fifo_alloc()
83 		for (i = 0; i < nelem; i++)  in tn40_rxdb_alloc()
126  * takes 0 CPU cycles.
128  * Return: 0 on success and negative value on error.
166 	return 0;  in tn40_create_rx_ring()
186 	for (i = 0; i < db->nelem; i++) {  in tn40_rx_free_buffers()
213 	rxfd->info = cpu_to_le32(0x10003);	/* INFO =1 BC =3 */  in tn40_set_rx_desc()
220 	if (unlikely(delta >= 0)) {  in tn40_set_rx_desc()
222 		if (delta > 0) {  in tn40_set_rx_desc()
249 	for (i = dno; i > 0; i--) {  in tn40_rx_alloc_buffers()
262 	netdev_dbg(priv->ndev, "write_reg 0x%04x f->m.reg_wptr 0x%x\n",  in tn40_rx_alloc_buffers()
264 	netdev_dbg(priv->ndev, "read_reg  0x%04x f->m.reg_rptr=0x%x\n",  in tn40_rx_alloc_buffers()
266 	netdev_dbg(priv->ndev, "write_reg 0x%04x f->m.reg_wptr=0x%x\n",  in tn40_rx_alloc_buffers()
288 	int tmp_len, size, done = 0;  in tn40_rx_receive()
298 	if (size < 0)  in tn40_rx_receive()
301 	while (size > 0) {  in tn40_rx_receive()
328 		if (size < 0) {  in tn40_rx_receive()
350 		if (unlikely(tmp_len >= 0)) {  in tn40_rx_receive()
352 			if (tmp_len > 0) {  in tn40_rx_receive()
391 		    (pkt_id == 0) ? CHECKSUM_NONE : CHECKSUM_UNNECESSARY;  in tn40_rx_receive()
493 	return 0;  in tn40_tx_db_init()
508  * for (i = 0; i < TN40_MAX_PBL; i++) {
520 	{0x20, 0x04},
521 	{0x28, 0x05},
522 	{0x38, 0x07},
523 	{0x40, 0x08},
524 	{0x50, 0x0a},
525 	{0x58, 0x0b},
526 	{0x68, 0x0d},
527 	{0x70, 0x0e},
528 	{0x80, 0x10},
529 	{0x88, 0x11},
530 	{0x98, 0x13},
531 	{0xa0, 0x14},
532 	{0xb0, 0x16},
533 	{0xb8, 0x17},
534 	{0xc8, 0x19},
535 	{0xd0, 0x1a},
536 	{0xe0, 0x1c},
537 	{0xe8, 0x1d},
538 	{0xf8, 0x1f},
572  * Return: 0 on success and negative value on error.
579 	struct tn40_pbl *pbl = &txdd->pbl[0];  in tn40_tx_map_skb()
605 	for (i = 0; i < nr_frags; i++) {  in tn40_tx_map_skb()
609 		dma = skb_frag_dma_map(&priv->pdev->dev, frag, 0,  in tn40_tx_map_skb()
619 	for (i = 0; i < nr_frags; i++) {  in tn40_tx_map_skb()
636 	return 0;  in tn40_tx_map_skb()
640 	for (; i > 0; i--)  in tn40_tx_map_skb()
678 	return 0;  in tn40_create_tx_ring()
701 	if (fsize <= 0)  in tn40_tx_space()
716 	int txd_vlan_id = 0;  in tn40_start_xmit()
717 	int txd_lgsnd = 0;  in tn40_start_xmit()
718 	int txd_vtag = 0;  in tn40_start_xmit()
719 	int txd_mss = 0;  in tn40_start_xmit()
733 		txd_checksum = 0;  in tn40_start_xmit()
746 	txdd->va_hi = 0;  in tn40_start_xmit()
747 	txdd->va_lo = 0;  in tn40_start_xmit()
757 	netdev_dbg(priv->ndev, "=== w1: 0x%x ================\n",  in tn40_start_xmit()
759 	netdev_dbg(priv->ndev, "=== w2: mss 0x%x len 0x%x\n", txdd->mss,  in tn40_start_xmit()
784 	if (unlikely(len >= 0)) {  in tn40_start_xmit()
786 		if (len > 0)  in tn40_start_xmit()
800 			priv->tx_noupd = 0;  in tn40_start_xmit()
822 	int tx_level = 0;  in tn40_tx_cleanup()
841 		} while (db->rptr->len > 0);  in tn40_tx_cleanup()
860 		priv->tx_noupd = 0;  in tn40_tx_cleanup()
897 		priv->b0_len = 0;  in tn40_destroy_tx_ring()
919 	if (size == 0)  in tn40_tx_push_desc()
945 	int timer = 0;  in tn40_tx_push_desc_safe()
947 	while (size > 0) {  in tn40_tx_push_desc_safe()
955 		if (avail <= 0) {  in tn40_tx_push_desc_safe()
984 		tn40_write_reg(priv, 0x1010, 0x217);	/*ETHSD.REFCLK_CONF  */  in tn40_set_link_speed()
985 		tn40_write_reg(priv, 0x104c, 0x4c);	/*ETHSD.L0_RX_PCNT  */  in tn40_set_link_speed()
986 		tn40_write_reg(priv, 0x1050, 0x4c);	/*ETHSD.L1_RX_PCNT  */  in tn40_set_link_speed()
987 		tn40_write_reg(priv, 0x1054, 0x4c);	/*ETHSD.L2_RX_PCNT  */  in tn40_set_link_speed()
988 		tn40_write_reg(priv, 0x1058, 0x4c);	/*ETHSD.L3_RX_PCNT  */  in tn40_set_link_speed()
989 		tn40_write_reg(priv, 0x102c, 0x434);	/*ETHSD.L0_TX_PCNT  */  in tn40_set_link_speed()
990 		tn40_write_reg(priv, 0x1030, 0x434);	/*ETHSD.L1_TX_PCNT  */  in tn40_set_link_speed()
991 		tn40_write_reg(priv, 0x1034, 0x434);	/*ETHSD.L2_TX_PCNT  */  in tn40_set_link_speed()
992 		tn40_write_reg(priv, 0x1038, 0x434);	/*ETHSD.L3_TX_PCNT  */  in tn40_set_link_speed()
993 		tn40_write_reg(priv, 0x6300, 0x0400);	/*MAC.PCS_CTRL */  in tn40_set_link_speed()
995 		tn40_write_reg(priv, 0x1018, 0x00);	/*Mike2 */  in tn40_set_link_speed()
997 		tn40_write_reg(priv, 0x1018, 0x04);	/*Mike2 */  in tn40_set_link_speed()
999 		tn40_write_reg(priv, 0x1018, 0x06);	/*Mike2 */  in tn40_set_link_speed()
1002 		/*L0: 0x103c , L1: 0x1040 , L2: 0x1044 , L3: 0x1048 =0x81644 */  in tn40_set_link_speed()
1003 		tn40_write_reg(priv, 0x103c, 0x81644);	/*ETHSD.L0_TX_DCNT  */  in tn40_set_link_speed()
1004 		tn40_write_reg(priv, 0x1040, 0x81644);	/*ETHSD.L1_TX_DCNT  */  in tn40_set_link_speed()
1005 		tn40_write_reg(priv, 0x1044, 0x81644);	/*ETHSD.L2_TX_DCNT  */  in tn40_set_link_speed()
1006 		tn40_write_reg(priv, 0x1048, 0x81644);	/*ETHSD.L3_TX_DCNT  */  in tn40_set_link_speed()
1007 		tn40_write_reg(priv, 0x1014, 0x043);	/*ETHSD.INIT_STAT */  in tn40_set_link_speed()
1011 			val = tn40_read_reg(priv, 0x1014);  in tn40_set_link_speed()
1014 				tn40_write_reg(priv, 0x1014, 0x3);  in tn40_set_link_speed()
1016 				val = tn40_read_reg(priv, 0x1014);  in tn40_set_link_speed()
1024 		tn40_write_reg(priv, 0x6350, 0x0);	/*MAC.PCS_IF_MODE */  in tn40_set_link_speed()
1025 		tn40_write_reg(priv, TN40_REG_CTRLST, 0xC13);	/*0x93//0x13 */  in tn40_set_link_speed()
1026 		tn40_write_reg(priv, 0x111c, 0x7ff);	/*MAC.MAC_RST_CNT */  in tn40_set_link_speed()
1029 		tn40_write_reg(priv, 0x111c, 0x0);	/*MAC.MAC_RST_CNT */  in tn40_set_link_speed()
1034 		tn40_write_reg(priv, 0x1010, 0x613);	/*ETHSD.REFCLK_CONF */  in tn40_set_link_speed()
1035 		tn40_write_reg(priv, 0x104c, 0x4d);	/*ETHSD.L0_RX_PCNT  */  in tn40_set_link_speed()
1036 		tn40_write_reg(priv, 0x1050, 0x0);	/*ETHSD.L1_RX_PCNT  */  in tn40_set_link_speed()
1037 		tn40_write_reg(priv, 0x1054, 0x0);	/*ETHSD.L2_RX_PCNT  */  in tn40_set_link_speed()
1038 		tn40_write_reg(priv, 0x1058, 0x0);	/*ETHSD.L3_RX_PCNT  */  in tn40_set_link_speed()
1039 		tn40_write_reg(priv, 0x102c, 0x35);	/*ETHSD.L0_TX_PCNT  */  in tn40_set_link_speed()
1040 		tn40_write_reg(priv, 0x1030, 0x0);	/*ETHSD.L1_TX_PCNT  */  in tn40_set_link_speed()
1041 		tn40_write_reg(priv, 0x1034, 0x0);	/*ETHSD.L2_TX_PCNT  */  in tn40_set_link_speed()
1042 		tn40_write_reg(priv, 0x1038, 0x0);	/*ETHSD.L3_TX_PCNT  */  in tn40_set_link_speed()
1043 		tn40_write_reg(priv, 0x6300, 0x01140);	/*MAC.PCS_CTRL */  in tn40_set_link_speed()
1045 		tn40_write_reg(priv, 0x1014, 0x043);	/*ETHSD.INIT_STAT */  in tn40_set_link_speed()
1048 			val = tn40_read_reg(priv, 0x1014); /*ETHSD.INIT_STAT */  in tn40_set_link_speed()
1051 				tn40_write_reg(priv, 0x1014, 0x3);  in tn40_set_link_speed()
1053 				val = tn40_read_reg(priv, 0x1014);  in tn40_set_link_speed()
1061 		tn40_write_reg(priv, 0x6350, 0x2b);	/*MAC.PCS_IF_MODE 1g */  in tn40_set_link_speed()
1062 		tn40_write_reg(priv, 0x6310, 0x9801);	/*MAC.PCS_DEV_AB */  in tn40_set_link_speed()
1064 		tn40_write_reg(priv, 0x6314, 0x1);	/*MAC.PCS_PART_AB */  in tn40_set_link_speed()
1065 		tn40_write_reg(priv, 0x6348, 0xc8);	/*MAC.PCS_LINK_LO */  in tn40_set_link_speed()
1066 		tn40_write_reg(priv, 0x634c, 0xc8);	/*MAC.PCS_LINK_HI */  in tn40_set_link_speed()
1068 		tn40_write_reg(priv, TN40_REG_CTRLST, 0xC13);	/*0x93//0x13 */  in tn40_set_link_speed()
1069 		tn40_write_reg(priv, 0x111c, 0x7ff);	/*MAC.MAC_RST_CNT */  in tn40_set_link_speed()
1072 		tn40_write_reg(priv, 0x111c, 0x0);	/*MAC.MAC_RST_CNT */  in tn40_set_link_speed()
1073 		tn40_write_reg(priv, 0x6300, 0x1140);	/*MAC.PCS_CTRL */  in tn40_set_link_speed()
1076 	case 0:		/* Link down */  in tn40_set_link_speed()
1077 		tn40_write_reg(priv, 0x104c, 0x0);	/*ETHSD.L0_RX_PCNT  */  in tn40_set_link_speed()
1078 		tn40_write_reg(priv, 0x1050, 0x0);	/*ETHSD.L1_RX_PCNT  */  in tn40_set_link_speed()
1079 		tn40_write_reg(priv, 0x1054, 0x0);	/*ETHSD.L2_RX_PCNT  */  in tn40_set_link_speed()
1080 		tn40_write_reg(priv, 0x1058, 0x0);	/*ETHSD.L3_RX_PCNT  */  in tn40_set_link_speed()
1081 		tn40_write_reg(priv, 0x102c, 0x0);	/*ETHSD.L0_TX_PCNT  */  in tn40_set_link_speed()
1082 		tn40_write_reg(priv, 0x1030, 0x0);	/*ETHSD.L1_TX_PCNT  */  in tn40_set_link_speed()
1083 		tn40_write_reg(priv, 0x1034, 0x0);	/*ETHSD.L2_TX_PCNT  */  in tn40_set_link_speed()
1084 		tn40_write_reg(priv, 0x1038, 0x0);	/*ETHSD.L3_TX_PCNT  */  in tn40_set_link_speed()
1086 		tn40_write_reg(priv, TN40_REG_CTRLST, 0x800);  in tn40_set_link_speed()
1087 		tn40_write_reg(priv, 0x111c, 0x7ff);	/*MAC.MAC_RST_CNT */  in tn40_set_link_speed()
1090 		tn40_write_reg(priv, 0x111c, 0x0);	/*MAC.MAC_RST_CNT */  in tn40_set_link_speed()
1096 		speed = 0;  in tn40_set_link_speed()
1113 		netdev_dbg(priv->ndev, "isr = 0x%x\n", isr);  in tn40_isr_extra()
1140 		 * tn40_poll: tn40_enable_interrupts(priv); return 0;  in tn40_isr_napi()
1163 		return 0;  in tn40_poll()
1197 		netdev_dbg(priv->ndev, "VPC: 0x%x VIC: 0x%x STATUS: 0x%xd\n",  in tn40_fw_load()
1218 	val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);  in tn40_restore_mac()
1228 		       (ndev->dev_addr[1] << 8) | (ndev->dev_addr[0]));  in tn40_restore_mac()
1240 	tn40_write_reg(priv, TN40_REG_FRM_LENGTH, 0X3FE0);  in tn40_hw_start()
1241 	tn40_write_reg(priv, TN40_REG_GMAC_RXF_A, 0X10fd);  in tn40_hw_start()
1243 	/*L0: 0x103c , L1: 0x1040 , L2: 0x1044 , L3: 0x1048 =0x81644 */  in tn40_hw_start()
1244 	tn40_write_reg(priv, 0x103c, 0x81644);	/*ETHSD.L0_TX_DCNT  */  in tn40_hw_start()
1245 	tn40_write_reg(priv, 0x1040, 0x81644);	/*ETHSD.L1_TX_DCNT  */  in tn40_hw_start()
1246 	tn40_write_reg(priv, 0x1044, 0x81644);	/*ETHSD.L2_TX_DCNT  */  in tn40_hw_start()
1247 	tn40_write_reg(priv, 0x1048, 0x81644);	/*ETHSD.L3_TX_DCNT  */  in tn40_hw_start()
1248 	tn40_write_reg(priv, TN40_REG_RX_FIFO_SECTION, 0x10);  in tn40_hw_start()
1249 	tn40_write_reg(priv, TN40_REG_TX_FIFO_SECTION, 0xE00010);  in tn40_hw_start()
1250 	tn40_write_reg(priv, TN40_REG_RX_FULLNESS, 0);  in tn40_hw_start()
1251 	tn40_write_reg(priv, TN40_REG_TX_FULLNESS, 0);  in tn40_hw_start()
1253 	tn40_write_reg(priv, TN40_REG_VGLB, 0);  in tn40_hw_start()
1257 	tn40_write_reg(priv, TN40_REG_RDINTCM2, 0);  in tn40_hw_start()
1259 	/* old val = 0x300064 */  in tn40_hw_start()
1266 	tn40_write_reg(priv, 0x12E0, 0x28);  in tn40_hw_start()
1267 	tn40_write_reg(priv, TN40_REG_PAUSE_QUANT, 0xFFFF);  in tn40_hw_start()
1268 	tn40_write_reg(priv, 0x6064, 0xF);  in tn40_hw_start()
1281 	/* Reset sequences: read, write 1, read, write 0 */  in tn40_hw_reset()
1283 	tn40_write_reg(priv, TN40_REG_CLKPLL, (val | TN40_CLKPLL_SFTRST) + 0x8);  in tn40_hw_reset()
1298 	return 0;  in tn40_hw_reset()
1308 	tn40_write_reg(priv, TN40_REG_GMAC_RXF_A, 0);  in tn40_sw_reset()
1321 	tn40_write_reg(priv, TN40_REG_RDINTCM0, 0);  in tn40_sw_reset()
1322 	tn40_write_reg(priv, TN40_REG_TDINTCM0, 0);  in tn40_sw_reset()
1323 	tn40_write_reg(priv, TN40_REG_IMR, 0);  in tn40_sw_reset()
1331 	for (i = TN40_REG_TXD_WPTR_0; i <= TN40_REG_TXF_RPTR_3; i += 0x10)  in tn40_sw_reset()
1332 		tn40_write_reg(priv, i, 0);  in tn40_sw_reset()
1334 	tn40_write_reg(priv, TN40_REG_DIS_PORT, 0);  in tn40_sw_reset()
1336 	tn40_write_reg(priv, TN40_REG_DIS_QU, 0);  in tn40_sw_reset()
1338 	tn40_write_reg(priv, TN40_REG_RST_QU, 0);  in tn40_sw_reset()
1340 	tn40_write_reg(priv, TN40_REG_RST_PORT, 0);  in tn40_sw_reset()
1376 	return 0;  in tn40_start()
1403 	return 0;  in tn40_close()
1426 	return 0;  in tn40_open()
1452 	return 0;  in tn40_vlan_rx_add_vid()
1458 	__tn40_vlan_rx_vid(ndev, vid, 0);  in tn40_vlan_rx_kill_vid()
1459 	return 0;  in tn40_vlan_rx_kill_vid()
1477 		for (i = 0; i < TN40_MAC_MCST_HASH_NUM; i++)  in tn40_setmulti()
1479 				       TN40_REG_RX_MCST_HASH0 + i * 4, ~0);  in tn40_setmulti()
1486 		for (i = 0; i < TN40_MAC_MCST_HASH_NUM; i++)  in tn40_setmulti()
1488 				       TN40_REG_RX_MCST_HASH0 + i * 4, 0);  in tn40_setmulti()
1491 		for (i = 0; i < TN40_MAC_MCST_NUM; i++) {  in tn40_setmulti()
1493 				       TN40_REG_RX_MAC_MCST0 + i * 8, 0);  in tn40_setmulti()
1495 				       TN40_REG_RX_MAC_MCST1 + i * 8, 0);  in tn40_setmulti()
1505 			hash = 0;  in tn40_setmulti()
1506 			for (i = 0; i < ETH_ALEN; i++)  in tn40_setmulti()
1529 	return 0;  in tn40_set_mac()
1622 	rx->packets = 0;  in tn40_get_base_stats()
1623 	rx->bytes = 0;  in tn40_get_base_stats()
1624 	rx->alloc_fail = 0;  in tn40_get_base_stats()
1626 	tx->packets = 0;  in tn40_get_base_stats()
1627 	tx->bytes = 0;  in tn40_get_base_stats()
1640 	tn40_set_link_speed(priv, 0);  in tn40_priv_init()
1642 	/* Set GPIO[9:0] to output 0 */  in tn40_priv_init()
1643 	tn40_write_reg(priv, 0x51E0, 0x30010006);	/* GPIO_OE_ WR CMD */  in tn40_priv_init()
1644 	tn40_write_reg(priv, 0x51F0, 0x0);	/* GPIO_OE_ DATA */  in tn40_priv_init()
1645 	tn40_write_reg(priv, TN40_REG_MDIO_CMD_STAT, 0x3ec8);  in tn40_priv_init()
1667 	ndev->mem_start = pci_resource_start(pdev, 0);  in tn40_netdev_alloc()
1668 	ndev->mem_end = pci_resource_end(pdev, 0);  in tn40_netdev_alloc()
1721 	regs = pci_iomap(pdev, 0, TN40_REGS_SIZE);  in tn40_probe()
1748 	priv->rdintcm = TN40_INT_REG_VAL(0x20, 1, 4, 12);  in tn40_probe()
1749 	priv->tdintcm = TN40_INT_REG_VAL(0x20, 1, 0, 12);  in tn40_probe()
1758 	if (ret < 0) {  in tn40_probe()
1770 		((tn40_read_reg(priv, TN40_FPGA_VER) & 0xFFF) != 308);  in tn40_probe()
1795 	return 0;  in tn40_probe()
1827 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022,
1828 			 PCI_VENDOR_ID_TEHUTI, 0x3015) },
1829 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022,
1830 			 PCI_VENDOR_ID_DLINK, 0x4d00) },
1831 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022,
1832 			 PCI_VENDOR_ID_ASUSTEK, 0x8709) },
1833 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022,
1834 			 PCI_VENDOR_ID_EDIMAX, 0x8103) },