66 	{ PCI_VDEVICE(TEHUTI, 0x3009), },
67 	{ PCI_VDEVICE(TEHUTI, 0x3010), },
68 	{ PCI_VDEVICE(TEHUTI, 0x3014), },
69 	{ 0 }
100 	u16 pci_link_status = 0;  in print_hw_id()
101 	u16 pci_ctrl = 0;  in print_hw_id()
108 	pr_info("srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n",  in print_hw_id()
109 		readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,  in print_hw_id()
117 	pr_info("fw 0x%x\n", readl(nic->regs + FW_VER));  in print_fw_id()
123 		    BDX_NIC_NAME, (ndev->if_port == 0) ? 'A' : 'B');  in print_eth_id()
132 	do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
134 	do { WRITE_REG(priv, regIMR, 0); } while (0)
140  * @fsz_type: fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
149  * Returns 0 on success, negative value on failure
158 	memset(f, 0, sizeof(struct fifo));  in bdx_fifo_init()
170 	f->rptr = 0;  in bdx_fifo_init()
171 	f->wptr = 0;  in bdx_fifo_init()
177 	RET(0);  in bdx_fifo_init()
275 			 *    return 0;  in bdx_isr_napi()
303 		priv->napi_stop = 0;  in bdx_poll()
336 	for (i = 0; i < 200; i++) {  in bdx_fw_load()
338 			rc = 0;  in bdx_fw_load()
353 			DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",  in bdx_fw_load()
360 		RET(0);  in bdx_fw_load()
373 	val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);  in bdx_restore_mac()
399 	WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);  in bdx_hw_start()
400 	WRITE_REG(priv, regPAUSE_QUANT, 0x96);  in bdx_hw_start()
401 	WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);  in bdx_hw_start()
402 	WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);  in bdx_hw_start()
403 	WRITE_REG(priv, regRX_FULLNESS, 0);  in bdx_hw_start()
404 	WRITE_REG(priv, regTX_FULLNESS, 0);  in bdx_hw_start()
408 	WRITE_REG(priv, regVGLB, 0);  in bdx_hw_start()
414 	WRITE_REG(priv, regRDINTCM2, 0);	/*cpu_to_le32(rcm.val)); */  in bdx_hw_start()
417 	WRITE_REG(priv, regTDINTCM0, priv->tdintcm);	/* old val = 0x300064 */  in bdx_hw_start()
426 #define BDX_IRQ_TYPE	((priv->nic->irq_type == IRQ_MSI) ? 0 : IRQF_SHARED)  in bdx_hw_start()
434 	RET(0);  in bdx_hw_start()
457 	/* reset sequences: read, write 1, read, write 0 */  in bdx_hw_reset_direct()
459 	writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);  in bdx_hw_reset_direct()
465 	for (i = 0; i < 70; i++, mdelay(10))  in bdx_hw_reset_direct()
469 			return 0;  in bdx_hw_reset_direct()
480 	if (priv->port == 0) {  in bdx_hw_reset()
481 		/* reset sequences: read, write 1, read, write 0 */  in bdx_hw_reset()
483 		WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);  in bdx_hw_reset()
489 	for (i = 0; i < 70; i++, mdelay(10))  in bdx_hw_reset()
493 			return 0;  in bdx_hw_reset()
506 	WRITE_REG(priv, regGMAC_RXF_A, 0);  in bdx_sw_reset()
513 	for (i = 0; i < 50; i++) {  in bdx_sw_reset()
522 	WRITE_REG(priv, regRDINTCM0, 0);  in bdx_sw_reset()
523 	WRITE_REG(priv, regTDINTCM0, 0);  in bdx_sw_reset()
524 	WRITE_REG(priv, regIMR, 0);  in bdx_sw_reset()
532 	for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)  in bdx_sw_reset()
534 	for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)  in bdx_sw_reset()
535 		WRITE_REG(priv, i, 0);  in bdx_sw_reset()
537 	WRITE_REG(priv, regDIS_PORT, 0);  in bdx_sw_reset()
539 	WRITE_REG(priv, regDIS_QU, 0);  in bdx_sw_reset()
541 	WRITE_REG(priv, regRST_QU, 0);  in bdx_sw_reset()
543 	WRITE_REG(priv, regRST_PORT, 0);  in bdx_sw_reset()
547 	for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)  in bdx_sw_reset()
550 	RET(0);  in bdx_sw_reset()
557 	RET((priv->pdev->device == 0x3009)  in bdx_reset()
566  * Returns 0, this is not allowed to fail
586 	RET(0);  in bdx_close()
593  * Returns 0 on success, negative value on failure
627 	RET(0);  in bdx_open()
637 		-EINVAL : 0;  in bdx_range_check()
656 		DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);  in bdx_siocdevprivate()
664 	switch (data[0]) {  in bdx_siocdevprivate()
668 		if (error < 0)  in bdx_siocdevprivate()
671 		DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],  in bdx_siocdevprivate()
680 		if (error < 0)  in bdx_siocdevprivate()
683 		DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);  in bdx_siocdevprivate()
689 	return 0;  in bdx_siocdevprivate()
733 	return 0;  in bdx_vlan_rx_add_vid()
744 	__bdx_vlan_rx_vid(ndev, vid, 0);  in bdx_vlan_rx_kill_vid()
745 	return 0;  in bdx_vlan_rx_kill_vid()
753  * Returns 0 on success, negative on failure
764 	RET(0);  in bdx_change_mtu()
784 		for (i = 0; i < MAC_MCST_HASH_NUM; i++)  in bdx_setmulti()
785 			WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);  in bdx_setmulti()
792 		for (i = 0; i < MAC_MCST_HASH_NUM; i++)  in bdx_setmulti()
793 			WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);  in bdx_setmulti()
795 		for (i = 0; i < MAC_MCST_NUM; i++) {  in bdx_setmulti()
796 			WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);  in bdx_setmulti()
797 			WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);  in bdx_setmulti()
806 			hash = 0;  in bdx_setmulti()
807 			for (i = 0; i < ETH_ALEN; i++)  in bdx_setmulti()
837 	RET(0);  in bdx_set_mac()
850 	macAddress[0] = READ_REG(priv, regUNC_MAC2_A);  in bdx_read_mac()
851 	macAddress[0] = READ_REG(priv, regUNC_MAC2_A);  in bdx_read_mac()
852 	for (i = 0; i < 3; i++) {  in bdx_read_mac()
857 	RET(0);  in bdx_read_mac()
878 	addr = 0x7200;  in bdx_update_stats()
879 	/*First 12 statistics - 0x7200 - 0x72B0 */  in bdx_update_stats()
880 	for (i = 0; i < 12; i++) {  in bdx_update_stats()
882 		addr += 0x10;  in bdx_update_stats()
884 	BDX_ASSERT(addr != 0x72C0);  in bdx_update_stats()
885 	/* 0x72C0-0x72E0 RSRV */  in bdx_update_stats()
886 	addr = 0x72F0;  in bdx_update_stats()
889 		addr += 0x10;  in bdx_update_stats()
891 	BDX_ASSERT(addr != 0x7330);  in bdx_update_stats()
892 	/* 0x7330-0x7360 RSRV */  in bdx_update_stats()
893 	addr = 0x7370;  in bdx_update_stats()
896 		addr += 0x10;  in bdx_update_stats()
898 	BDX_ASSERT(addr != 0x73A0);  in bdx_update_stats()
899 	/* 0x73A0-0x73B0 RSRV */  in bdx_update_stats()
900 	addr = 0x73C0;  in bdx_update_stats()
903 		addr += 0x10;  in bdx_update_stats()
905 	BDX_ASSERT(addr != 0x7400);  in bdx_update_stats()
935 		for (i = 0; i < nelem; i++)  in bdx_rxdb_create()
945 	BDX_ASSERT(db->top <= 0);  in bdx_rxdb_alloc_elem()
951 	BDX_ASSERT((n < 0) || (n >= db->nelem));  in bdx_rxdb_addr_elem()
962 	BDX_ASSERT((n >= db->nelem) || (n < 0));  in bdx_rxdb_free_elem()
974  * Returns 0 on success, negative value on failure
983  * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
1006 	return 0;  in bdx_rx_init()
1027 	while (bdx_rxdb_available(db) > 0) {  in bdx_rx_free_skbs()
1030 		dm->dma = 0;  in bdx_rx_free_skbs()
1032 	for (i = 0; i < db->nelem; i++) {  in bdx_rx_free_skbs()
1089 	while (dno > 0) {  in bdx_rx_alloc_skbs()
1102 		rxfd->info = CPU_CHIP_SWAP32(0x10003);	/* INFO=1 BC=3 */  in bdx_rx_alloc_skbs()
1111 		if (unlikely(delta >= 0)) {  in bdx_rx_alloc_skbs()
1113 			if (delta > 0) {  in bdx_rx_alloc_skbs()
1157 	rxfd->info = CPU_CHIP_SWAP32(0x10003);	/* INFO=1 BC=3 */  in bdx_recycle_skb()
1166 	if (unlikely(delta >= 0)) {  in bdx_recycle_skb()
1168 		if (delta > 0) {  in bdx_recycle_skb()
1197 	int done = 0;  in bdx_rx_receive()
1211 	if (size < 0)  in bdx_rx_receive()
1214 	while (size > 0) {  in bdx_rx_receive()
1226 		BDX_ASSERT(tmp_len <= 0);  in bdx_rx_receive()
1228 		if (size < 0)	/* test for partially arrived descriptor */  in bdx_rx_receive()
1234 		if (unlikely(tmp_len >= 0)) {  in bdx_rx_receive()
1236 			if (tmp_len > 0) {  in bdx_rx_receive()
1244 			DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));  in bdx_rx_receive()
1277 		if (GET_RXD_PKT_ID(rxd_val1) == 0)  in bdx_rx_receive()
1316 	    "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",  in print_rxfd()
1407  * Returns 0 on success, error code otherwise
1429 	return 0;  in bdx_tx_db_init()
1472 	struct pbl *pbl = &txdd->pbl[0];  in bdx_tx_map_skb()
1482 	DBG("=== pbl   len: 0x%x ================\n", pbl->len);  in bdx_tx_map_skb()
1483 	DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);  in bdx_tx_map_skb()
1484 	DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);  in bdx_tx_map_skb()
1487 	for (i = 0; i < nr_frags; i++) {  in bdx_tx_map_skb()
1493 						      0, skb_frag_size(frag),  in bdx_tx_map_skb()
1518 	for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {  in init_txd_sizes()
1549 	return 0;  in bdx_tx_init()
1569 	if (fsize <= 0)  in bdx_tx_space()
1590 	int txd_lgsnd = 0;  in bdx_tx_transmit()
1591 	int txd_vlan_id = 0;  in bdx_tx_transmit()
1592 	int txd_vtag = 0;  in bdx_tx_transmit()
1593 	int txd_mss = 0;  in bdx_tx_transmit()
1608 		txd_checksum = 0;  in bdx_tx_transmit()
1630 	DBG("=== w1: 0x%x ================\n", txdd->txd_val1);  in bdx_tx_transmit()
1631 	DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);  in bdx_tx_transmit()
1640 	if (unlikely(len >= 0)) {  in bdx_tx_transmit()
1642 		if (len > 0) {  in bdx_tx_transmit()
1650 	BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);  in bdx_tx_transmit()
1660 			priv->tx_noupd = 0;  in bdx_tx_transmit()
1700 	int tx_level = 0;  in bdx_tx_cleanup()
1712 		BDX_ASSERT(db->rptr->len == 0);  in bdx_tx_cleanup()
1714 			BDX_ASSERT(db->rptr->addr.dma == 0);  in bdx_tx_cleanup()
1718 		} while (db->rptr->len > 0);  in bdx_tx_cleanup()
1734 	BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);  in bdx_tx_cleanup()
1737 		priv->tx_noupd = 0;  in bdx_tx_cleanup()
1801 	if (size == 0)  in bdx_tx_push_desc()
1826 	int timer = 0;  in bdx_tx_push_desc_safe()
1829 	while (size > 0) {  in bdx_tx_push_desc_safe()
1834 		if (avail <= 0) {  in bdx_tx_push_desc_safe()
1870  * Returns 0 on success, negative on failure
1915 	pciaddr = pci_resource_start(pdev, 0);  in bdx_probe()
1921 	regionSize = pci_resource_len(pdev, 0);  in bdx_probe()
1942 	if (pdev->device == 0x3014)  in bdx_probe()
1953 	if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {  in bdx_probe()
1964 	for (port = 0; port < nic->port_num; port++) {  in bdx_probe()
1990 		priv->pBdxRegs = nic->regs + port * 0x8000;  in bdx_probe()
1999 		if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {  in bdx_probe()
2001 			priv->stats_flag = 0;  in bdx_probe()
2013 		priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);  in bdx_probe()
2014 		priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);  in bdx_probe()
2047 	RET(0);  in bdx_probe()
2067 	"InUCast",		/* 0x7200 */
2068 	"InMCast",		/* 0x7210 */
2069 	"InBCast",		/* 0x7220 */
2070 	"InPkts",		/* 0x7230 */
2071 	"InErrors",		/* 0x7240 */
2072 	"InDropped",		/* 0x7250 */
2073 	"FrameTooLong",		/* 0x7260 */
2074 	"FrameSequenceErrors",	/* 0x7270 */
2075 	"InVLAN",		/* 0x7280 */
2076 	"InDroppedDFE",		/* 0x7290 */
2077 	"InDroppedIntFull",	/* 0x72A0 */
2078 	"InFrameAlignErrors",	/* 0x72B0 */
2080 	/* 0x72C0-0x72E0 RSRV */
2082 	"OutUCast",		/* 0x72F0 */
2083 	"OutMCast",		/* 0x7300 */
2084 	"OutBCast",		/* 0x7310 */
2085 	"OutPkts",		/* 0x7320 */
2087 	/* 0x7330-0x7360 RSRV */
2089 	"OutVLAN",		/* 0x7370 */
2090 	"InUCastOctects",	/* 0x7380 */
2091 	"OutUCastOctects",	/* 0x7390 */
2093 	/* 0x73A0-0x73B0 RSRV */
2095 	"InBCastOctects",	/* 0x73C0 */
2096 	"OutBCastOctects",	/* 0x73D0 */
2097 	"InOctects",		/* 0x73E0 */
2098 	"OutOctects",		/* 0x73F0 */
2123 	return 0;  in bdx_get_link_ksettings()
2171 	return 0;  in bdx_get_coalesce()
2206 	if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF) ||  in bdx_set_coalesce()
2207 	    (rx_max_coal > 0xF) || (tx_max_coal > 0xF))  in bdx_set_coalesce()
2212 	tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,  in bdx_set_coalesce()
2221 	return 0;  in bdx_set_coalesce()
2270 	int rx_size = 0;  in bdx_set_ringparam()
2271 	int tx_size = 0;  in bdx_set_ringparam()
2290 		return 0;  in bdx_set_ringparam()
2304 	return 0;  in bdx_set_ringparam()
2333 		return (priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names)	: 0;  in bdx_get_sset_count()
2399 	for (port = 0; port < nic->port_num; port++) {  in bdx_remove()