Lines Matching +full:5 +full:b00
45 * DEFAULT: 0x0, SIZE: 5 bits
178 * DEFAULT: 0bxx000, SIZE: 5 bits
233 0b00: RD_PCI_WAT
237 0b00: AD_IDL_RX
242 0b00: WR_PCI_WAT
461 0b00: tx mac req,
533 * 5 TX_COMPLETE_3_LSB
619 #define RX_CFG_COMP_RING_SHIFT 5
659 0b00 = 2k, 0b01 = 4k
671 0b00 = 1k, 0b01 = 2k
678 0b00 = 0,
1074 /* access to RX Instruction RAM. 5-bit register/counter holds addr
1082 #define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */
1139 * FLOW_DB(5) = IP_DA[127:96], FLOW_DB(6) = IP_DA[95:64]
1556 * 5*x 16 LSB "" [15:0]
1567 * alt addr 1 reg 5 reg 4 reg 3
1568 * alt addr x reg 5*x reg 4*x reg 3*x
1906 pattern, D21.5
2017 * 0b00 undergoing reset
2149 #define LD_R1 5
2167 #define S1_LLCc 5
2839 #define LINK_TRANSITION_LINK_DOWN 5