Lines Matching +full:0 +full:xb00

14 #define PTP_XGMAC_OFFSET	0xd00
15 #define	PTP_GMAC4_OFFSET	0xb00
16 #define	PTP_GMAC3_X_OFFSET	0x700
19 #define	PTP_TCR		0x00	/* Timestamp Control Reg */
20 #define	PTP_SSIR	0x04	/* Sub-Second Increment Reg */
21 #define	PTP_STSR	0x08	/* System Time – Seconds Regr */
22 #define	PTP_STNSR	0x0c	/* System Time – Nanoseconds Reg */
23 #define	PTP_STSUR	0x10	/* System Time – Seconds Update Reg */
24 #define	PTP_STNSUR	0x14	/* System Time – Nanoseconds Update Reg */
25 #define	PTP_TAR		0x18	/* Timestamp Addend Reg */
26 #define	PTP_ACR		0x40	/* Auxiliary Control Reg */
27 #define	PTP_ATNR	0x48	/* Auxiliary Timestamp - Nanoseconds Reg */
28 #define	PTP_ATSR	0x4c	/* Auxiliary Timestamp - Seconds Reg */
29 #define	PTP_TS_INGR_CORR_NS	0x58	/* Ingress timestamp correction nanoseconds */
30 #define	PTP_TS_EGR_CORR_NS	0x5C	/* Egress timestamp correction nanoseconds*/
31 #define	PTP_TS_INGR_CORR_SNS	0x60	/* Ingress timestamp correction subnanoseconds */
32 #define	PTP_TS_EGR_CORR_SNS	0x64	/* Egress timestamp correction subnanoseconds */
33 #define	PTP_TS_INGR_LAT	0x68	/* MAC internal Ingress Latency */
34 #define	PTP_TS_EGR_LAT	0x6c	/* MAC internal Egress Latency */
37 #define	PTP_DIGITAL_ROLLOVER_MODE	0x3B9ACA00	/* 10e9-1 ns */
38 #define	PTP_BINARY_ROLLOVER_MODE	0x80000000	/* ~0.466 ns */
41 #define	PTP_TCR_TSENA		BIT(0)	/* Timestamp Enable */
73 #define	PTP_SSIR_SSINC_MAX		0xff
77 #define	PTP_ACR_ATSFC		BIT(0)	/* Auxiliary Snapshot FIFO Clear */
78 #define	PTP_ACR_ATSEN0		BIT(4)	/* Auxiliary Snapshot 0 Enable */
84 #define	PMC_ART_VALUE0		0x01	/* PMC_ART[15:0] timer value */
85 #define	PMC_ART_VALUE1		0x02	/* PMC_ART[31:16] timer value */
86 #define	PMC_ART_VALUE2		0x03	/* PMC_ART[47:32] timer value */
87 #define	PMC_ART_VALUE3		0x04	/* PMC_ART[63:48] timer value */
91 	AUX_SNAPSHOT0 = 0x10,
92 	AUX_SNAPSHOT1 = 0x20,
93 	AUX_SNAPSHOT2 = 0x40,
94 	AUX_SNAPSHOT3 = 0x80,