Lines Matching +full:v +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dwmac-sun8i.c - Allwinner sun8i DWMAC specific glue layer
11 #include <linux/mdio-mux.h>
28 /* General notes on dwmac-sun8i:
33 /* struct emac_variant - Describe dwmac-sun8i hardware variant
61 /* struct sunxi_priv_data - hold all sunxi private data
69 * @mux_handle: Internal pointer used by mdio-mux lib
147 * co-packaged AC200 chip instead.
181 #define EMAC_DUPLEX_FULL BIT(0)
182 #define EMAC_LOOPBACK BIT(1)
191 #define EMAC_FRM_FLT_RXALL BIT(0)
192 #define EMAC_FRM_FLT_CTL BIT(13)
193 #define EMAC_FRM_FLT_MULTICAST BIT(16)
196 #define EMAC_RX_MD BIT(1)
202 #define EMAC_RX_DMA_EN BIT(30)
203 #define EMAC_RX_DMA_START BIT(31)
206 #define EMAC_TX_MD BIT(1)
207 #define EMAC_TX_NEXT_FRM BIT(2)
213 #define EMAC_TX_DMA_EN BIT(30)
214 #define EMAC_TX_DMA_START BIT(31)
217 #define EMAC_RX_RECEIVER_EN BIT(31)
218 #define EMAC_RX_DO_CRC BIT(27)
219 #define EMAC_RX_FLOW_CTL_EN BIT(16)
222 #define EMAC_TX_TRANSMITTER_EN BIT(31)
225 #define EMAC_TX_FLOW_CTL_EN BIT(0)
228 #define EMAC_TX_INT BIT(0)
229 #define EMAC_TX_DMA_STOP_INT BIT(1)
230 #define EMAC_TX_BUF_UA_INT BIT(2)
231 #define EMAC_TX_TIMEOUT_INT BIT(3)
232 #define EMAC_TX_UNDERFLOW_INT BIT(4)
233 #define EMAC_TX_EARLY_INT BIT(5)
234 #define EMAC_RX_INT BIT(8)
235 #define EMAC_RX_BUF_UA_INT BIT(9)
236 #define EMAC_RX_DMA_STOP_INT BIT(10)
237 #define EMAC_RX_TIMEOUT_INT BIT(11)
238 #define EMAC_RX_OVERFLOW_INT BIT(12)
239 #define EMAC_RX_EARLY_INT BIT(13)
240 #define EMAC_RGMII_STA_INT BIT(16)
258 #define MAC_ADDR_TYPE_DST BIT(31)
262 #define H3_EPHY_CLK_SEL BIT(18) /* 1: 24MHz, 0: 25MHz */
263 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
264 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
265 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
271 #define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
277 #define SYSCON_EPIT BIT(2) /* 1: RGMII, 0: MII */
283 /* sun8i_dwmac_dma_reset() - reset the EMAC
284 * Called from stmmac via stmmac_dma_ops->reset
298 /* sun8i_dwmac_dma_init() - initialize the EMAC
299 * Called from stmmac via stmmac_dma_ops->init
326 /* sun8i_dwmac_dump_regs() - Dump EMAC address space
327 * Called from stmmac_dma_ops->dump_regs
342 /* sun8i_dwmac_dump_mac_regs() - Dump EMAC address space
343 * Called from stmmac_ops->dump_regs
350 void __iomem *ioaddr = hw->pcsr; in sun8i_dwmac_dump_mac_regs()
390 u32 v; in sun8i_dwmac_dma_start_tx() local
392 v = readl(ioaddr + EMAC_TX_CTL1); in sun8i_dwmac_dma_start_tx()
393 v |= EMAC_TX_DMA_START; in sun8i_dwmac_dma_start_tx()
394 v |= EMAC_TX_DMA_EN; in sun8i_dwmac_dma_start_tx()
395 writel(v, ioaddr + EMAC_TX_CTL1); in sun8i_dwmac_dma_start_tx()
400 u32 v; in sun8i_dwmac_enable_dma_transmission() local
402 v = readl(ioaddr + EMAC_TX_CTL1); in sun8i_dwmac_enable_dma_transmission()
403 v |= EMAC_TX_DMA_START; in sun8i_dwmac_enable_dma_transmission()
404 v |= EMAC_TX_DMA_EN; in sun8i_dwmac_enable_dma_transmission()
405 writel(v, ioaddr + EMAC_TX_CTL1); in sun8i_dwmac_enable_dma_transmission()
411 u32 v; in sun8i_dwmac_dma_stop_tx() local
413 v = readl(ioaddr + EMAC_TX_CTL1); in sun8i_dwmac_dma_stop_tx()
414 v &= ~EMAC_TX_DMA_EN; in sun8i_dwmac_dma_stop_tx()
415 writel(v, ioaddr + EMAC_TX_CTL1); in sun8i_dwmac_dma_stop_tx()
421 u32 v; in sun8i_dwmac_dma_start_rx() local
423 v = readl(ioaddr + EMAC_RX_CTL1); in sun8i_dwmac_dma_start_rx()
424 v |= EMAC_RX_DMA_START; in sun8i_dwmac_dma_start_rx()
425 v |= EMAC_RX_DMA_EN; in sun8i_dwmac_dma_start_rx()
426 writel(v, ioaddr + EMAC_RX_CTL1); in sun8i_dwmac_dma_start_rx()
432 u32 v; in sun8i_dwmac_dma_stop_rx() local
434 v = readl(ioaddr + EMAC_RX_CTL1); in sun8i_dwmac_dma_stop_rx()
435 v &= ~EMAC_RX_DMA_EN; in sun8i_dwmac_dma_stop_rx()
436 writel(v, ioaddr + EMAC_RX_CTL1); in sun8i_dwmac_dma_stop_rx()
444 struct stmmac_pcpu_stats *stats = this_cpu_ptr(priv->xstats.pcpu_stats); in sun8i_dwmac_dma_interrupt()
446 u32 v; in sun8i_dwmac_dma_interrupt() local
448 v = readl(ioaddr + EMAC_INT_STA); in sun8i_dwmac_dma_interrupt()
451 v &= EMAC_INT_MSK_RX; in sun8i_dwmac_dma_interrupt()
453 v &= EMAC_INT_MSK_TX; in sun8i_dwmac_dma_interrupt()
455 if (v & EMAC_TX_INT) { in sun8i_dwmac_dma_interrupt()
457 u64_stats_update_begin(&stats->syncp); in sun8i_dwmac_dma_interrupt()
458 u64_stats_inc(&stats->tx_normal_irq_n[chan]); in sun8i_dwmac_dma_interrupt()
459 u64_stats_update_end(&stats->syncp); in sun8i_dwmac_dma_interrupt()
462 if (v & EMAC_TX_DMA_STOP_INT) in sun8i_dwmac_dma_interrupt()
463 x->tx_process_stopped_irq++; in sun8i_dwmac_dma_interrupt()
465 if (v & EMAC_TX_BUF_UA_INT) in sun8i_dwmac_dma_interrupt()
466 x->tx_process_stopped_irq++; in sun8i_dwmac_dma_interrupt()
468 if (v & EMAC_TX_TIMEOUT_INT) in sun8i_dwmac_dma_interrupt()
471 if (v & EMAC_TX_UNDERFLOW_INT) { in sun8i_dwmac_dma_interrupt()
473 x->tx_undeflow_irq++; in sun8i_dwmac_dma_interrupt()
476 if (v & EMAC_TX_EARLY_INT) in sun8i_dwmac_dma_interrupt()
477 x->tx_early_irq++; in sun8i_dwmac_dma_interrupt()
479 if (v & EMAC_RX_INT) { in sun8i_dwmac_dma_interrupt()
481 u64_stats_update_begin(&stats->syncp); in sun8i_dwmac_dma_interrupt()
482 u64_stats_inc(&stats->rx_normal_irq_n[chan]); in sun8i_dwmac_dma_interrupt()
483 u64_stats_update_end(&stats->syncp); in sun8i_dwmac_dma_interrupt()
486 if (v & EMAC_RX_BUF_UA_INT) in sun8i_dwmac_dma_interrupt()
487 x->rx_buf_unav_irq++; in sun8i_dwmac_dma_interrupt()
489 if (v & EMAC_RX_DMA_STOP_INT) in sun8i_dwmac_dma_interrupt()
490 x->rx_process_stopped_irq++; in sun8i_dwmac_dma_interrupt()
492 if (v & EMAC_RX_TIMEOUT_INT) in sun8i_dwmac_dma_interrupt()
495 if (v & EMAC_RX_OVERFLOW_INT) { in sun8i_dwmac_dma_interrupt()
497 x->rx_overflow_irq++; in sun8i_dwmac_dma_interrupt()
500 if (v & EMAC_RX_EARLY_INT) in sun8i_dwmac_dma_interrupt()
501 x->rx_early_irq++; in sun8i_dwmac_dma_interrupt()
503 if (v & EMAC_RGMII_STA_INT) in sun8i_dwmac_dma_interrupt()
504 x->irq_rgmii_n++; in sun8i_dwmac_dma_interrupt()
506 writel(v, ioaddr + EMAC_INT_STA); in sun8i_dwmac_dma_interrupt()
515 u32 v; in sun8i_dwmac_dma_operation_mode_rx() local
517 v = readl(ioaddr + EMAC_RX_CTL1); in sun8i_dwmac_dma_operation_mode_rx()
519 v |= EMAC_RX_MD; in sun8i_dwmac_dma_operation_mode_rx()
521 v &= ~EMAC_RX_MD; in sun8i_dwmac_dma_operation_mode_rx()
522 v &= ~EMAC_RX_TH_MASK; in sun8i_dwmac_dma_operation_mode_rx()
524 v |= EMAC_RX_TH_32; in sun8i_dwmac_dma_operation_mode_rx()
526 v |= EMAC_RX_TH_64; in sun8i_dwmac_dma_operation_mode_rx()
528 v |= EMAC_RX_TH_96; in sun8i_dwmac_dma_operation_mode_rx()
530 v |= EMAC_RX_TH_128; in sun8i_dwmac_dma_operation_mode_rx()
532 writel(v, ioaddr + EMAC_RX_CTL1); in sun8i_dwmac_dma_operation_mode_rx()
539 u32 v; in sun8i_dwmac_dma_operation_mode_tx() local
541 v = readl(ioaddr + EMAC_TX_CTL1); in sun8i_dwmac_dma_operation_mode_tx()
543 v |= EMAC_TX_MD; in sun8i_dwmac_dma_operation_mode_tx()
544 /* Undocumented bit (called TX_NEXT_FRM in BSP), the original in sun8i_dwmac_dma_operation_mode_tx()
547 * especially when transmit store-and-forward is used." in sun8i_dwmac_dma_operation_mode_tx()
549 v |= EMAC_TX_NEXT_FRM; in sun8i_dwmac_dma_operation_mode_tx()
551 v &= ~EMAC_TX_MD; in sun8i_dwmac_dma_operation_mode_tx()
552 v &= ~EMAC_TX_TH_MASK; in sun8i_dwmac_dma_operation_mode_tx()
554 v |= EMAC_TX_TH_64; in sun8i_dwmac_dma_operation_mode_tx()
556 v |= EMAC_TX_TH_128; in sun8i_dwmac_dma_operation_mode_tx()
558 v |= EMAC_TX_TH_192; in sun8i_dwmac_dma_operation_mode_tx()
560 v |= EMAC_TX_TH_256; in sun8i_dwmac_dma_operation_mode_tx()
562 writel(v, ioaddr + EMAC_TX_CTL1); in sun8i_dwmac_dma_operation_mode_tx()
591 if (gmac->regulator) { in sun8i_dwmac_init()
592 ret = regulator_enable(gmac->regulator); in sun8i_dwmac_init()
594 dev_err(&pdev->dev, "Fail to enable regulator\n"); in sun8i_dwmac_init()
599 if (gmac->use_internal_phy) { in sun8i_dwmac_init()
608 if (gmac->regulator) in sun8i_dwmac_init()
609 regulator_disable(gmac->regulator); in sun8i_dwmac_init()
617 void __iomem *ioaddr = hw->pcsr; in sun8i_dwmac_core_init()
618 u32 v; in sun8i_dwmac_core_init() local
620 v = (8 << EMAC_BURSTLEN_SHIFT); /* burst len */ in sun8i_dwmac_core_init()
621 writel(v, ioaddr + EMAC_BASIC_CTL1); in sun8i_dwmac_core_init()
649 void __iomem *ioaddr = hw->pcsr; in sun8i_dwmac_set_umac_addr()
650 u32 v; in sun8i_dwmac_set_umac_addr() local
660 v = readl(ioaddr + EMAC_MACADDR_HI(reg_n)); in sun8i_dwmac_set_umac_addr()
661 v |= MAC_ADDR_TYPE_DST; in sun8i_dwmac_set_umac_addr()
662 writel(v, ioaddr + EMAC_MACADDR_HI(reg_n)); in sun8i_dwmac_set_umac_addr()
670 void __iomem *ioaddr = hw->pcsr; in sun8i_dwmac_get_umac_addr()
679 void __iomem *ioaddr = hw->pcsr; in sun8i_dwmac_rx_ipc_enable()
680 u32 v; in sun8i_dwmac_rx_ipc_enable() local
682 v = readl(ioaddr + EMAC_RX_CTL0); in sun8i_dwmac_rx_ipc_enable()
683 v |= EMAC_RX_DO_CRC; in sun8i_dwmac_rx_ipc_enable()
684 writel(v, ioaddr + EMAC_RX_CTL0); in sun8i_dwmac_rx_ipc_enable()
692 void __iomem *ioaddr = hw->pcsr; in sun8i_dwmac_set_filter()
693 u32 v; in sun8i_dwmac_set_filter() local
698 v = EMAC_FRM_FLT_CTL; in sun8i_dwmac_set_filter()
700 if (dev->flags & IFF_PROMISC) { in sun8i_dwmac_set_filter()
701 v = EMAC_FRM_FLT_RXALL; in sun8i_dwmac_set_filter()
702 } else if (dev->flags & IFF_ALLMULTI) { in sun8i_dwmac_set_filter()
703 v |= EMAC_FRM_FLT_MULTICAST; in sun8i_dwmac_set_filter()
704 } else if (macaddrs <= hw->unicast_filter_entries) { in sun8i_dwmac_set_filter()
707 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); in sun8i_dwmac_set_filter()
713 sun8i_dwmac_set_umac_addr(hw, ha->addr, i); in sun8i_dwmac_set_filter()
720 v = EMAC_FRM_FLT_RXALL; in sun8i_dwmac_set_filter()
724 while (i < hw->unicast_filter_entries) in sun8i_dwmac_set_filter()
727 writel(v, ioaddr + EMAC_RX_FRM_FLT); in sun8i_dwmac_set_filter()
734 void __iomem *ioaddr = hw->pcsr; in sun8i_dwmac_flow_ctrl()
735 u32 v; in sun8i_dwmac_flow_ctrl() local
737 v = readl(ioaddr + EMAC_RX_CTL0); in sun8i_dwmac_flow_ctrl()
739 v |= EMAC_RX_FLOW_CTL_EN; in sun8i_dwmac_flow_ctrl()
741 v &= ~EMAC_RX_FLOW_CTL_EN; in sun8i_dwmac_flow_ctrl()
742 writel(v, ioaddr + EMAC_RX_CTL0); in sun8i_dwmac_flow_ctrl()
744 v = readl(ioaddr + EMAC_TX_FLOW_CTL); in sun8i_dwmac_flow_ctrl()
746 v |= EMAC_TX_FLOW_CTL_EN; in sun8i_dwmac_flow_ctrl()
748 v &= ~EMAC_TX_FLOW_CTL_EN; in sun8i_dwmac_flow_ctrl()
749 writel(v, ioaddr + EMAC_TX_FLOW_CTL); in sun8i_dwmac_flow_ctrl()
754 u32 v; in sun8i_dwmac_reset() local
757 v = readl(priv->ioaddr + EMAC_BASIC_CTL1); in sun8i_dwmac_reset()
758 writel(v | 0x01, priv->ioaddr + EMAC_BASIC_CTL1); in sun8i_dwmac_reset()
763 err = readl_poll_timeout(priv->ioaddr + EMAC_BASIC_CTL1, v, in sun8i_dwmac_reset()
764 !(v & 0x01), 100, 100000); in sun8i_dwmac_reset()
767 dev_err(priv->device, "EMAC reset timeout\n"); in sun8i_dwmac_reset()
773 /* Search in mdio-mux node for internal PHY node and get its clk/reset */
776 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in get_ephy_nodes()
781 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); in get_ephy_nodes()
783 dev_err(priv->device, "Cannot get mdio-mux node\n"); in get_ephy_nodes()
784 return -ENODEV; in get_ephy_nodes()
788 "allwinner,sun8i-h3-mdio-internal"); in get_ephy_nodes()
791 dev_err(priv->device, "Cannot get internal_mdio node\n"); in get_ephy_nodes()
792 return -ENODEV; in get_ephy_nodes()
797 gmac->ephy_clk = of_clk_get(iphynode, 0); in get_ephy_nodes()
798 if (IS_ERR(gmac->ephy_clk)) in get_ephy_nodes()
800 gmac->rst_ephy = of_reset_control_get_exclusive(iphynode, NULL); in get_ephy_nodes()
801 if (IS_ERR(gmac->rst_ephy)) { in get_ephy_nodes()
802 ret = PTR_ERR(gmac->rst_ephy); in get_ephy_nodes()
803 if (ret == -EPROBE_DEFER) { in get_ephy_nodes()
809 dev_info(priv->device, "Found internal PHY node\n"); in get_ephy_nodes()
815 return -ENODEV; in get_ephy_nodes()
820 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in sun8i_dwmac_power_internal_phy()
823 if (gmac->internal_phy_powered) { in sun8i_dwmac_power_internal_phy()
824 dev_warn(priv->device, "Internal PHY already powered\n"); in sun8i_dwmac_power_internal_phy()
828 dev_info(priv->device, "Powering internal PHY\n"); in sun8i_dwmac_power_internal_phy()
829 ret = clk_prepare_enable(gmac->ephy_clk); in sun8i_dwmac_power_internal_phy()
831 dev_err(priv->device, "Cannot enable internal PHY\n"); in sun8i_dwmac_power_internal_phy()
835 /* Make sure the EPHY is properly reseted, as U-Boot may leave in sun8i_dwmac_power_internal_phy()
840 ret = reset_control_reset(gmac->rst_ephy); in sun8i_dwmac_power_internal_phy()
842 dev_err(priv->device, "Cannot reset internal PHY\n"); in sun8i_dwmac_power_internal_phy()
843 clk_disable_unprepare(gmac->ephy_clk); in sun8i_dwmac_power_internal_phy()
847 gmac->internal_phy_powered = true; in sun8i_dwmac_power_internal_phy()
854 if (!gmac->internal_phy_powered) in sun8i_dwmac_unpower_internal_phy()
857 clk_disable_unprepare(gmac->ephy_clk); in sun8i_dwmac_unpower_internal_phy()
858 reset_control_assert(gmac->rst_ephy); in sun8i_dwmac_unpower_internal_phy()
859 gmac->internal_phy_powered = false; in sun8i_dwmac_unpower_internal_phy()
863 * This function is called by the mdio-mux layer when it thinks the mdio bus
868 * The first time this function is called, current_child == -1.
876 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in mdio_mux_syscon_switch_fn()
881 regmap_field_read(gmac->regmap_field, ®); in mdio_mux_syscon_switch_fn()
884 dev_info(priv->device, "Switch mux to internal PHY"); in mdio_mux_syscon_switch_fn()
886 gmac->use_internal_phy = true; in mdio_mux_syscon_switch_fn()
889 dev_info(priv->device, "Switch mux to external PHY"); in mdio_mux_syscon_switch_fn()
891 gmac->use_internal_phy = false; in mdio_mux_syscon_switch_fn()
894 dev_err(priv->device, "Invalid child ID %x\n", in mdio_mux_syscon_switch_fn()
896 return -EINVAL; in mdio_mux_syscon_switch_fn()
898 regmap_field_write(gmac->regmap_field, val); in mdio_mux_syscon_switch_fn()
899 if (gmac->use_internal_phy) { in mdio_mux_syscon_switch_fn()
918 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in sun8i_dwmac_register_mdio_mux()
920 mdio_mux = of_get_child_by_name(priv->device->of_node, "mdio-mux"); in sun8i_dwmac_register_mdio_mux()
922 return -ENODEV; in sun8i_dwmac_register_mdio_mux()
924 ret = mdio_mux_init(priv->device, mdio_mux, mdio_mux_syscon_switch_fn, in sun8i_dwmac_register_mdio_mux()
925 &gmac->mux_handle, priv, priv->mii); in sun8i_dwmac_register_mdio_mux()
933 struct sunxi_priv_data *gmac = plat->bsp_priv; in sun8i_dwmac_set_syscon()
934 struct device_node *node = dev->of_node; in sun8i_dwmac_set_syscon()
938 ret = regmap_field_read(gmac->regmap_field, &val); in sun8i_dwmac_set_syscon()
944 reg = gmac->variant->default_syscon_value; in sun8i_dwmac_set_syscon()
950 if (gmac->variant->soc_has_internal_phy) { in sun8i_dwmac_set_syscon()
951 if (of_property_read_bool(node, "allwinner,leds-active-low")) in sun8i_dwmac_set_syscon()
959 ret = of_mdio_parse_addr(dev, plat->phy_node); in sun8i_dwmac_set_syscon()
969 /* For SoCs without internal PHY the PHY selection bit should be in sun8i_dwmac_set_syscon()
975 if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) { in sun8i_dwmac_set_syscon()
977 dev_err(dev, "tx-delay must be a multiple of 100\n"); in sun8i_dwmac_set_syscon()
978 return -EINVAL; in sun8i_dwmac_set_syscon()
981 dev_dbg(dev, "set tx-delay to %x\n", val); in sun8i_dwmac_set_syscon()
982 if (val <= gmac->variant->tx_delay_max) { in sun8i_dwmac_set_syscon()
983 reg &= ~(gmac->variant->tx_delay_max << in sun8i_dwmac_set_syscon()
989 return -EINVAL; in sun8i_dwmac_set_syscon()
993 if (!of_property_read_u32(node, "allwinner,rx-delay-ps", &val)) { in sun8i_dwmac_set_syscon()
995 dev_err(dev, "rx-delay must be a multiple of 100\n"); in sun8i_dwmac_set_syscon()
996 return -EINVAL; in sun8i_dwmac_set_syscon()
999 dev_dbg(dev, "set rx-delay to %x\n", val); in sun8i_dwmac_set_syscon()
1000 if (val <= gmac->variant->rx_delay_max) { in sun8i_dwmac_set_syscon()
1001 reg &= ~(gmac->variant->rx_delay_max << in sun8i_dwmac_set_syscon()
1007 return -EINVAL; in sun8i_dwmac_set_syscon()
1013 if (gmac->variant->support_rmii) in sun8i_dwmac_set_syscon()
1016 switch (plat->mac_interface) { in sun8i_dwmac_set_syscon()
1031 phy_modes(plat->mac_interface)); in sun8i_dwmac_set_syscon()
1032 return -EINVAL; in sun8i_dwmac_set_syscon()
1035 regmap_field_write(gmac->regmap_field, reg); in sun8i_dwmac_set_syscon()
1042 u32 reg = gmac->variant->default_syscon_value; in sun8i_dwmac_unset_syscon()
1044 regmap_field_write(gmac->regmap_field, reg); in sun8i_dwmac_unset_syscon()
1051 if (gmac->variant->soc_has_internal_phy) in sun8i_dwmac_exit()
1054 if (gmac->regulator) in sun8i_dwmac_exit()
1055 regulator_disable(gmac->regulator); in sun8i_dwmac_exit()
1087 mac = devm_kzalloc(priv->device, sizeof(*mac), GFP_KERNEL); in sun8i_dwmac_setup()
1091 mac->pcsr = priv->ioaddr; in sun8i_dwmac_setup()
1092 mac->mac = &sun8i_dwmac_ops; in sun8i_dwmac_setup()
1093 mac->dma = &sun8i_dwmac_dma_ops; in sun8i_dwmac_setup()
1095 priv->dev->priv_flags |= IFF_UNICAST_FLT; in sun8i_dwmac_setup()
1097 mac->link.caps = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in sun8i_dwmac_setup()
1099 /* The loopback bit seems to be re-set when link change in sun8i_dwmac_setup()
1101 * Speed 10/100/1000 are set in BIT(2)/BIT(3) in sun8i_dwmac_setup()
1103 mac->link.speed_mask = GENMASK(3, 2) | EMAC_LOOPBACK; in sun8i_dwmac_setup()
1104 mac->link.speed10 = EMAC_SPEED_10; in sun8i_dwmac_setup()
1105 mac->link.speed100 = EMAC_SPEED_100; in sun8i_dwmac_setup()
1106 mac->link.speed1000 = EMAC_SPEED_1000; in sun8i_dwmac_setup()
1107 mac->link.duplex = EMAC_DUPLEX_FULL; in sun8i_dwmac_setup()
1108 mac->mii.addr = EMAC_MDIO_CMD; in sun8i_dwmac_setup()
1109 mac->mii.data = EMAC_MDIO_DATA; in sun8i_dwmac_setup()
1110 mac->mii.reg_shift = 4; in sun8i_dwmac_setup()
1111 mac->mii.reg_mask = GENMASK(8, 4); in sun8i_dwmac_setup()
1112 mac->mii.addr_shift = 12; in sun8i_dwmac_setup()
1113 mac->mii.addr_mask = GENMASK(16, 12); in sun8i_dwmac_setup()
1114 mac->mii.clk_csr_shift = 20; in sun8i_dwmac_setup()
1115 mac->mii.clk_csr_mask = GENMASK(22, 20); in sun8i_dwmac_setup()
1116 mac->unicast_filter_entries = 8; in sun8i_dwmac_setup()
1119 priv->synopsys_id = 0; in sun8i_dwmac_setup()
1132 return ERR_PTR(-ENODEV); in sun8i_dwmac_get_syscon_from_dev()
1137 regmap = ERR_PTR(-EPROBE_DEFER); in sun8i_dwmac_get_syscon_from_dev()
1142 regmap = dev_get_regmap(&syscon_pdev->dev, NULL); in sun8i_dwmac_get_syscon_from_dev()
1144 regmap = ERR_PTR(-EINVAL); in sun8i_dwmac_get_syscon_from_dev()
1157 struct device *dev = &pdev->dev; in sun8i_dwmac_probe()
1170 return -ENOMEM; in sun8i_dwmac_probe()
1172 gmac->variant = of_device_get_match_data(&pdev->dev); in sun8i_dwmac_probe()
1173 if (!gmac->variant) { in sun8i_dwmac_probe()
1174 dev_err(&pdev->dev, "Missing dwmac-sun8i variant\n"); in sun8i_dwmac_probe()
1175 return -EINVAL; in sun8i_dwmac_probe()
1179 gmac->regulator = devm_regulator_get_optional(dev, "phy"); in sun8i_dwmac_probe()
1180 if (IS_ERR(gmac->regulator)) { in sun8i_dwmac_probe()
1181 if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER) in sun8i_dwmac_probe()
1182 return -EPROBE_DEFER; in sun8i_dwmac_probe()
1184 gmac->regulator = NULL; in sun8i_dwmac_probe()
1204 regmap = sun8i_dwmac_get_syscon_from_dev(pdev->dev.of_node); in sun8i_dwmac_probe()
1206 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in sun8i_dwmac_probe()
1210 dev_err(&pdev->dev, "Unable to map syscon: %d\n", ret); in sun8i_dwmac_probe()
1214 gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, in sun8i_dwmac_probe()
1215 *gmac->variant->syscon_field); in sun8i_dwmac_probe()
1216 if (IS_ERR(gmac->regmap_field)) { in sun8i_dwmac_probe()
1217 ret = PTR_ERR(gmac->regmap_field); in sun8i_dwmac_probe()
1222 ret = of_get_phy_mode(dev->of_node, &interface); in sun8i_dwmac_probe()
1224 return -EINVAL; in sun8i_dwmac_probe()
1233 plat_dat->mac_interface = interface; in sun8i_dwmac_probe()
1234 plat_dat->rx_coe = STMMAC_RX_COE_TYPE2; in sun8i_dwmac_probe()
1235 plat_dat->tx_coe = 1; in sun8i_dwmac_probe()
1236 plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I; in sun8i_dwmac_probe()
1237 plat_dat->bsp_priv = gmac; in sun8i_dwmac_probe()
1238 plat_dat->init = sun8i_dwmac_init; in sun8i_dwmac_probe()
1239 plat_dat->exit = sun8i_dwmac_exit; in sun8i_dwmac_probe()
1240 plat_dat->setup = sun8i_dwmac_setup; in sun8i_dwmac_probe()
1241 plat_dat->tx_fifo_size = 4096; in sun8i_dwmac_probe()
1242 plat_dat->rx_fifo_size = 16384; in sun8i_dwmac_probe()
1244 ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat); in sun8i_dwmac_probe()
1248 ret = sun8i_dwmac_init(pdev, plat_dat->bsp_priv); in sun8i_dwmac_probe()
1252 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in sun8i_dwmac_probe()
1256 ndev = dev_get_drvdata(&pdev->dev); in sun8i_dwmac_probe()
1263 pm_runtime_get_sync(&pdev->dev); in sun8i_dwmac_probe()
1268 if (gmac->variant->soc_has_internal_phy) { in sun8i_dwmac_probe()
1274 dev_err(&pdev->dev, "Failed to register mux\n"); in sun8i_dwmac_probe()
1283 pm_runtime_put(&pdev->dev); in sun8i_dwmac_probe()
1288 reset_control_put(gmac->rst_ephy); in sun8i_dwmac_probe()
1289 clk_put(gmac->ephy_clk); in sun8i_dwmac_probe()
1291 pm_runtime_put_noidle(&pdev->dev); in sun8i_dwmac_probe()
1292 stmmac_dvr_remove(&pdev->dev); in sun8i_dwmac_probe()
1305 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in sun8i_dwmac_remove()
1307 if (gmac->variant->soc_has_internal_phy) { in sun8i_dwmac_remove()
1308 mdio_mux_uninit(gmac->mux_handle); in sun8i_dwmac_remove()
1310 reset_control_put(gmac->rst_ephy); in sun8i_dwmac_remove()
1311 clk_put(gmac->ephy_clk); in sun8i_dwmac_remove()
1322 struct sunxi_priv_data *gmac = priv->plat->bsp_priv; in sun8i_dwmac_shutdown()
1328 { .compatible = "allwinner,sun8i-h3-emac",
1330 { .compatible = "allwinner,sun8i-v3s-emac",
1332 { .compatible = "allwinner,sun8i-a83t-emac",
1334 { .compatible = "allwinner,sun8i-r40-gmac",
1336 { .compatible = "allwinner,sun50i-a64-emac",
1338 { .compatible = "allwinner,sun50i-h6-emac",
1349 .name = "dwmac-sun8i",