Lines Matching full:tx_delay
70 u32 tx_delay; member
150 mac_delay->tx_delay /= 550; in mt2712_delay_ps2stage()
158 mac_delay->tx_delay /= 170; in mt2712_delay_ps2stage()
175 mac_delay->tx_delay *= 550; in mt2712_delay_stage2ps()
183 mac_delay->tx_delay *= 170; in mt2712_delay_stage2ps()
201 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
202 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
220 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
221 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
261 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
262 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
330 mac_delay->tx_delay /= 290; in mt8195_delay_ps2stage()
339 mac_delay->tx_delay *= 290; in mt8195_delay_stage2ps()
352 delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay); in mt8195_set_delay()
353 delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay); in mt8195_set_delay()
368 !!mac_delay->tx_delay); in mt8195_set_delay()
370 mac_delay->tx_delay); in mt8195_set_delay()
416 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt8195_set_delay()
417 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay); in mt8195_set_delay()
475 mac_delay->tx_delay = tx_delay_ps; in mediatek_dwmac_config_dt()