Lines Matching +full:burst +full:- +full:clk +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys DWC Ethernet Quality-of-Service v4.10a linux driver
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
32 struct clk *clk_master;
33 struct clk *clk_slave;
34 struct clk *clk_tx;
35 struct clk *clk_rx;
43 struct device *dev = &pdev->dev; in dwc_eth_dwmac_config_dt()
48 if (!plat_dat->axi) { in dwc_eth_dwmac_config_dt()
49 plat_dat->axi = devm_kzalloc(&pdev->dev, in dwc_eth_dwmac_config_dt()
53 if (!plat_dat->axi) in dwc_eth_dwmac_config_dt()
54 return -ENOMEM; in dwc_eth_dwmac_config_dt()
57 plat_dat->axi->axi_lpi_en = device_property_read_bool(dev, in dwc_eth_dwmac_config_dt()
58 "snps,en-lpi"); in dwc_eth_dwmac_config_dt()
59 if (device_property_read_u32(dev, "snps,write-requests", in dwc_eth_dwmac_config_dt()
60 &plat_dat->axi->axi_wr_osr_lmt)) { in dwc_eth_dwmac_config_dt()
65 plat_dat->axi->axi_wr_osr_lmt = 1; in dwc_eth_dwmac_config_dt()
71 plat_dat->axi->axi_wr_osr_lmt--; in dwc_eth_dwmac_config_dt()
74 if (device_property_read_u32(dev, "snps,read-requests", in dwc_eth_dwmac_config_dt()
75 &plat_dat->axi->axi_rd_osr_lmt)) { in dwc_eth_dwmac_config_dt()
80 plat_dat->axi->axi_rd_osr_lmt = 1; in dwc_eth_dwmac_config_dt()
86 plat_dat->axi->axi_rd_osr_lmt--; in dwc_eth_dwmac_config_dt()
88 device_property_read_u32(dev, "snps,burst-map", &burst_map); in dwc_eth_dwmac_config_dt()
90 /* converts burst-map bitmask to burst array */ in dwc_eth_dwmac_config_dt()
95 plat_dat->axi->axi_blen[a_index] = 4; break; in dwc_eth_dwmac_config_dt()
97 plat_dat->axi->axi_blen[a_index] = 8; break; in dwc_eth_dwmac_config_dt()
99 plat_dat->axi->axi_blen[a_index] = 16; break; in dwc_eth_dwmac_config_dt()
101 plat_dat->axi->axi_blen[a_index] = 32; break; in dwc_eth_dwmac_config_dt()
103 plat_dat->axi->axi_blen[a_index] = 64; break; in dwc_eth_dwmac_config_dt()
105 plat_dat->axi->axi_blen[a_index] = 128; break; in dwc_eth_dwmac_config_dt()
107 plat_dat->axi->axi_blen[a_index] = 256; break; in dwc_eth_dwmac_config_dt()
115 /* dwc-qos needs GMAC4, AAL, TSO and PMT */ in dwc_eth_dwmac_config_dt()
116 plat_dat->has_gmac4 = 1; in dwc_eth_dwmac_config_dt()
117 plat_dat->dma_cfg->aal = 1; in dwc_eth_dwmac_config_dt()
118 plat_dat->flags |= STMMAC_FLAG_TSO_EN; in dwc_eth_dwmac_config_dt()
119 plat_dat->pmt = 1; in dwc_eth_dwmac_config_dt()
130 plat_dat->stmmac_clk = devm_clk_get(&pdev->dev, "apb_pclk"); in dwc_qos_probe()
131 if (IS_ERR(plat_dat->stmmac_clk)) { in dwc_qos_probe()
132 dev_err(&pdev->dev, "apb_pclk clock not found.\n"); in dwc_qos_probe()
133 return PTR_ERR(plat_dat->stmmac_clk); in dwc_qos_probe()
136 err = clk_prepare_enable(plat_dat->stmmac_clk); in dwc_qos_probe()
138 dev_err(&pdev->dev, "failed to enable apb_pclk clock: %d\n", in dwc_qos_probe()
143 plat_dat->pclk = devm_clk_get(&pdev->dev, "phy_ref_clk"); in dwc_qos_probe()
144 if (IS_ERR(plat_dat->pclk)) { in dwc_qos_probe()
145 dev_err(&pdev->dev, "phy_ref_clk clock not found.\n"); in dwc_qos_probe()
146 err = PTR_ERR(plat_dat->pclk); in dwc_qos_probe()
150 err = clk_prepare_enable(plat_dat->pclk); in dwc_qos_probe()
152 dev_err(&pdev->dev, "failed to enable phy_ref clock: %d\n", in dwc_qos_probe()
160 clk_disable_unprepare(plat_dat->stmmac_clk); in dwc_qos_probe()
169 clk_disable_unprepare(priv->plat->pclk); in dwc_qos_remove()
170 clk_disable_unprepare(priv->plat->stmmac_clk); in dwc_qos_remove()
202 dev_err(eqos->dev, "invalid speed %u\n", speed); in tegra_eqos_fix_speed()
208 value = readl(eqos->regs + SDMEMCOMPPADCTRL); in tegra_eqos_fix_speed()
210 writel(value, eqos->regs + SDMEMCOMPPADCTRL); in tegra_eqos_fix_speed()
214 value = readl(eqos->regs + AUTO_CAL_CONFIG); in tegra_eqos_fix_speed()
216 writel(value, eqos->regs + AUTO_CAL_CONFIG); in tegra_eqos_fix_speed()
218 err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS, in tegra_eqos_fix_speed()
223 dev_err(eqos->dev, "calibration did not start\n"); in tegra_eqos_fix_speed()
227 err = readl_poll_timeout_atomic(eqos->regs + AUTO_CAL_STATUS, in tegra_eqos_fix_speed()
232 dev_err(eqos->dev, "calibration didn't finish\n"); in tegra_eqos_fix_speed()
237 value = readl(eqos->regs + SDMEMCOMPPADCTRL); in tegra_eqos_fix_speed()
239 writel(value, eqos->regs + SDMEMCOMPPADCTRL); in tegra_eqos_fix_speed()
241 value = readl(eqos->regs + AUTO_CAL_CONFIG); in tegra_eqos_fix_speed()
243 writel(value, eqos->regs + AUTO_CAL_CONFIG); in tegra_eqos_fix_speed()
246 err = clk_set_rate(eqos->clk_tx, rate); in tegra_eqos_fix_speed()
248 dev_err(eqos->dev, "failed to set TX rate: %d\n", err); in tegra_eqos_fix_speed()
257 rate = clk_get_rate(eqos->clk_slave); in tegra_eqos_init()
259 value = (rate / 1000000) - 1; in tegra_eqos_init()
260 writel(value, eqos->regs + GMAC_1US_TIC_COUNTER); in tegra_eqos_init()
269 struct device *dev = &pdev->dev; in tegra_eqos_probe()
273 eqos = devm_kzalloc(&pdev->dev, sizeof(*eqos), GFP_KERNEL); in tegra_eqos_probe()
275 return -ENOMEM; in tegra_eqos_probe()
277 eqos->dev = &pdev->dev; in tegra_eqos_probe()
278 eqos->regs = res->addr; in tegra_eqos_probe()
280 if (!is_of_node(dev->fwnode)) in tegra_eqos_probe()
283 eqos->clk_master = devm_clk_get(&pdev->dev, "master_bus"); in tegra_eqos_probe()
284 if (IS_ERR(eqos->clk_master)) { in tegra_eqos_probe()
285 err = PTR_ERR(eqos->clk_master); in tegra_eqos_probe()
289 err = clk_prepare_enable(eqos->clk_master); in tegra_eqos_probe()
293 eqos->clk_slave = devm_clk_get(&pdev->dev, "slave_bus"); in tegra_eqos_probe()
294 if (IS_ERR(eqos->clk_slave)) { in tegra_eqos_probe()
295 err = PTR_ERR(eqos->clk_slave); in tegra_eqos_probe()
299 data->stmmac_clk = eqos->clk_slave; in tegra_eqos_probe()
301 err = clk_prepare_enable(eqos->clk_slave); in tegra_eqos_probe()
305 eqos->clk_rx = devm_clk_get(&pdev->dev, "rx"); in tegra_eqos_probe()
306 if (IS_ERR(eqos->clk_rx)) { in tegra_eqos_probe()
307 err = PTR_ERR(eqos->clk_rx); in tegra_eqos_probe()
311 err = clk_prepare_enable(eqos->clk_rx); in tegra_eqos_probe()
315 eqos->clk_tx = devm_clk_get(&pdev->dev, "tx"); in tegra_eqos_probe()
316 if (IS_ERR(eqos->clk_tx)) { in tegra_eqos_probe()
317 err = PTR_ERR(eqos->clk_tx); in tegra_eqos_probe()
321 err = clk_prepare_enable(eqos->clk_tx); in tegra_eqos_probe()
325 eqos->reset = devm_gpiod_get(&pdev->dev, "phy-reset", GPIOD_OUT_HIGH); in tegra_eqos_probe()
326 if (IS_ERR(eqos->reset)) { in tegra_eqos_probe()
327 err = PTR_ERR(eqos->reset); in tegra_eqos_probe()
332 gpiod_set_value(eqos->reset, 0); in tegra_eqos_probe()
335 data->mdio_bus_data->needs_reset = false; in tegra_eqos_probe()
337 eqos->rst = devm_reset_control_get(&pdev->dev, "eqos"); in tegra_eqos_probe()
338 if (IS_ERR(eqos->rst)) { in tegra_eqos_probe()
339 err = PTR_ERR(eqos->rst); in tegra_eqos_probe()
343 err = reset_control_assert(eqos->rst); in tegra_eqos_probe()
349 err = reset_control_deassert(eqos->rst); in tegra_eqos_probe()
356 data->fix_mac_speed = tegra_eqos_fix_speed; in tegra_eqos_probe()
357 data->init = tegra_eqos_init; in tegra_eqos_probe()
358 data->bsp_priv = eqos; in tegra_eqos_probe()
359 data->flags |= STMMAC_FLAG_SPH_DISABLE; in tegra_eqos_probe()
367 reset_control_assert(eqos->rst); in tegra_eqos_probe()
369 gpiod_set_value(eqos->reset, 1); in tegra_eqos_probe()
371 clk_disable_unprepare(eqos->clk_tx); in tegra_eqos_probe()
373 clk_disable_unprepare(eqos->clk_rx); in tegra_eqos_probe()
375 clk_disable_unprepare(eqos->clk_slave); in tegra_eqos_probe()
377 clk_disable_unprepare(eqos->clk_master); in tegra_eqos_probe()
384 struct tegra_eqos *eqos = get_stmmac_bsp_priv(&pdev->dev); in tegra_eqos_remove()
386 reset_control_assert(eqos->rst); in tegra_eqos_remove()
387 gpiod_set_value(eqos->reset, 1); in tegra_eqos_remove()
388 clk_disable_unprepare(eqos->clk_tx); in tegra_eqos_remove()
389 clk_disable_unprepare(eqos->clk_rx); in tegra_eqos_remove()
390 clk_disable_unprepare(eqos->clk_slave); in tegra_eqos_remove()
391 clk_disable_unprepare(eqos->clk_master); in tegra_eqos_remove()
418 data = device_get_match_data(&pdev->dev); in dwc_eth_dwmac_probe()
439 ret = data->probe(pdev, plat_dat, &stmmac_res); in dwc_eth_dwmac_probe()
441 dev_err_probe(&pdev->dev, ret, "failed to probe subdriver\n"); in dwc_eth_dwmac_probe()
449 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in dwc_eth_dwmac_probe()
456 data->remove(pdev); in dwc_eth_dwmac_probe()
463 const struct dwc_eth_dwmac_data *data = device_get_match_data(&pdev->dev); in dwc_eth_dwmac_remove()
465 stmmac_dvr_remove(&pdev->dev); in dwc_eth_dwmac_remove()
467 data->remove(pdev); in dwc_eth_dwmac_remove()
471 { .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data },
472 { .compatible = "nvidia,tegra186-eqos", .data = &tegra_eqos_data },
481 .name = "dwc-eth-dwmac",
489 MODULE_DESCRIPTION("Synopsys DWC Ethernet Quality-of-Service v4.10a driver");