Lines Matching full:lp
65 #define SMC_IO_SHIFT (lp->io_shift)
71 SMC_16BIT(lp) ? readw((a) + __smc_r) : \
72 SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) : \
78 #define SMC_outw(lp, v, a, r) \ argument
81 if (SMC_16BIT(lp)) \
82 __SMC_outw(lp, __v, a, __smc_r); \
83 else if (SMC_8BIT(lp)) \
111 #define __SMC_outw(lp, v, a, r) \ argument
114 (lp)->cfg.pxa_u16_align4)
128 #define SMC_outw(lp, v, a, r) writew(v, (a) + (r)) argument
160 #define SMC_outw(lp, v, a, r) iowrite16be(v, (a) + (r)) argument
177 #define SMC_IO_SHIFT (lp->io_shift)
183 #define SMC_outw(lp, v, a, r) iowrite16(v, (a) + (r)) argument
267 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
269 smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len) in smc_pxa_dma_inpump() argument
277 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); in smc_pxa_dma_inpump()
278 tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len, in smc_pxa_dma_inpump()
282 dma_async_issue_pending(lp->dma_chan); in smc_pxa_dma_inpump()
284 status = dmaengine_tx_status(lp->dma_chan, cookie, in smc_pxa_dma_inpump()
289 dmaengine_terminate_all(lp->dma_chan); in smc_pxa_dma_inpump()
291 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); in smc_pxa_dma_inpump()
295 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, in smc_pxa_dma_insl() argument
302 if (!lp->dma_chan) { in smc_pxa_dma_insl()
317 config.src_addr = lp->physaddr + reg; in smc_pxa_dma_insl()
318 config.dst_addr = lp->physaddr + reg; in smc_pxa_dma_insl()
321 ret = dmaengine_slave_config(lp->dma_chan, &config); in smc_pxa_dma_insl()
323 dev_err(lp->device, "dma channel configuration failed: %d\n", in smc_pxa_dma_insl()
329 smc_pxa_dma_inpump(lp, buf, len); in smc_pxa_dma_insl()
336 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
338 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, in smc_pxa_dma_insw() argument
345 if (!lp->dma_chan) { in smc_pxa_dma_insw()
360 config.src_addr = lp->physaddr + reg; in smc_pxa_dma_insw()
361 config.dst_addr = lp->physaddr + reg; in smc_pxa_dma_insw()
364 ret = dmaengine_slave_config(lp->dma_chan, &config); in smc_pxa_dma_insw()
366 dev_err(lp->device, "dma channel configuration failed: %d\n", in smc_pxa_dma_insw()
372 smc_pxa_dma_inpump(lp, buf, len); in smc_pxa_dma_insw()
400 #define SMC_outw(lp, x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg) argument
459 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) argument
478 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) argument
497 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) argument
514 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) argument
519 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) argument
524 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) argument
550 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) argument
562 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) argument
567 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) argument
568 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) argument
569 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) argument
574 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1) argument
579 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) argument
592 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) argument
606 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2) argument
611 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2) argument
617 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) argument
622 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) argument
625 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) argument
629 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) argument
637 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) argument
642 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2) argument
647 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2) argument
660 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) argument
661 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) argument
662 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) argument
663 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) argument
668 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3) argument
679 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3) argument
685 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) argument
692 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) argument
816 #define SMC_REG(lp, reg, bank) \ argument
818 int __b = SMC_CURRENT_BANK(lp); \
827 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) argument
839 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp) argument
841 #define SMC_GET_PN(lp) \ argument
842 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
843 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
845 #define SMC_SET_PN(lp, x) \ argument
847 if (SMC_MUST_ALIGN_WRITE(lp)) \
848 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
849 else if (SMC_8BIT(lp)) \
850 SMC_outb(x, ioaddr, PN_REG(lp)); \
852 SMC_outw(lp, x, ioaddr, PN_REG(lp)); \
855 #define SMC_GET_AR(lp) \ argument
856 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
857 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
859 #define SMC_GET_TXFIFO(lp) \ argument
860 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
861 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
863 #define SMC_GET_RXFIFO(lp) \ argument
864 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
865 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
867 #define SMC_GET_INT(lp) \ argument
868 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
869 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
871 #define SMC_ACK_INT(lp, x) \ argument
873 if (SMC_8BIT(lp)) \
874 SMC_outb(x, ioaddr, INT_REG(lp)); \
879 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
880 SMC_outw(lp, __mask | (x), ioaddr, INT_REG(lp)); \
885 #define SMC_GET_INT_MASK(lp) \ argument
886 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
887 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
889 #define SMC_SET_INT_MASK(lp, x) \ argument
891 if (SMC_8BIT(lp)) \
892 SMC_outb(x, ioaddr, IM_REG(lp)); \
894 SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp)); \
897 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) argument
899 #define SMC_SELECT_BANK(lp, x) \ argument
901 if (SMC_MUST_ALIGN_WRITE(lp)) \
904 SMC_outw(lp, x, ioaddr, BANK_SELECT); \
907 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp)) argument
909 #define SMC_SET_BASE(lp, x) SMC_outw(lp, x, ioaddr, BASE_REG(lp)) argument
911 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp)) argument
913 #define SMC_SET_CONFIG(lp, x) SMC_outw(lp, x, ioaddr, CONFIG_REG(lp)) argument
915 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp)) argument
917 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp)) argument
919 #define SMC_SET_CTL(lp, x) SMC_outw(lp, x, ioaddr, CTL_REG(lp)) argument
921 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp)) argument
923 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp)) argument
925 #define SMC_SET_GP(lp, x) \ argument
927 if (SMC_MUST_ALIGN_WRITE(lp)) \
928 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
930 SMC_outw(lp, x, ioaddr, GP_REG(lp)); \
933 #define SMC_SET_MII(lp, x) SMC_outw(lp, x, ioaddr, MII_REG(lp)) argument
935 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp)) argument
937 #define SMC_SET_MIR(lp, x) SMC_outw(lp, x, ioaddr, MIR_REG(lp)) argument
939 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp)) argument
941 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(lp, x, ioaddr, MMU_CMD_REG(lp)) argument
943 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp)) argument
945 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp)) argument
947 #define SMC_SET_PTR(lp, x) \ argument
949 if (SMC_MUST_ALIGN_WRITE(lp)) \
950 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
952 SMC_outw(lp, x, ioaddr, PTR_REG(lp)); \
955 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp)) argument
957 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp)) argument
959 #define SMC_SET_RCR(lp, x) SMC_outw(lp, x, ioaddr, RCR_REG(lp)) argument
961 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp)) argument
963 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp)) argument
965 #define SMC_SET_RPC(lp, x) \ argument
967 if (SMC_MUST_ALIGN_WRITE(lp)) \
968 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
970 SMC_outw(lp, x, ioaddr, RPC_REG(lp)); \
973 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp)) argument
975 #define SMC_SET_TCR(lp, x) SMC_outw(lp, x, ioaddr, TCR_REG(lp)) argument
978 #define SMC_GET_MAC_ADDR(lp, addr) \ argument
981 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
983 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
985 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
990 #define SMC_SET_MAC_ADDR(lp, addr) \ argument
992 SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
993 SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
994 SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
997 #define SMC_SET_MCAST(lp, x) \ argument
1000 SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1001 SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1002 SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1003 SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1006 #define SMC_PUT_PKT_HDR(lp, status, length) \ argument
1008 if (SMC_32BIT(lp)) \
1010 DATA_REG(lp)); \
1012 SMC_outw(lp, status, ioaddr, DATA_REG(lp)); \
1013 SMC_outw(lp, length, ioaddr, DATA_REG(lp)); \
1017 #define SMC_GET_PKT_HDR(lp, status, length) \ argument
1019 if (SMC_32BIT(lp)) { \
1020 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1024 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1025 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1029 #define SMC_PUSH_DATA(lp, p, l) \ argument
1031 if (SMC_32BIT(lp)) { \
1037 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1040 if (SMC_CAN_USE_DATACS && lp->datacs) \
1041 __ioaddr = lp->datacs; \
1042 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1045 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1047 } else if (SMC_16BIT(lp)) \
1048 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1049 else if (SMC_8BIT(lp)) \
1050 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1053 #define SMC_PULL_DATA(lp, p, l) \ argument
1055 if (SMC_32BIT(lp)) { \
1075 SMC_SET_PTR(lp, \
1078 if (SMC_CAN_USE_DATACS && lp->datacs) \
1079 __ioaddr = lp->datacs; \
1081 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1082 } else if (SMC_16BIT(lp)) \
1083 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1084 else if (SMC_8BIT(lp)) \
1085 SMC_insb(ioaddr, DATA_REG(lp), p, l); \