Lines Matching +full:rev +full:- +full:mii

1 /* SPDX-License-Identifier: GPL-2.0 */
6  *	preliminary Rev. 1.0 Jan. 14, 1998
8  *	preliminary Rev. 1.0 Nov. 10, 1998
9  *   SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
10  *	preliminary Rev. 1.0 Jan. 18, 1998
40         pmer=0xB4               //Power Management Wake-up Event Register
131 /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
172 /* Wake-on-LAN support. */
216 /* MII register offsets */
223 /* mii registers specific to SiS 900 */
229 /* mii registers specific to ICS 1893 */
235 /* mii registers specific to AMD 79C901 */
240 /* MII Control register bit definitions. */
248 /* MII Status register bit  */
262 /* MII NWAY Register Bits ...
263    valid for the ANAR (Auto-Negotiation Advertisement) and
264    ANLPAR (Auto-Negotiation Link Partner) registers */