1 /* SPDX-License-Identifier: GPL-2.0-only */
4  * Copyright 2005-2006 Fen Systems Ltd.
5  * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
64  * queue visible to the networking core is backed by two hardware TX
83 /* Size of an RX scatter buffer.  Small enough to pack 2 into a 4K page,
86 #define EFX_RX_USR_BUF_SIZE	(2048 - 256)
89  * of every buffer.  Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
111  * struct efx_buffer - A general-purpose DMA buffer
126  * struct efx_tx_buffer - buffer state for a TX descriptor
131  * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
136  *	This field is zero when the queue slot is empty.
164  * struct efx_tx_queue - An Efx TX queue
177  * @queue: DMA queue number
179  *	Is our index within @channel->tx_queue array.
180  * @type: configuration type of this TX queue.  A bitmask of %EFX_TXQ_TYPE_* flags.
181  * @tso_version: Version of TSO in use for this queue.
184  * @core_txq: The networking core TX queue structure
187  *	%EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
190  * @piobuf: PIO buffer region for this TX queue (shared with its partner).
193  * @initialised: Has hardware queue been initialised?
195  * @xdp_tx: Is this an XDP tx queue?
206  *	only get the up-to-date value of @write_count if this
207  *	variable indicates that the queue is empty.  This is to
208  *	avoid cache-line ping-pong between the xmit path and the
237  *	Filled in iff @efx->type->option_descriptors; only used for PIO.
241  *	only get the up-to-date value of read_count if this
242  *	variable indicates that the queue is full.  This is to
243  *	avoid cache-line ping-pong between the xmit path and the
256  * @empty_read_count: If the completion path has seen the queue as empty
258  *	@read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
263 	unsigned int queue;  member
321 #define EFX_TX_CB_SIZE	(1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
324  * struct efx_rx_buffer - An Efx RX data buffer
350  * struct efx_rx_page_state - Page-based rx buffer state
353  * Used to facilitate sharing dma mappings between recycled rx buffers
365  * struct efx_rx_queue - An Efx RX queue
367  * @core_index:  Index of network core RX queue.  Will be >= 0 iff this
368  *	is associated with a real RX queue.
373  * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
375  * @grant_credits: Posted RX descriptors need to be granted to the MAE with
378  * @added_count: Number of buffers added to the receive queue.
381  * @removed_count: Number of buffers removed from the receive queue.
392  * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
393  * @max_fill: RX descriptor maximum fill level (<= ring size)
394  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
396  * @min_fill: RX descriptor minimum non-zero fill level.
399  * @recycle_count: RX buffer recycle counter.
406  * @xdp_rxq_info: XDP specific RX queue information.
457  * struct efx_channel - An Efx channel
459  * A channel comprises an event queue, at least one TX queue, at least
460  * one RX queue, and an associated tasklet for processing the event
461  * queue.
466  * @eventq_init: Event queue initialised flag
468  * @irq: IRQ number (MSI and MSI-X only)
474  * @eventq: Event queue buffer
475  * @eventq_mask: Event queue pointer mask
476  * @eventq_read_ptr: Event queue read pointer
490  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
491  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
494  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
495  * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
497  * @n_rx_merge_events: Number of RX merged completion events
498  * @n_rx_merge_packets: Number of RX packets completed by merged events
499  * @n_rx_xdp_drops: Count of RX packets intentionally dropped due to XDP
500  * @n_rx_xdp_bad_drops: Count of RX packets dropped due to XDP errors
501  * @n_rx_xdp_tx: Count of RX packets retransmitted due to XDP
502  * @n_rx_xdp_redirect: Count of RX packets redirected to a different NIC by XDP
503  * @n_rx_mport_bad: Count of RX packets dropped because their ingress mport was
505  * @old_n_rx_hw_drops: Count of all RX packets dropped for any reason as of last
513  * @rx_list: list of SKBs from current RX, awaiting processing
514  * @rx_queue: RX queue for this channel
589  * struct efx_msi_context - Context for each MSI
604  * struct efx_channel_type - distinguishes traffic and extra channels
615  * @receive_raw: Handle an RX buffer ready to be passed to __efx_rx_packet()
618  * @keep_eventq: Flag for whether event queue should be kept initialised
650 	STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
659 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
714 /* Pseudo bit-mask flow control field */
720  * struct efx_link_state - Current state of the link
722  * @fd: Link is full-duplex
736 	return left->up == right->up && left->fd == right->fd &&  in efx_link_state_equal()
737 		left->fc == right->fc && left->speed == right->speed;  in efx_link_state_equal()
741  * enum efx_phy_mode - PHY operating mode flags
762  * struct efx_hw_stat_desc - Description of a hardware statistic
765  * @dma_width: Width in bits (0 for non-DMA statistics)
766  * @offset: Offset within stats (ignored for non-DMA statistics)
779  * struct efx_rss_context_priv - driver private data for an RSS context
782  * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
790  * struct efx_rss_context - an RSS context
791  * @priv: hardware-specific state
805 #define EFX_ARFS_FILTER_ID_PENDING	-1
806 #define EFX_ARFS_FILTER_ID_ERROR	-2
807 #define EFX_ARFS_FILTER_ID_REMOVING	-3
809  * struct efx_arfs_rule - record of an ARFS filter and its IDs
811  * @spec: details of the filter (used as key for hash table).  Use efx->type to
832  * struct efx_async_filter_insertion - Request to asynchronously insert a filter
838  * @flow_id: Identifies the kernel-side flow for which this request was made
854 	EFX_XDP_TX_QUEUES_DEDICATED,	/* one queue per core, locking not needed */
855 	EFX_XDP_TX_QUEUES_SHARED,	/* each queue used by more than 1 core */
862  * struct efx_nic - an Efx NIC
880  * @vi_stride: step between per-VI registers / memory regions
884  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
886  * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
887  * @irq_rx_moderation_us: IRQ moderation time for RX event queues
892  * @rx_queue: RX DMA queues
895  * @extra_channel_types: Types of extra (non-traffic) channels that
903  * @txq_stop_thresh: TX queue fill level at or above which we stop it.
904  * @txq_wake_thresh: TX queue fill level at or below which we wake it.
905  * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
906  * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
909  * @n_rx_channels: Number of channels used for RX (= number of RX queues)
916  * @rx_ip_align: RX DMA address offset to have IP header aligned in
918  * @rx_dma_len: Current maximum RX DMA length
919  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
920  * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
922  * @rx_prefix_size: Size of RX prefix before packet data
923  * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
925  * @rx_packet_len_offset: Offset of RX packet length from start of packet data
928  *	(valid only if channel->sync_timestamps_enabled; always negative)
935  * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
938  * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
939  * @irq_level: IRQ level/index for IRQs not triggered by an event queue
940  * @selftest_work: Work item for asynchronous self-test
943  * @mcdi: Management-Controller-to-Driver Interface state
958  * @phy_data: PHY private data (including PHY-specific stats)
966  * @fc_disable: When non-zero flow control is disabled. Typically used to
967  *	ensure that network back pressure doesn't delay dma queue flushes.
972  * @loopback_selftest: Offline self-test private state
975  * @filter_state: Architecture-dependent filter table state
977  * @rps_slot_map: bitmap of in-flight entries in @rps_slot
983  * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
986  * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
989  * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
998  * @xdp_rxq_info_failed: Have any of the rx queues failed to initialise their
1014  * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
1201  * struct efx_probe_data - State after hardware probe
1215 	return &probe_data->efx;  in efx_netdev_priv()
1220 	return efx->net_dev->reg_state == NETREG_REGISTERED;  in efx_dev_registered()
1225 	return efx->port_num;  in efx_port_num()
1243  * struct efx_nic_type - Efx device type definition
1260  * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1285  *	The SDU length may be any value from 0 up to the protocol-
1295  * @irq_enable_master: Enable IRQs on the NIC.  Each event queue must
1298  * @irq_disable_non_ev: Disable non-event IRQs on the NIC.  Each event
1299  *	queue must be separately disabled before this.
1304  * @tx_probe: Allocate resources for TX queue (and select TXQ type)
1305  * @tx_init: Initialise TX queue on the NIC
1306  * @tx_remove: Free resources for TX queue
1308  * @tx_enqueue: Add an SKB to TX queue
1315  * @rx_probe: Allocate resources for RX queue
1316  * @rx_init: Initialise RX queue on the NIC
1317  * @rx_remove: Free resources for RX queue
1318  * @rx_write: Write RX descriptors and doorbell
1320  * @rx_packet: Receive the queued RX buffer on a channel
1321  * @rx_buf_hash_valid: Determine whether the RX prefix contains a valid hash
1322  * @ev_probe: Allocate resources for event queue
1323  * @ev_init: Initialise event queue on the NIC
1324  * @ev_fini: Deinitialise event queue on the NIC
1325  * @ev_remove: Free resources for event queue
1326  * @ev_process: Process events for a queue, up to the given NAPI quota
1327  * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1332  * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1336  * @filter_clear_rx: Remove all RX filters whose priority is less than or
1340  * @filter_get_rx_ids: Get list of RX filters at a given priority
1350  * @mtd_sync: Wait for write-back to complete on MTD partition.  This
1354  * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1361  * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1365  * @print_additional_fwver: Dump NIC-specific additional FW version info
1367  * @rx_recycle_ring_size: Size of the RX recycle ring
1370  * @rxd_ptr_tbl_base: RX descriptor ring base address
1372  * @evq_ptr_tbl_base: Event queue pointer table base address
1373  * @evq_rptr_tbl_base: Event queue read-pointer table base address
1375  * @rx_prefix_size: Size of RX prefix before packet data
1376  * @rx_hash_offset: Offset of RX flow hash within prefix
1378  * @rx_buffer_padding: Size of padding at end of RX packet
1576 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);  in efx_get_channel()
1577 	return efx->channel[index];  in efx_get_channel()
1582 	for (_channel = (_efx)->channel[0];				\
1584 	     _channel = (_channel->channel + 1 < (_efx)->n_channels) ?	\
1585 		     (_efx)->channel[_channel->channel + 1] : NULL)
1589 	for (_channel = (_efx)->channel[(_efx)->n_channels - 1];	\
1591 	     _channel = _channel->channel ?				\
1592 		     (_efx)->channel[_channel->channel - 1] : NULL)
1597 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);  in efx_get_tx_channel()
1598 	return efx->channel[efx->tx_channel_offset + index];  in efx_get_tx_channel()
1604 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);  in efx_get_xdp_channel()
1605 	return efx->channel[efx->xdp_channel_offset + index];  in efx_get_xdp_channel()
1610 	return channel->channel - channel->efx->xdp_channel_offset <  in efx_channel_is_xdp_tx()
1611 	       channel->efx->n_xdp_channels;  in efx_channel_is_xdp_tx()
1616 	return channel && channel->channel >= channel->efx->tx_channel_offset;  in efx_channel_has_tx_queues()
1622 		return channel->efx->xdp_tx_per_channel;  in efx_channel_num_tx_queues()
1623 	return channel->efx->tx_queues_per_channel;  in efx_channel_num_tx_queues()
1630 	return channel->tx_queue_by_type[type];  in efx_channel_get_tx_queue()
1646 		for (_tx_queue = (_channel)->tx_queue;			\
1647 		     _tx_queue < (_channel)->tx_queue +			\
1653 	return channel->rx_queue.core_index >= 0;  in efx_channel_has_rx_queue()
1660 	return &channel->rx_queue;  in efx_channel_get_rx_queue()
1663 /* Iterate over all RX queues belonging to a channel */
1668 		for (_rx_queue = &(_channel)->rx_queue;			\
1680 	return efx_rx_queue_channel(rx_queue)->channel;  in efx_rx_queue_index()
1683 /* Returns a pointer to the specified receive buffer in the RX
1684  * descriptor queue.
1689 	return &rx_queue->buffer[index];  in efx_rx_buffer()
1695 	if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))  in efx_rx_buf_next()
1702  * EFX_MAX_FRAME_LEN - calculate maximum frame length
1710  * The 10G MAC requires 8-byte alignment on the frame
1713  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1724 	return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;  in efx_xmit_with_hwtstamp()
1728 	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;  in efx_xmit_hwtstamp_pending()
1740 				 tx_queue->insert_count - tx_queue->read_count);  in efx_channel_tx_fill_level()
1754 				 tx_queue->insert_count - tx_queue->old_read_count);  in efx_channel_tx_old_fill_level()
1766 	const struct net_device *net_dev = efx->net_dev;  in efx_supported_features()
1768 	return net_dev->features | net_dev->hw_features;  in efx_supported_features()
1771 /* Get the current TX queue insert index. */
1775 	return tx_queue->insert_count & tx_queue->ptr_mask;  in efx_tx_queue_get_insert_index()
1782 	return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];  in __efx_tx_queue_get_insert_buffer()
1792 	EFX_WARN_ON_ONCE_PARANOID(buffer->len);  in efx_tx_queue_get_insert_buffer()
1793 	EFX_WARN_ON_ONCE_PARANOID(buffer->flags);  in efx_tx_queue_get_insert_buffer()
1794 	EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);  in efx_tx_queue_get_insert_buffer()