Lines Matching +full:0 +full:x00000200
29 EDSR = 0,
127 /* TSU_ADR{H,L}{0..31} are assumed to be contiguous */
164 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
170 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
175 EDMR_NBST = 0x80,
176 EDMR_EL = 0x40, /* Litte endian */
177 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
178 EDMR_SRST_GETHER = 0x03,
179 EDMR_SRST_ETHER = 0x01,
184 EDTRR_TRNS_GETHER = 0x03,
185 EDTRR_TRNS_ETHER = 0x01,
190 EDRRR_R = 0x01,
195 TPAUSER_TPAUSE = 0x0000ffff,
196 TPAUSER_UNLIMITED = 0,
201 BCFR_RPAUSE = 0x0000ffff,
202 BCFR_UNLIMITED = 0,
207 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
211 enum PSR_BIT { PSR_LMON = 0x01, };
215 EESR_TWB1 = 0x80000000,
216 EESR_TWB = 0x40000000, /* same as TWB0 */
217 EESR_TC1 = 0x20000000,
218 EESR_TUC = 0x10000000,
219 EESR_ROC = 0x08000000,
220 EESR_TABT = 0x04000000,
221 EESR_RABT = 0x02000000,
222 EESR_RFRMER = 0x01000000, /* same as RFCOF */
223 EESR_ADE = 0x00800000,
224 EESR_ECI = 0x00400000,
225 EESR_FTC = 0x00200000, /* same as TC or TC0 */
226 EESR_TDE = 0x00100000,
227 EESR_TFE = 0x00080000, /* same as TFUF */
228 EESR_FRC = 0x00040000, /* same as FR */
229 EESR_RDE = 0x00020000,
230 EESR_RFE = 0x00010000,
231 EESR_CND = 0x00000800,
232 EESR_DLC = 0x00000400,
233 EESR_CD = 0x00000200,
234 EESR_TRO = 0x00000100,
235 EESR_RMAF = 0x00000080,
236 EESR_CEEF = 0x00000040,
237 EESR_CELF = 0x00000020,
238 EESR_RRF = 0x00000010,
239 EESR_RTLF = 0x00000008,
240 EESR_RTSF = 0x00000004,
241 EESR_PRE = 0x00000002,
242 EESR_CERF = 0x00000001,
261 EESIPR_TWB1IP = 0x80000000,
262 EESIPR_TWBIP = 0x40000000, /* same as TWB0IP */
263 EESIPR_TC1IP = 0x20000000,
264 EESIPR_TUCIP = 0x10000000,
265 EESIPR_ROCIP = 0x08000000,
266 EESIPR_TABTIP = 0x04000000,
267 EESIPR_RABTIP = 0x02000000,
268 EESIPR_RFCOFIP = 0x01000000,
269 EESIPR_ADEIP = 0x00800000,
270 EESIPR_ECIIP = 0x00400000,
271 EESIPR_FTCIP = 0x00200000, /* same as TC0IP */
272 EESIPR_TDEIP = 0x00100000,
273 EESIPR_TFUFIP = 0x00080000,
274 EESIPR_FRIP = 0x00040000,
275 EESIPR_RDEIP = 0x00020000,
276 EESIPR_RFOFIP = 0x00010000,
277 EESIPR_CNDIP = 0x00000800,
278 EESIPR_DLCIP = 0x00000400,
279 EESIPR_CDIP = 0x00000200,
280 EESIPR_TROIP = 0x00000100,
281 EESIPR_RMAFIP = 0x00000080,
282 EESIPR_CEEFIP = 0x00000040,
283 EESIPR_CELFIP = 0x00000020,
284 EESIPR_RRFIP = 0x00000010,
285 EESIPR_RTLFIP = 0x00000008,
286 EESIPR_RTSFIP = 0x00000004,
287 EESIPR_PREIP = 0x00000002,
288 EESIPR_CERFIP = 0x00000001,
293 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
294 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
295 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
302 RMCR_RNC = 0x00000001,
307 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
308 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
309 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
310 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
311 ECMR_MPDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
312 ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
313 ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
318 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
319 ECSR_LCHNG = 0x04,
320 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
328 ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
329 ECSIPR_LCHNGIP = 0x04,
330 ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
338 APR_AP = 0x0000ffff,
343 MPR_MP = 0x0000ffff,
348 TRSCER_CNDCE = 0x00000800,
349 TRSCER_DLCCE = 0x00000400,
350 TRSCER_CDCE = 0x00000200,
351 TRSCER_TROCE = 0x00000100,
352 TRSCER_RMAFCE = 0x00000080,
353 TRSCER_RRFCE = 0x00000010,
354 TRSCER_RTLFCE = 0x00000008,
355 TRSCER_RTSFCE = 0x00000004,
356 TRSCER_PRECE = 0x00000002,
357 TRSCER_CERFCE = 0x00000001,
364 RPADIR_PADS = 0x1f0000, RPADIR_PADR = 0xffff,
368 #define DEFAULT_FDR_INIT 0x00000707
371 enum ARSTR_BIT { ARSTR_ARST = 0x00000001, };
375 TSU_FWEN0_0 = 0x00000001,
380 TSU_ADSBSY_0 = 0x00000001,
385 TSU_TEN_0 = 0x80000000,
390 TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
391 TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
392 TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
397 TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
398 TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
399 TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
400 TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
401 TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
405 #define TSU_VTAG_ENABLE 0x80000000
406 #define TSU_VTAG_VID_MASK 0x00000fff
418 /* Transmit descriptor 0 bits */
420 TD_TACT = 0x80000000,
421 TD_TDLE = 0x40000000,
422 TD_TFP1 = 0x20000000,
423 TD_TFP0 = 0x10000000,
424 TD_TFE = 0x08000000,
425 TD_TWBI = 0x04000000,
433 TD_TBL = 0xffff0000, /* transmit buffer length */
446 /* Receive descriptor 0 bits */
448 RD_RACT = 0x80000000,
449 RD_RDLE = 0x40000000,
450 RD_RFP1 = 0x20000000,
451 RD_RFP0 = 0x10000000,
452 RD_RFE = 0x08000000,
453 RD_RFS10 = 0x00000200,
454 RD_RFS9 = 0x00000100,
455 RD_RFS8 = 0x00000080,
456 RD_RFS7 = 0x00000040,
457 RD_RFS6 = 0x00000020,
458 RD_RFS5 = 0x00000010,
459 RD_RFS4 = 0x00000008,
460 RD_RFS3 = 0x00000004,
461 RD_RFS2 = 0x00000002,
462 RD_RFS1 = 0x00000001,
470 RD_RFL = 0x0000ffff, /* receive frame length */
471 RD_RBL = 0xffff0000, /* receive buffer length */