Lines Matching +full:0 +full:x3fffc000
12 #define RTASE_HW_VER_MASK 0x7C800000
13 #define RTASE_HW_VER_906X_7XA 0x00800000
14 #define RTASE_HW_VER_906X_7XC 0x04000000
15 #define RTASE_HW_VER_907XD_V1 0x04800000
16 #define RTASE_HW_VER_907XD_VA 0x08000000
26 #define RTASE_INTERFRAMEGAP 0x03
29 #define RTASE_PCI_REGS_SIZE 0x100
42 #define RTASE_MITI_TIME_COUNT_MASK GENMASK(3, 0)
60 RTASE_MAC0 = 0x0000,
61 RTASE_MAC4 = 0x0004,
62 RTASE_MAR0 = 0x0008,
63 RTASE_MAR1 = 0x000C,
64 RTASE_DTCCR0 = 0x0010,
65 RTASE_DTCCR4 = 0x0014,
66 #define RTASE_COUNTER_RESET BIT(0)
69 RTASE_FCR = 0x0018,
72 RTASE_LBK_CTRL = 0x001A,
74 #define RTASE_LBK_CLR BIT(0)
76 RTASE_TX_DESC_ADDR0 = 0x0020,
77 RTASE_TX_DESC_ADDR4 = 0x0024,
78 RTASE_TX_DESC_COMMAND = 0x0028,
82 RTASE_BOOT_CTL = 0x6004,
83 RTASE_CLKSW_SET = 0x6018,
85 RTASE_CHIP_CMD = 0x0037,
91 RTASE_IMR0 = 0x0038,
92 RTASE_ISR0 = 0x003C,
100 #define RTASE_ROK BIT(0)
102 RTASE_IMR1 = 0x0800,
103 RTASE_ISR1 = 0x0802,
106 #define RTASE_Q_ROK BIT(0)
108 RTASE_EPHY_ISR = 0x6014,
109 RTASE_EPHY_IMR = 0x6016,
111 RTASE_TX_CONFIG_0 = 0x0040,
113 /* DMA burst value (0-7) is shift this many bits */
116 RTASE_RX_CONFIG_0 = 0x0044,
126 #define RTASE_ACCEPT_ALLPHYS BIT(0)
132 RTASE_RX_CONFIG_1 = 0x0046,
138 #define RTASE_PCIE_RELOAD_EN BIT(0)
140 RTASE_EEM = 0x0050,
141 #define RTASE_EEM_UNLOCK 0xC0
143 RTASE_TDFNR = 0x0057,
144 RTASE_TPPOLL = 0x0090,
145 RTASE_PDR = 0x00B0,
146 RTASE_FIFOR = 0x00D3,
150 RTASE_RMS = 0x00DA,
151 RTASE_CPLUS_CMD = 0x00E0,
156 RTASE_Q0_RX_DESC_ADDR0 = 0x00E4,
157 RTASE_Q0_RX_DESC_ADDR4 = 0x00E8,
158 RTASE_Q1_RX_DESC_ADDR0 = 0x4000,
159 RTASE_Q1_RX_DESC_ADDR4 = 0x4004,
160 RTASE_MTPS = 0x00EC,
163 RTASE_MISC = 0x00F2,
166 RTASE_TFUN_CTRL = 0x0400,
167 #define RTASE_TX_NEW_DESC_FORMAT_EN BIT(0)
169 RTASE_TX_CONFIG_1 = 0x203E,
172 RTASE_TOKSEL = 0x2046,
173 RTASE_RFIFONFULL = 0x4406,
174 RTASE_INT_MITI_TX = 0x0A00,
175 RTASE_INT_MITI_RX = 0x0A80,
177 RTASE_VLAN_ENTRY_0 = 0xAC80,
190 #define RSVD_MASK 0x3FFFC000
202 /*------ offset 0 of tx descriptor ------*/
259 #define RTASE_VLAN_TAG_MASK GENMASK(15, 0)
260 #define RTASE_RX_PKT_SIZE_MASK GENMASK(13, 0)