50 #define MCR0		0x00	/* Control register 0 */
51 #define  MCR0_RCVEN	0x0002	/* Receive enable */
52 #define  MCR0_PROMISC	0x0020	/* Promiscuous mode */
53 #define  MCR0_HASH_EN	0x0100	/* Enable multicast hash table function */
54 #define  MCR0_XMTEN	0x1000	/* Transmission enable */
55 #define  MCR0_FD	0x8000	/* Full/Half duplex */
56 #define MCR1		0x04	/* Control register 1 */
57 #define  MAC_RST	0x0001	/* Reset the MAC */
58 #define MBCR		0x08	/* Bus control */
59 #define MT_ICR		0x0C	/* TX interrupt control */
60 #define MR_ICR		0x10	/* RX interrupt control */
61 #define MTPR		0x14	/* TX poll command register */
62 #define  TM2TX		0x0001	/* Trigger MAC to transmit */
63 #define MR_BSR		0x18	/* RX buffer size */
64 #define MR_DCR		0x1A	/* RX descriptor control */
65 #define MLSR		0x1C	/* Last status */
66 #define  TX_FIFO_UNDR	0x0200	/* TX FIFO under-run */
67 #define	 TX_EXCEEDC	0x2000	/* Transmit exceed collision */
68 #define  TX_LATEC	0x4000	/* Transmit late collision */
69 #define MMDIO		0x20	/* MDIO control register */
70 #define  MDIO_WRITE	0x4000	/* MDIO write */
71 #define  MDIO_READ	0x2000	/* MDIO read */
72 #define MMRD		0x24	/* MDIO read data register */
73 #define MMWD		0x28	/* MDIO write data register */
74 #define MTD_SA0		0x2C	/* TX descriptor start address 0 */
75 #define MTD_SA1		0x30	/* TX descriptor start address 1 */
76 #define MRD_SA0		0x34	/* RX descriptor start address 0 */
77 #define MRD_SA1		0x38	/* RX descriptor start address 1 */
78 #define MISR		0x3C	/* Status register */
79 #define MIER		0x40	/* INT enable register */
80 #define  MSK_INT	0x0000	/* Mask off interrupts */
81 #define  RX_FINISH	0x0001  /* RX finished */
82 #define  RX_NO_DESC	0x0002  /* No RX descriptor available */
83 #define  RX_FIFO_FULL	0x0004  /* RX FIFO full */
84 #define  RX_EARLY	0x0008  /* RX early */
85 #define  TX_FINISH	0x0010  /* TX finished */
86 #define  TX_EARLY	0x0080  /* TX early */
87 #define  EVENT_OVRFL	0x0100  /* Event counter overflow */
88 #define  LINK_CHANGED	0x0200  /* PHY link changed */
89 #define ME_CISR		0x44	/* Event counter INT status */
90 #define ME_CIER		0x48	/* Event counter INT enable  */
91 #define MR_CNT		0x50	/* Successfully received packet counter */
92 #define ME_CNT0		0x52	/* Event counter 0 */
93 #define ME_CNT1		0x54	/* Event counter 1 */
94 #define ME_CNT2		0x56	/* Event counter 2 */
95 #define ME_CNT3		0x58	/* Event counter 3 */
96 #define MT_CNT		0x5A	/* Successfully transmit packet counter */
97 #define ME_CNT4		0x5C	/* Event counter 4 */
98 #define MP_CNT		0x5E	/* Pause frame counter register */
99 #define MAR0		0x60	/* Hash table 0 */
100 #define MAR1		0x62	/* Hash table 1 */
101 #define MAR2		0x64	/* Hash table 2 */
102 #define MAR3		0x66	/* Hash table 3 */
103 #define MID_0L		0x68	/* Multicast address MID0 Low */
104 #define MID_0M		0x6A	/* Multicast address MID0 Medium */
105 #define MID_0H		0x6C	/* Multicast address MID0 High */
106 #define MID_1L		0x70	/* MID1 Low */
107 #define MID_1M		0x72	/* MID1 Medium */
108 #define MID_1H		0x74	/* MID1 High */
109 #define MID_2L		0x78	/* MID2 Low */
110 #define MID_2M		0x7A	/* MID2 Medium */
111 #define MID_2H		0x7C	/* MID2 High */
112 #define MID_3L		0x80	/* MID3 Low */
113 #define MID_3M		0x82	/* MID3 Medium */
114 #define MID_3H		0x84	/* MID3 High */
115 #define PHY_CC		0x88	/* PHY status change configuration register */
116 #define  SCEN		0x8000	/* PHY status change enable */
118 #define  TMRDIV_SHIFT	0	/* Timer divider shift */
119 #define PHY_ST		0x8A	/* PHY status register */
120 #define MAC_SM		0xAC	/* MAC status machine */
121 #define  MAC_SM_RST	0x0002	/* MAC status machine reset */
122 #define MD_CSC		0xb6	/* MDC speed control register */
123 #define  MD_CSC_DEFAULT	0x0030
124 #define MAC_ID		0xBE	/* Identifier register */
126 #define TX_DCNT		0x80	/* TX descriptor count */
127 #define RX_DCNT		0x80	/* RX descriptor count */
128 #define MAX_BUF_SIZE	0x600
131 #define MBCR_DEFAULT	0x012A	/* MAC Bus Control Register */
137 #define DSC_OWNER_MAC	0x8000	/* MAC is the owner of this descriptor */
138 #define DSC_RX_OK	0x4000	/* RX was successful */
139 #define DSC_RX_ERR	0x0800	/* RX PHY error */
140 #define DSC_RX_ERR_DRI	0x0400	/* RX dribble packet */
141 #define DSC_RX_ERR_BUF	0x0200	/* RX length exceeds buffer size */
142 #define DSC_RX_ERR_LONG	0x0100	/* RX length > maximum packet length */
143 #define DSC_RX_ERR_RUNT	0x0080	/* RX packet length < 64 byte */
144 #define DSC_RX_ERR_CRC	0x0040	/* RX CRC error */
145 #define DSC_RX_BCAST	0x0020	/* RX broadcast (no error) */
146 #define DSC_RX_MCAST	0x0010	/* RX multicast (no error) */
147 #define DSC_RX_MCH_HIT	0x0008	/* RX multicast hit in hash table (no error) */
148 #define DSC_RX_MIDH_HIT	0x0004	/* RX MID table hit (no error) */
164 	u16	status, len;		/* 0-3 */
214 	if (limit < 0)  in r6040_phy_read()
238 	return (limit < 0) ? -ETIMEDOUT : 0;  in r6040_phy_write()
265 	for (i = 0; i < TX_DCNT; i++) {  in r6040_free_txbufs()
282 	for (i = 0; i < RX_DCNT; i++) {  in r6040_free_rxbufs()
300 	while (size-- > 0) {  in r6040_init_ring_desc()
348 	return 0;  in r6040_alloc_rxbufs()
372 	iowrite16(0, ioaddr + MAC_SM);  in r6040_reset_mac()
406 	iowrite16(0, ioaddr + MT_ICR);  in r6040_init_mac_regs()
407 	iowrite16(0, ioaddr + MR_ICR);  in r6040_init_mac_regs()
466 	iowrite16(adrp[0], ioaddr + MID_0L);  in r6040_down()
506 	return 0;  in r6040_close()
514 	int count = 0;  in r6040_rx()
661 	if (status == 0x0000 || status == 0xffff) {  in r6040_interrupt()
714 			(r6040_phy_read(ioaddr, 30, 17) | 0x4000));  in r6040_up()
716 			~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));  in r6040_up()
717 	r6040_phy_write(ioaddr, 0, 19, 0x0000);  in r6040_up()
718 	r6040_phy_write(ioaddr, 0, 30, 0x01F0);  in r6040_up()
725 	return 0;  in r6040_up()
741 	iowrite16(adrp[0], ioaddr + MID_0L);  in r6040_mac_address()
784 	return 0;  in r6040_open()
806 	if (skb_put_padto(skb, ETH_ZLEN) < 0)  in r6040_start_xmit()
853 	u16 hash_table[4] = { 0 };  in r6040_multicast_list()
859 	iowrite16(adrp[0], ioaddr + MID_0L);  in r6040_multicast_list()
875 		for (i = 0; i < MCAST_MAX ; i++) {  in r6040_multicast_list()
876 			iowrite16(0, ioaddr + MID_1L + 8 * i);  in r6040_multicast_list()
877 			iowrite16(0, ioaddr + MID_1M + 8 * i);  in r6040_multicast_list()
878 			iowrite16(0, ioaddr + MID_1H + 8 * i);  in r6040_multicast_list()
881 		for (i = 0; i < 4; i++)  in r6040_multicast_list()
882 			hash_table[i] = 0xffff;  in r6040_multicast_list()
887 		i = 0;  in r6040_multicast_list()
890 			iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);  in r6040_multicast_list()
896 			iowrite16(0, ioaddr + MID_1L + 8 * i);  in r6040_multicast_list()
897 			iowrite16(0, ioaddr + MID_1M + 8 * i);  in r6040_multicast_list()
898 			iowrite16(0, ioaddr + MID_1H + 8 * i);  in r6040_multicast_list()
908 		for (i = 0; i < MCAST_MAX ; i++) {  in r6040_multicast_list()
909 			iowrite16(0, ioaddr + MID_1L + 8 * i);  in r6040_multicast_list()
910 			iowrite16(0, ioaddr + MID_1M + 8 * i);  in r6040_multicast_list()
911 			iowrite16(0, ioaddr + MID_1H + 8 * i);  in r6040_multicast_list()
920 			hash_table[crc >> 4] |= 1 << (crc & 0xf);  in r6040_multicast_list()
928 		iowrite16(hash_table[0], ioaddr + MAR0);  in r6040_multicast_list()
975 	int status_changed = 0;  in r6040_adjust_link()
987 		lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);  in r6040_adjust_link()
1019 	lp->old_link = 0;  in r6040_mii_probe()
1024 	return 0;  in r6040_mii_probe()
1035 	int bar = 0;  in r6040_init_one()
1091 	if (ioread16(ioaddr + PHY_CC) == 0)  in r6040_init_one()
1105 	addr[0] = ioread16(ioaddr + MID_0L);  in r6040_init_one()
1112 	if (!(addr[0] || addr[1] || addr[2])) {  in r6040_init_one()
1164 	return 0;  in r6040_init_one()
1203 	{ PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1204 	{ 0 }