Lines Matching +full:multi +full:- +full:ported
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
41 #include <linux/dma-mapping.h>
43 #include <linux/io-mapping.h>
48 #include <uapi/rdma/mlx4-abi.h>
57 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
75 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi…
103 " flow steering when available, set to -1");
147 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
151 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
152 /* Log2 max number of VLANs per ETH port (0-7) */
164 "(0-7) (default: 0)");
177 ctx->val.vbool = !!mlx4_internal_err_reset; in mlx4_devlink_ierr_reset_get()
185 mlx4_internal_err_reset = ctx->val.vbool; in mlx4_devlink_ierr_reset_set()
193 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_crdump_snapshot_get()
195 ctx->val.vbool = dev->persist->crdump.snapshot_enable; in mlx4_devlink_crdump_snapshot_get()
204 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_crdump_snapshot_set()
206 dev->persist->crdump.snapshot_enable = ctx->val.vbool; in mlx4_devlink_crdump_snapshot_set()
218 return -ERANGE; in mlx4_devlink_max_macs_validate()
222 return -EINVAL; in mlx4_devlink_max_macs_validate()
295 dev->caps.reserved_uars = in mlx4_set_num_reserved_uars()
298 dev_cap->reserved_uars / in mlx4_set_num_reserved_uars()
299 (1 << (PAGE_SHIFT - dev->uar_page_shift))); in mlx4_set_num_reserved_uars()
307 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { in mlx4_check_port_params()
308 for (i = 0; i < dev->caps.num_ports - 1; i++) { in mlx4_check_port_params()
311 return -EOPNOTSUPP; in mlx4_check_port_params()
316 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_check_port_params()
317 if (!(port_type[i] & dev->caps.supported_type[i+1])) { in mlx4_check_port_params()
320 return -EOPNOTSUPP; in mlx4_check_port_params()
330 for (i = 1; i <= dev->caps.num_ports; ++i) in mlx4_set_port_mask()
331 dev->caps.port_mask[i] = dev->caps.port_type[i]; in mlx4_set_port_mask()
343 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { in mlx4_query_func()
349 dev_cap->max_eqs = func.max_eq; in mlx4_query_func()
350 dev_cap->reserved_eqs = func.rsvd_eqs; in mlx4_query_func()
351 dev_cap->reserved_uars = func.rsvd_uars; in mlx4_query_func()
359 struct mlx4_caps *dev_cap = &dev->caps; in mlx4_enable_cqe_eqe_stride()
362 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || in mlx4_enable_cqe_eqe_stride()
363 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) in mlx4_enable_cqe_eqe_stride()
369 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || in mlx4_enable_cqe_eqe_stride()
370 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) { in mlx4_enable_cqe_eqe_stride()
371 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
372 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
379 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; in mlx4_enable_cqe_eqe_stride()
380 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; in mlx4_enable_cqe_eqe_stride()
383 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
387 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
388 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; in mlx4_enable_cqe_eqe_stride()
395 dev->caps.vl_cap[port] = port_cap->max_vl; in _mlx4_dev_port()
396 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; in _mlx4_dev_port()
397 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; in _mlx4_dev_port()
398 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; in _mlx4_dev_port()
400 * to non-sriov values in _mlx4_dev_port()
402 dev->caps.gid_table_len[port] = port_cap->max_gids; in _mlx4_dev_port()
403 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; in _mlx4_dev_port()
404 dev->caps.port_width_cap[port] = port_cap->max_port_width; in _mlx4_dev_port()
405 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; in _mlx4_dev_port()
406 dev->caps.max_tc_eth = port_cap->max_tc_eth; in _mlx4_dev_port()
407 dev->caps.def_mac[port] = port_cap->def_mac; in _mlx4_dev_port()
408 dev->caps.supported_type[port] = port_cap->supported_port_types; in _mlx4_dev_port()
409 dev->caps.suggested_type[port] = port_cap->suggested_type; in _mlx4_dev_port()
410 dev->caps.default_sense[port] = port_cap->default_sense; in _mlx4_dev_port()
411 dev->caps.trans_type[port] = port_cap->trans_type; in _mlx4_dev_port()
412 dev->caps.vendor_oui[port] = port_cap->vendor_oui; in _mlx4_dev_port()
413 dev->caps.wavelength[port] = port_cap->wavelength; in _mlx4_dev_port()
414 dev->caps.trans_code[port] = port_cap->trans_code; in _mlx4_dev_port()
434 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)) in mlx4_enable_ignore_fcs()
438 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS"); in mlx4_enable_ignore_fcs()
439 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; in mlx4_enable_ignore_fcs()
443 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) { in mlx4_enable_ignore_fcs()
445 "Keep FCS is not supported - Disabling Ignore FCS"); in mlx4_enable_ignore_fcs()
446 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS; in mlx4_enable_ignore_fcs()
464 if (dev_cap->min_page_sz > PAGE_SIZE) { in mlx4_dev_cap()
466 dev_cap->min_page_sz, PAGE_SIZE); in mlx4_dev_cap()
467 return -ENODEV; in mlx4_dev_cap()
469 if (dev_cap->num_ports > MLX4_MAX_PORTS) { in mlx4_dev_cap()
471 dev_cap->num_ports, MLX4_MAX_PORTS); in mlx4_dev_cap()
472 return -ENODEV; in mlx4_dev_cap()
475 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) { in mlx4_dev_cap()
477 dev_cap->uar_size, in mlx4_dev_cap()
479 pci_resource_len(dev->persist->pdev, 2)); in mlx4_dev_cap()
480 return -ENODEV; in mlx4_dev_cap()
483 dev->caps.num_ports = dev_cap->num_ports; in mlx4_dev_cap()
484 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs; in mlx4_dev_cap()
485 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ? in mlx4_dev_cap()
486 dev->caps.num_sys_eqs : in mlx4_dev_cap()
488 for (i = 1; i <= dev->caps.num_ports; ++i) { in mlx4_dev_cap()
489 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i); in mlx4_dev_cap()
496 dev->caps.map_clock_to_user = dev_cap->map_clock_to_user; in mlx4_dev_cap()
497 dev->caps.uar_page_size = PAGE_SIZE; in mlx4_dev_cap()
498 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; in mlx4_dev_cap()
499 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; in mlx4_dev_cap()
500 dev->caps.bf_reg_size = dev_cap->bf_reg_size; in mlx4_dev_cap()
501 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; in mlx4_dev_cap()
502 dev->caps.max_sq_sg = dev_cap->max_sq_sg; in mlx4_dev_cap()
503 dev->caps.max_rq_sg = dev_cap->max_rq_sg; in mlx4_dev_cap()
504 dev->caps.max_wqes = dev_cap->max_qp_sz; in mlx4_dev_cap()
505 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; in mlx4_dev_cap()
506 dev->caps.max_srq_wqes = dev_cap->max_srq_sz; in mlx4_dev_cap()
507 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; in mlx4_dev_cap()
508 dev->caps.reserved_srqs = dev_cap->reserved_srqs; in mlx4_dev_cap()
509 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; in mlx4_dev_cap()
510 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; in mlx4_dev_cap()
515 dev->caps.max_cqes = dev_cap->max_cq_sz - 1; in mlx4_dev_cap()
516 dev->caps.reserved_cqs = dev_cap->reserved_cqs; in mlx4_dev_cap()
517 dev->caps.reserved_eqs = dev_cap->reserved_eqs; in mlx4_dev_cap()
518 dev->caps.reserved_mtts = dev_cap->reserved_mtts; in mlx4_dev_cap()
519 dev->caps.reserved_mrws = dev_cap->reserved_mrws; in mlx4_dev_cap()
521 dev->caps.reserved_pds = dev_cap->reserved_pds; in mlx4_dev_cap()
522 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? in mlx4_dev_cap()
523 dev_cap->reserved_xrcds : 0; in mlx4_dev_cap()
524 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? in mlx4_dev_cap()
525 dev_cap->max_xrcds : 0; in mlx4_dev_cap()
526 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; in mlx4_dev_cap()
528 dev->caps.max_msg_sz = dev_cap->max_msg_sz; in mlx4_dev_cap()
529 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); in mlx4_dev_cap()
530 dev->caps.flags = dev_cap->flags; in mlx4_dev_cap()
531 dev->caps.flags2 = dev_cap->flags2; in mlx4_dev_cap()
532 dev->caps.bmme_flags = dev_cap->bmme_flags; in mlx4_dev_cap()
533 dev->caps.reserved_lkey = dev_cap->reserved_lkey; in mlx4_dev_cap()
534 dev->caps.stat_rate_support = dev_cap->stat_rate_support; in mlx4_dev_cap()
535 dev->caps.max_gso_sz = dev_cap->max_gso_sz; in mlx4_dev_cap()
536 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; in mlx4_dev_cap()
537 dev->caps.wol_port[1] = dev_cap->wol_port[1]; in mlx4_dev_cap()
538 dev->caps.wol_port[2] = dev_cap->wol_port[2]; in mlx4_dev_cap()
539 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs; in mlx4_dev_cap()
546 if (enable_4k_uar || !dev->persist->num_vfs) in mlx4_dev_cap()
547 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT; in mlx4_dev_cap()
549 dev->uar_page_shift = PAGE_SHIFT; in mlx4_dev_cap()
554 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) { in mlx4_dev_cap()
566 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN; in mlx4_dev_cap()
569 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ in mlx4_dev_cap()
570 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) in mlx4_dev_cap()
571 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; in mlx4_dev_cap()
574 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; in mlx4_dev_cap()
577 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC; in mlx4_dev_cap()
578 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS; in mlx4_dev_cap()
580 dev->caps.log_num_macs = log_num_mac; in mlx4_dev_cap()
581 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; in mlx4_dev_cap()
584 for (i = 1; i <= dev->caps.num_ports; ++i) { in mlx4_dev_cap()
585 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; in mlx4_dev_cap()
586 if (dev->caps.supported_type[i]) { in mlx4_dev_cap()
587 /* if only ETH is supported - assign ETH */ in mlx4_dev_cap()
588 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) in mlx4_dev_cap()
589 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; in mlx4_dev_cap()
591 else if (dev->caps.supported_type[i] == in mlx4_dev_cap()
593 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; in mlx4_dev_cap()
598 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) in mlx4_dev_cap()
599 dev->caps.port_type[i] = dev->caps.suggested_type[i] ? in mlx4_dev_cap()
602 dev->caps.port_type[i] = port_type_array[i - 1]; in mlx4_dev_cap()
611 mlx4_priv(dev)->sense.sense_allowed[i] = in mlx4_dev_cap()
612 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && in mlx4_dev_cap()
613 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && in mlx4_dev_cap()
614 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); in mlx4_dev_cap()
621 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { in mlx4_dev_cap()
623 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; in mlx4_dev_cap()
626 dev->caps.port_type[i] = sensed_port; in mlx4_dev_cap()
628 dev->caps.possible_type[i] = dev->caps.port_type[i]; in mlx4_dev_cap()
631 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) { in mlx4_dev_cap()
632 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs; in mlx4_dev_cap()
634 i, 1 << dev->caps.log_num_macs); in mlx4_dev_cap()
636 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) { in mlx4_dev_cap()
637 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans; in mlx4_dev_cap()
639 i, 1 << dev->caps.log_num_vlans); in mlx4_dev_cap()
643 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) && in mlx4_dev_cap()
648 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP; in mlx4_dev_cap()
651 dev->caps.max_counters = dev_cap->max_counters; in mlx4_dev_cap()
653 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; in mlx4_dev_cap()
654 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = in mlx4_dev_cap()
655 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = in mlx4_dev_cap()
656 (1 << dev->caps.log_num_macs) * in mlx4_dev_cap()
657 (1 << dev->caps.log_num_vlans) * in mlx4_dev_cap()
658 dev->caps.num_ports; in mlx4_dev_cap()
659 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; in mlx4_dev_cap()
661 if (dev_cap->dmfs_high_rate_qpn_base > 0 && in mlx4_dev_cap()
662 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) in mlx4_dev_cap()
663 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base; in mlx4_dev_cap()
665 dev->caps.dmfs_high_rate_qpn_base = in mlx4_dev_cap()
666 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; in mlx4_dev_cap()
668 if (dev_cap->dmfs_high_rate_qpn_range > 0 && in mlx4_dev_cap()
669 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) { in mlx4_dev_cap()
670 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range; in mlx4_dev_cap()
671 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT; in mlx4_dev_cap()
672 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0; in mlx4_dev_cap()
674 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED; in mlx4_dev_cap()
675 dev->caps.dmfs_high_rate_qpn_base = in mlx4_dev_cap()
676 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; in mlx4_dev_cap()
677 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE; in mlx4_dev_cap()
680 dev->caps.rl_caps = dev_cap->rl_caps; in mlx4_dev_cap()
682 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] = in mlx4_dev_cap()
683 dev->caps.dmfs_high_rate_qpn_range; in mlx4_dev_cap()
685 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + in mlx4_dev_cap()
686 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + in mlx4_dev_cap()
687 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + in mlx4_dev_cap()
688 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; in mlx4_dev_cap()
690 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; in mlx4_dev_cap()
693 if (dev_cap->flags & in mlx4_dev_cap()
696 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; in mlx4_dev_cap()
697 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; in mlx4_dev_cap()
700 if (dev_cap->flags2 & in mlx4_dev_cap()
704 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE; in mlx4_dev_cap()
705 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE; in mlx4_dev_cap()
709 if ((dev->caps.flags & in mlx4_dev_cap()
712 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; in mlx4_dev_cap()
716 dev->caps.alloc_res_qp_mask = in mlx4_dev_cap()
717 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) | in mlx4_dev_cap()
720 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) && in mlx4_dev_cap()
721 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { in mlx4_dev_cap()
724 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; in mlx4_dev_cap()
728 dev->caps.alloc_res_qp_mask = 0; in mlx4_dev_cap()
744 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { in mlx4_how_many_lives_vf()
745 s_state = &priv->mfunc.master.slave_state[i]; in mlx4_how_many_lives_vf()
746 if (s_state->active && s_state->last_cmd != in mlx4_how_many_lives_vf()
760 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || in mlx4_get_parav_qkey()
761 qpn < dev->phys_caps.base_proxy_sqpn) in mlx4_get_parav_qkey()
762 return -EINVAL; in mlx4_get_parav_qkey()
764 if (qpn >= dev->phys_caps.base_tunnel_sqpn) in mlx4_get_parav_qkey()
766 qk += qpn - dev->phys_caps.base_tunnel_sqpn; in mlx4_get_parav_qkey()
768 qk += qpn - dev->phys_caps.base_proxy_sqpn; in mlx4_get_parav_qkey()
781 priv->virt2phys_pkey[slave][port - 1][i] = val; in mlx4_sync_pkey_table()
792 priv->slave_node_guids[slave] = guid; in mlx4_put_slave_node_guid()
803 return priv->slave_node_guids[slave]; in mlx4_get_slave_node_guid()
815 s_slave = &priv->mfunc.master.slave_state[slave]; in mlx4_is_slave_active()
816 return !!s_slave->active; in mlx4_is_slave_active()
823 if (is_multicast_ether_addr(eth_header->eth.dst_mac) || in mlx4_handle_eth_header_mcast_prio()
824 is_broadcast_ether_addr(eth_header->eth.dst_mac)) { in mlx4_handle_eth_header_mcast_prio()
828 bool last_rule = next_rule->size == 0 && next_rule->id == 0 && in mlx4_handle_eth_header_mcast_prio()
829 next_rule->rsvd == 0; in mlx4_handle_eth_header_mcast_prio()
832 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC); in mlx4_handle_eth_header_mcast_prio()
841 dev->caps.steering_mode = hca_param->steering_mode; in slave_adjust_steering_mode()
842 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { in slave_adjust_steering_mode()
843 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; in slave_adjust_steering_mode()
844 dev->caps.fs_log_max_ucast_qp_range_size = in slave_adjust_steering_mode()
845 dev_cap->fs_log_max_ucast_qp_range_size; in slave_adjust_steering_mode()
847 dev->caps.num_qp_per_mgm = in slave_adjust_steering_mode()
848 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); in slave_adjust_steering_mode()
851 mlx4_steering_mode_str(dev->caps.steering_mode)); in slave_adjust_steering_mode()
856 kfree(dev->caps.spec_qps); in mlx4_slave_destroy_special_qp_cap()
857 dev->caps.spec_qps = NULL; in mlx4_slave_destroy_special_qp_cap()
863 struct mlx4_caps *caps = &dev->caps; in mlx4_slave_special_qp_cap()
867 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL); in mlx4_slave_special_qp_cap()
869 if (!func_cap || !caps->spec_qps) { in mlx4_slave_special_qp_cap()
871 err = -ENOMEM; in mlx4_slave_special_qp_cap()
875 for (i = 1; i <= caps->num_ports; ++i) { in mlx4_slave_special_qp_cap()
882 caps->spec_qps[i - 1] = func_cap->spec_qps; in mlx4_slave_special_qp_cap()
883 caps->port_mask[i] = caps->port_type[i]; in mlx4_slave_special_qp_cap()
884 caps->phys_port_id[i] = func_cap->phys_port_id; in mlx4_slave_special_qp_cap()
886 &caps->gid_table_len[i], in mlx4_slave_special_qp_cap()
887 &caps->pkey_table_len[i]); in mlx4_slave_special_qp_cap()
915 err = -ENOMEM; in mlx4_slave_cap()
928 if (hca_param->global_caps) { in mlx4_slave_cap()
930 err = -EINVAL; in mlx4_slave_cap()
934 dev->caps.hca_core_clock = hca_param->hca_core_clock; in mlx4_slave_cap()
936 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp; in mlx4_slave_cap()
947 page_size = ~dev->caps.page_size_cap + 1; in mlx4_slave_cap()
952 err = -ENODEV; in mlx4_slave_cap()
957 dev->uar_page_shift = hca_param->uar_page_sz + 12; in mlx4_slave_cap()
960 if (dev->uar_page_shift > PAGE_SHIFT) { in mlx4_slave_cap()
963 err = -ENODEV; in mlx4_slave_cap()
974 dev->caps.uar_page_size = PAGE_SIZE; in mlx4_slave_cap()
983 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != in mlx4_slave_cap()
986 func_cap->pf_context_behaviour, in mlx4_slave_cap()
988 err = -EINVAL; in mlx4_slave_cap()
992 dev->caps.num_ports = func_cap->num_ports; in mlx4_slave_cap()
993 dev->quotas.qp = func_cap->qp_quota; in mlx4_slave_cap()
994 dev->quotas.srq = func_cap->srq_quota; in mlx4_slave_cap()
995 dev->quotas.cq = func_cap->cq_quota; in mlx4_slave_cap()
996 dev->quotas.mpt = func_cap->mpt_quota; in mlx4_slave_cap()
997 dev->quotas.mtt = func_cap->mtt_quota; in mlx4_slave_cap()
998 dev->caps.num_qps = 1 << hca_param->log_num_qps; in mlx4_slave_cap()
999 dev->caps.num_srqs = 1 << hca_param->log_num_srqs; in mlx4_slave_cap()
1000 dev->caps.num_cqs = 1 << hca_param->log_num_cqs; in mlx4_slave_cap()
1001 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz; in mlx4_slave_cap()
1002 dev->caps.num_eqs = func_cap->max_eq; in mlx4_slave_cap()
1003 dev->caps.reserved_eqs = func_cap->reserved_eq; in mlx4_slave_cap()
1004 dev->caps.reserved_lkey = func_cap->reserved_lkey; in mlx4_slave_cap()
1005 dev->caps.num_pds = MLX4_NUM_PDS; in mlx4_slave_cap()
1006 dev->caps.num_mgms = 0; in mlx4_slave_cap()
1007 dev->caps.num_amgms = 0; in mlx4_slave_cap()
1009 if (dev->caps.num_ports > MLX4_MAX_PORTS) { in mlx4_slave_cap()
1011 dev->caps.num_ports, MLX4_MAX_PORTS); in mlx4_slave_cap()
1012 err = -ENODEV; in mlx4_slave_cap()
1024 if (dev->caps.uar_page_size * (dev->caps.num_uars - in mlx4_slave_cap()
1025 dev->caps.reserved_uars) > in mlx4_slave_cap()
1026 pci_resource_len(dev->persist->pdev, in mlx4_slave_cap()
1029 dev->caps.uar_page_size * dev->caps.num_uars, in mlx4_slave_cap()
1031 pci_resource_len(dev->persist->pdev, 2)); in mlx4_slave_cap()
1032 err = -ENOMEM; in mlx4_slave_cap()
1036 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { in mlx4_slave_cap()
1037 dev->caps.eqe_size = 64; in mlx4_slave_cap()
1038 dev->caps.eqe_factor = 1; in mlx4_slave_cap()
1040 dev->caps.eqe_size = 32; in mlx4_slave_cap()
1041 dev->caps.eqe_factor = 0; in mlx4_slave_cap()
1044 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { in mlx4_slave_cap()
1045 dev->caps.cqe_size = 64; in mlx4_slave_cap()
1046 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; in mlx4_slave_cap()
1048 dev->caps.cqe_size = 32; in mlx4_slave_cap()
1051 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) { in mlx4_slave_cap()
1052 dev->caps.eqe_size = hca_param->eqe_size; in mlx4_slave_cap()
1053 dev->caps.eqe_factor = 0; in mlx4_slave_cap()
1056 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) { in mlx4_slave_cap()
1057 dev->caps.cqe_size = hca_param->cqe_size; in mlx4_slave_cap()
1059 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; in mlx4_slave_cap()
1062 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; in mlx4_slave_cap()
1065 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN; in mlx4_slave_cap()
1070 hca_param->rss_ip_frags ? "on" : "off"); in mlx4_slave_cap()
1072 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP && in mlx4_slave_cap()
1073 dev->caps.bf_reg_size) in mlx4_slave_cap()
1074 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP; in mlx4_slave_cap()
1076 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP) in mlx4_slave_cap()
1077 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP; in mlx4_slave_cap()
1100 for (port = 0; port < dev->caps.num_ports; port++) { in mlx4_change_port_types()
1103 if (port_types[port] != dev->caps.port_type[port + 1]) in mlx4_change_port_types()
1108 for (port = 1; port <= dev->caps.num_ports; port++) { in mlx4_change_port_types()
1110 dev->caps.port_type[port] = port_types[port - 1]; in mlx4_change_port_types()
1111 err = mlx4_SET_PORT(dev, port, -1); in mlx4_change_port_types()
1136 struct mlx4_dev *mdev = info->dev; in show_port_type()
1140 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? in show_port_type()
1142 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) in show_port_type()
1153 struct mlx4_dev *mdev = info->dev; in __set_port_type()
1160 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) { in __set_port_type()
1163 info->port); in __set_port_type()
1164 return -EOPNOTSUPP; in __set_port_type()
1168 mutex_lock(&priv->port_mutex); in __set_port_type()
1169 info->tmp_type = port_type; in __set_port_type()
1172 mdev->caps.possible_type[info->port] = info->tmp_type; in __set_port_type()
1174 for (i = 0; i < mdev->caps.num_ports; i++) { in __set_port_type()
1175 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : in __set_port_type()
1176 mdev->caps.possible_type[i+1]; in __set_port_type()
1178 types[i] = mdev->caps.port_type[i+1]; in __set_port_type()
1181 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && in __set_port_type()
1182 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { in __set_port_type()
1183 for (i = 1; i <= mdev->caps.num_ports; i++) { in __set_port_type()
1184 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { in __set_port_type()
1185 mdev->caps.possible_type[i] = mdev->caps.port_type[i]; in __set_port_type()
1186 err = -EOPNOTSUPP; in __set_port_type()
1204 for (i = 0; i < mdev->caps.num_ports; i++) in __set_port_type()
1205 priv->port[i + 1].tmp_type = 0; in __set_port_type()
1211 mutex_unlock(&priv->port_mutex); in __set_port_type()
1222 struct mlx4_dev *mdev = info->dev; in set_port_type()
1237 err = -EINVAL; in set_port_type()
1265 default: return -1; in int_to_ibta_mtu()
1277 default: return -1; in ibta_mtu_to_int()
1287 struct mlx4_dev *mdev = info->dev; in show_port_ib_mtu()
1289 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) in show_port_ib_mtu()
1293 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); in show_port_ib_mtu()
1303 struct mlx4_dev *mdev = info->dev; in set_port_ib_mtu()
1305 int err, port, mtu, ibta_mtu = -1; in set_port_ib_mtu()
1307 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { in set_port_ib_mtu()
1309 return -EINVAL; in set_port_ib_mtu()
1318 return -EINVAL; in set_port_ib_mtu()
1321 mdev->caps.port_ib_mtu[info->port] = ibta_mtu; in set_port_ib_mtu()
1324 mutex_lock(&priv->port_mutex); in set_port_ib_mtu()
1326 for (port = 1; port <= mdev->caps.num_ports; port++) { in set_port_ib_mtu()
1328 err = mlx4_SET_PORT(mdev, port, -1); in set_port_ib_mtu()
1337 mutex_unlock(&priv->port_mutex); in set_port_ib_mtu()
1342 /* bond for multi-function device */
1356 dev->persist->num_vfs + 1) > 1) { in mlx4_mf_bond()
1357 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n"); in mlx4_mf_bond()
1358 return -EINVAL; in mlx4_mf_bond()
1364 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) + in mlx4_mf_bond()
1365 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2; in mlx4_mf_bond()
1371 return -EINVAL; in mlx4_mf_bond()
1374 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { in mlx4_mf_bond()
1376 return -EINVAL; in mlx4_mf_bond()
1422 mutex_lock(&priv->bond_mutex); in mlx4_bond()
1437 mutex_unlock(&priv->bond_mutex); in mlx4_bond()
1449 mutex_lock(&priv->bond_mutex); in mlx4_unbond()
1465 mutex_unlock(&priv->bond_mutex); in mlx4_unbond()
1474 u8 port1 = v2p->port1; in mlx4_port_map_set()
1475 u8 port2 = v2p->port2; in mlx4_port_map_set()
1479 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP)) in mlx4_port_map_set()
1480 return -EOPNOTSUPP; in mlx4_port_map_set()
1482 mutex_lock(&priv->bond_mutex); in mlx4_port_map_set()
1486 port1 = priv->v2p.port1; in mlx4_port_map_set()
1488 port2 = priv->v2p.port2; in mlx4_port_map_set()
1495 err = -EINVAL; in mlx4_port_map_set()
1496 } else if ((port1 == priv->v2p.port1) && in mlx4_port_map_set()
1497 (port2 == priv->v2p.port2)) { in mlx4_port_map_set()
1504 priv->v2p.port1 = port1; in mlx4_port_map_set()
1505 priv->v2p.port2 = port2; in mlx4_port_map_set()
1511 mutex_unlock(&priv->bond_mutex); in mlx4_port_map_set()
1527 if (bond->is_bonded) { in mlx4_bond_work()
1528 if (!mlx4_is_bonded(bond->dev)) { in mlx4_bond_work()
1529 err = mlx4_bond(bond->dev); in mlx4_bond_work()
1531 mlx4_err(bond->dev, "Fail to bond device\n"); in mlx4_bond_work()
1534 err = mlx4_port_map_set(bond->dev, &bond->port_map); in mlx4_bond_work()
1536 mlx4_err(bond->dev, in mlx4_bond_work()
1538 bond->port_map.port1, in mlx4_bond_work()
1539 bond->port_map.port2, err); in mlx4_bond_work()
1541 } else if (mlx4_is_bonded(bond->dev)) { in mlx4_bond_work()
1542 err = mlx4_unbond(bond->dev); in mlx4_bond_work()
1544 mlx4_err(bond->dev, "Fail to unbond device\n"); in mlx4_bond_work()
1546 put_device(&bond->dev->persist->pdev->dev); in mlx4_bond_work()
1557 return -ENOMEM; in mlx4_queue_bond_work()
1559 INIT_WORK(&bond->work, mlx4_bond_work); in mlx4_queue_bond_work()
1560 get_device(&dev->persist->pdev->dev); in mlx4_queue_bond_work()
1561 bond->dev = dev; in mlx4_queue_bond_work()
1562 bond->is_bonded = is_bonded; in mlx4_queue_bond_work()
1563 bond->port_map.port1 = v2p_p1; in mlx4_queue_bond_work()
1564 bond->port_map.port2 = v2p_p2; in mlx4_queue_bond_work()
1565 queue_work(mlx4_wq, &bond->work); in mlx4_queue_bond_work()
1575 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, in mlx4_load_fw()
1577 if (!priv->fw.fw_icm) { in mlx4_load_fw()
1579 return -ENOMEM; in mlx4_load_fw()
1582 err = mlx4_MAP_FA(dev, priv->fw.fw_icm); in mlx4_load_fw()
1600 mlx4_free_icm(dev, priv->fw.fw_icm, 0); in mlx4_load_fw()
1611 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, in mlx4_init_cmpt_table()
1615 cmpt_entry_sz, dev->caps.num_qps, in mlx4_init_cmpt_table()
1616 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_cmpt_table()
1621 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, in mlx4_init_cmpt_table()
1625 cmpt_entry_sz, dev->caps.num_srqs, in mlx4_init_cmpt_table()
1626 dev->caps.reserved_srqs, 0, 0); in mlx4_init_cmpt_table()
1630 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, in mlx4_init_cmpt_table()
1634 cmpt_entry_sz, dev->caps.num_cqs, in mlx4_init_cmpt_table()
1635 dev->caps.reserved_cqs, 0, 0); in mlx4_init_cmpt_table()
1639 num_eqs = dev->phys_caps.num_phys_eqs; in mlx4_init_cmpt_table()
1640 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, in mlx4_init_cmpt_table()
1651 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); in mlx4_init_cmpt_table()
1654 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); in mlx4_init_cmpt_table()
1657 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); in mlx4_init_cmpt_table()
1681 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, in mlx4_init_icm()
1683 if (!priv->fw.aux_icm) { in mlx4_init_icm()
1685 return -ENOMEM; in mlx4_init_icm()
1688 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); in mlx4_init_icm()
1694 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); in mlx4_init_icm()
1701 num_eqs = dev->phys_caps.num_phys_eqs; in mlx4_init_icm()
1702 err = mlx4_init_icm_table(dev, &priv->eq_table.table, in mlx4_init_icm()
1703 init_hca->eqc_base, dev_cap->eqc_entry_sz, in mlx4_init_icm()
1714 * dev->caps.mtt_entry_sz below is really the MTT segment in mlx4_init_icm()
1717 dev->caps.reserved_mtts = in mlx4_init_icm()
1718 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, in mlx4_init_icm()
1719 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; in mlx4_init_icm()
1721 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, in mlx4_init_icm()
1722 init_hca->mtt_base, in mlx4_init_icm()
1723 dev->caps.mtt_entry_sz, in mlx4_init_icm()
1724 dev->caps.num_mtts, in mlx4_init_icm()
1725 dev->caps.reserved_mtts, 1, 0); in mlx4_init_icm()
1731 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, in mlx4_init_icm()
1732 init_hca->dmpt_base, in mlx4_init_icm()
1733 dev_cap->dmpt_entry_sz, in mlx4_init_icm()
1734 dev->caps.num_mpts, in mlx4_init_icm()
1735 dev->caps.reserved_mrws, 1, 1); in mlx4_init_icm()
1741 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, in mlx4_init_icm()
1742 init_hca->qpc_base, in mlx4_init_icm()
1743 dev_cap->qpc_entry_sz, in mlx4_init_icm()
1744 dev->caps.num_qps, in mlx4_init_icm()
1745 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_icm()
1752 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, in mlx4_init_icm()
1753 init_hca->auxc_base, in mlx4_init_icm()
1754 dev_cap->aux_entry_sz, in mlx4_init_icm()
1755 dev->caps.num_qps, in mlx4_init_icm()
1756 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_icm()
1763 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, in mlx4_init_icm()
1764 init_hca->altc_base, in mlx4_init_icm()
1765 dev_cap->altc_entry_sz, in mlx4_init_icm()
1766 dev->caps.num_qps, in mlx4_init_icm()
1767 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_icm()
1774 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, in mlx4_init_icm()
1775 init_hca->rdmarc_base, in mlx4_init_icm()
1776 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, in mlx4_init_icm()
1777 dev->caps.num_qps, in mlx4_init_icm()
1778 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], in mlx4_init_icm()
1785 err = mlx4_init_icm_table(dev, &priv->cq_table.table, in mlx4_init_icm()
1786 init_hca->cqc_base, in mlx4_init_icm()
1787 dev_cap->cqc_entry_sz, in mlx4_init_icm()
1788 dev->caps.num_cqs, in mlx4_init_icm()
1789 dev->caps.reserved_cqs, 0, 0); in mlx4_init_icm()
1795 err = mlx4_init_icm_table(dev, &priv->srq_table.table, in mlx4_init_icm()
1796 init_hca->srqc_base, in mlx4_init_icm()
1797 dev_cap->srq_entry_sz, in mlx4_init_icm()
1798 dev->caps.num_srqs, in mlx4_init_icm()
1799 dev->caps.reserved_srqs, 0, 0); in mlx4_init_icm()
1812 err = mlx4_init_icm_table(dev, &priv->mcg_table.table, in mlx4_init_icm()
1813 init_hca->mc_base, in mlx4_init_icm()
1815 dev->caps.num_mgms + dev->caps.num_amgms, in mlx4_init_icm()
1816 dev->caps.num_mgms + dev->caps.num_amgms, in mlx4_init_icm()
1826 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); in mlx4_init_icm()
1829 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); in mlx4_init_icm()
1832 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); in mlx4_init_icm()
1835 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); in mlx4_init_icm()
1838 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); in mlx4_init_icm()
1841 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); in mlx4_init_icm()
1844 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); in mlx4_init_icm()
1847 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); in mlx4_init_icm()
1850 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); in mlx4_init_icm()
1853 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); in mlx4_init_icm()
1854 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); in mlx4_init_icm()
1855 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); in mlx4_init_icm()
1856 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); in mlx4_init_icm()
1862 mlx4_free_icm(dev, priv->fw.aux_icm, 0); in mlx4_init_icm()
1871 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); in mlx4_free_icms()
1872 mlx4_cleanup_icm_table(dev, &priv->srq_table.table); in mlx4_free_icms()
1873 mlx4_cleanup_icm_table(dev, &priv->cq_table.table); in mlx4_free_icms()
1874 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); in mlx4_free_icms()
1875 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); in mlx4_free_icms()
1876 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); in mlx4_free_icms()
1877 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); in mlx4_free_icms()
1878 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); in mlx4_free_icms()
1879 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); in mlx4_free_icms()
1880 mlx4_cleanup_icm_table(dev, &priv->eq_table.table); in mlx4_free_icms()
1881 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); in mlx4_free_icms()
1882 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); in mlx4_free_icms()
1883 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); in mlx4_free_icms()
1884 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); in mlx4_free_icms()
1887 mlx4_free_icm(dev, priv->fw.aux_icm, 0); in mlx4_free_icms()
1894 mutex_lock(&priv->cmd.slave_cmd_mutex); in mlx4_slave_exit()
1898 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_slave_exit()
1908 if (!dev->caps.bf_reg_size) in map_bf_area()
1909 return -ENXIO; in map_bf_area()
1911 bf_start = pci_resource_start(dev->persist->pdev, 2) + in map_bf_area()
1912 (dev->caps.num_uars << PAGE_SHIFT); in map_bf_area()
1913 bf_len = pci_resource_len(dev->persist->pdev, 2) - in map_bf_area()
1914 (dev->caps.num_uars << PAGE_SHIFT); in map_bf_area()
1915 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); in map_bf_area()
1916 if (!priv->bf_mapping) in map_bf_area()
1917 err = -ENOMEM; in map_bf_area()
1924 if (mlx4_priv(dev)->bf_mapping) in unmap_bf_area()
1925 io_mapping_free(mlx4_priv(dev)->bf_mapping); in unmap_bf_area()
1936 clockhi = swab32(readl(priv->clock_mapping)); in mlx4_read_clock()
1937 clocklo = swab32(readl(priv->clock_mapping + 4)); in mlx4_read_clock()
1938 clockhi1 = swab32(readl(priv->clock_mapping)); in mlx4_read_clock()
1954 priv->clock_mapping = in map_internal_clock()
1955 ioremap(pci_resource_start(dev->persist->pdev, in map_internal_clock()
1956 priv->fw.clock_bar) + in map_internal_clock()
1957 priv->fw.clock_offset, MLX4_CLOCK_SIZE); in map_internal_clock()
1959 if (!priv->clock_mapping) in map_internal_clock()
1960 return -ENOMEM; in map_internal_clock()
1971 return -EOPNOTSUPP; in mlx4_get_internal_clock_params()
1973 if (!dev->caps.map_clock_to_user) { in mlx4_get_internal_clock_params()
1975 return -EOPNOTSUPP; in mlx4_get_internal_clock_params()
1979 return -EINVAL; in mlx4_get_internal_clock_params()
1981 params->bar = priv->fw.clock_bar; in mlx4_get_internal_clock_params()
1982 params->offset = priv->fw.clock_offset; in mlx4_get_internal_clock_params()
1983 params->size = MLX4_CLOCK_SIZE; in mlx4_get_internal_clock_params()
1993 if (priv->clock_mapping) in unmap_internal_clock()
1994 iounmap(priv->clock_mapping); in unmap_internal_clock()
2013 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); in mlx4_close_fw()
2028 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm + in mlx4_comm_check_offline()
2038 if (dev->persist->interface_state & in mlx4_comm_check_offline()
2050 return -EIO; in mlx4_comm_check_offline()
2061 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm + in mlx4_reset_vf_support()
2066 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET; in mlx4_reset_vf_support()
2072 u64 dma = (u64) priv->mfunc.vhcr_dma; in mlx4_init_slave()
2078 mlx4_warn(dev, "PF is not ready - Deferring probe\n"); in mlx4_init_slave()
2079 return -EPROBE_DEFER; in mlx4_init_slave()
2082 mutex_lock(&priv->cmd.slave_cmd_mutex); in mlx4_init_slave()
2083 priv->cmd.max_cmds = 1; in mlx4_init_slave()
2097 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); in mlx4_init_slave()
2098 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_init_slave()
2099 return -EPROBE_DEFER; in mlx4_init_slave()
2104 /* check the driver version - the slave I/F revision in mlx4_init_slave()
2106 slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); in mlx4_init_slave()
2129 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_init_slave()
2135 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_init_slave()
2136 return -EIO; in mlx4_init_slave()
2143 for (i = 1; i <= dev->caps.num_ports; i++) { in mlx4_parav_master_pf_caps()
2144 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) in mlx4_parav_master_pf_caps()
2145 dev->caps.gid_table_len[i] = in mlx4_parav_master_pf_caps()
2148 dev->caps.gid_table_len[i] = 1; in mlx4_parav_master_pf_caps()
2149 dev->caps.pkey_table_len[i] = in mlx4_parav_master_pf_caps()
2150 dev->phys_caps.pkey_phys_table_len[i] - 1; in mlx4_parav_master_pf_caps()
2160 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) in choose_log_fs_mgm_entry_size()
2164 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; in choose_log_fs_mgm_entry_size()
2196 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) { in choose_steering_mode()
2197 if (dev->caps.dmfs_high_steer_mode == in choose_steering_mode()
2201 dev->caps.dmfs_high_steer_mode = in choose_steering_mode()
2207 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && in choose_steering_mode()
2209 (dev_cap->fs_max_num_qp_per_entry >= in choose_steering_mode()
2210 (dev->persist->num_vfs + 1))) && in choose_steering_mode()
2211 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= in choose_steering_mode()
2213 dev->oper_log_mgm_entry_size = in choose_steering_mode()
2214 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); in choose_steering_mode()
2215 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; in choose_steering_mode()
2216 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; in choose_steering_mode()
2217 dev->caps.fs_log_max_ucast_qp_range_size = in choose_steering_mode()
2218 dev_cap->fs_log_max_ucast_qp_range_size; in choose_steering_mode()
2220 if (dev->caps.dmfs_high_steer_mode != in choose_steering_mode()
2222 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE; in choose_steering_mode()
2223 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && in choose_steering_mode()
2224 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) in choose_steering_mode()
2225 dev->caps.steering_mode = MLX4_STEERING_MODE_B0; in choose_steering_mode()
2227 dev->caps.steering_mode = MLX4_STEERING_MODE_A0; in choose_steering_mode()
2229 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || in choose_steering_mode()
2230 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) in choose_steering_mode()
2231 …mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back t… in choose_steering_mode()
2233 dev->oper_log_mgm_entry_size = in choose_steering_mode()
2237 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); in choose_steering_mode()
2240 mlx4_steering_mode_str(dev->caps.steering_mode), in choose_steering_mode()
2241 dev->oper_log_mgm_entry_size, in choose_steering_mode()
2248 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && in choose_tunnel_offload_mode()
2249 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) in choose_tunnel_offload_mode()
2250 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; in choose_tunnel_offload_mode()
2252 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; in choose_tunnel_offload_mode()
2254 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode in choose_tunnel_offload_mode()
2263 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) in mlx4_validate_optimized_steering()
2264 return -EINVAL; in mlx4_validate_optimized_steering()
2266 for (i = 1; i <= dev->caps.num_ports; i++) { in mlx4_validate_optimized_steering()
2270 } else if ((dev->caps.dmfs_high_steer_mode != in mlx4_validate_optimized_steering()
2273 !!(dev->caps.dmfs_high_steer_mode == in mlx4_validate_optimized_steering()
2278 dev->caps.dmfs_high_steer_mode), in mlx4_validate_optimized_steering()
2295 if (err == -EACCES) in mlx4_init_fw()
2296 mlx4_info(dev, "non-primary physical function, skipping\n"); in mlx4_init_fw()
2334 err = -ENOMEM; in mlx4_init_hca()
2347 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC && in mlx4_init_hca()
2349 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC; in mlx4_init_hca()
2364 if (dev->caps.steering_mode == in mlx4_init_hca()
2375 if (enable_4k_uar || !dev->persist->num_vfs) { in mlx4_init_hca()
2376 init_hca->log_uar_sz = ilog2(dev->caps.num_uars) + in mlx4_init_hca()
2377 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT; in mlx4_init_hca()
2378 init_hca->uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12; in mlx4_init_hca()
2380 init_hca->log_uar_sz = ilog2(dev->caps.num_uars); in mlx4_init_hca()
2381 init_hca->uar_page_sz = PAGE_SHIFT - 12; in mlx4_init_hca()
2384 init_hca->mw_enabled = 0; in mlx4_init_hca()
2385 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || in mlx4_init_hca()
2386 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) in mlx4_init_hca()
2387 init_hca->mw_enabled = INIT_HCA_TPT_MW_ENABLE; in mlx4_init_hca()
2399 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { in mlx4_init_hca()
2405 dev->caps.num_eqs = dev_cap->max_eqs; in mlx4_init_hca()
2406 dev->caps.reserved_eqs = dev_cap->reserved_eqs; in mlx4_init_hca()
2407 dev->caps.reserved_uars = dev_cap->reserved_uars; in mlx4_init_hca()
2415 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { in mlx4_init_hca()
2419 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; in mlx4_init_hca()
2421 dev->caps.hca_core_clock = in mlx4_init_hca()
2422 init_hca->hca_core_clock; in mlx4_init_hca()
2425 /* In case we got HCA frequency 0 - disable timestamping in mlx4_init_hca()
2428 if (!dev->caps.hca_core_clock) { in mlx4_init_hca()
2429 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; in mlx4_init_hca()
2431 "HCA frequency is 0 - timestamping is not supported\n"); in mlx4_init_hca()
2437 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; in mlx4_init_hca()
2442 if (dev->caps.dmfs_high_steer_mode != in mlx4_init_hca()
2447 if (dev->caps.dmfs_high_steer_mode == in mlx4_init_hca()
2449 dev->caps.dmfs_high_rate_qpn_base = in mlx4_init_hca()
2450 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]; in mlx4_init_hca()
2451 dev->caps.dmfs_high_rate_qpn_range = in mlx4_init_hca()
2457 dev->caps.dmfs_high_steer_mode)); in mlx4_init_hca()
2462 if (err != -EPROBE_DEFER) in mlx4_init_hca()
2489 if (err && err != -EOPNOTSUPP) { in mlx4_init_hca()
2492 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1; in mlx4_init_hca()
2493 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2; in mlx4_init_hca()
2495 priv->eq_table.inta_pin = adapter.inta_pin; in mlx4_init_hca()
2496 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id)); in mlx4_init_hca()
2530 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) in mlx4_init_counters_table()
2531 return -ENOENT; in mlx4_init_counters_table()
2533 if (!dev->caps.max_counters) in mlx4_init_counters_table()
2534 return -ENOSPC; in mlx4_init_counters_table()
2536 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters); in mlx4_init_counters_table()
2538 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2, in mlx4_init_counters_table()
2539 nent_pow2 - 1, 0, in mlx4_init_counters_table()
2540 nent_pow2 - dev->caps.max_counters + 1); in mlx4_init_counters_table()
2545 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) in mlx4_cleanup_counters_table()
2548 if (!dev->caps.max_counters) in mlx4_cleanup_counters_table()
2551 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); in mlx4_cleanup_counters_table()
2559 for (port = 0; port < dev->caps.num_ports; port++) in mlx4_cleanup_default_counters()
2560 if (priv->def_counter[port] != -1) in mlx4_cleanup_default_counters()
2561 mlx4_counter_free(dev, priv->def_counter[port]); in mlx4_cleanup_default_counters()
2570 for (port = 0; port < dev->caps.num_ports; port++) in mlx4_allocate_default_counters()
2571 priv->def_counter[port] = -1; in mlx4_allocate_default_counters()
2573 for (port = 0; port < dev->caps.num_ports; port++) { in mlx4_allocate_default_counters()
2576 if (!err || err == -ENOSPC) { in mlx4_allocate_default_counters()
2577 priv->def_counter[port] = idx; in mlx4_allocate_default_counters()
2579 } else if (err == -ENOENT) { in mlx4_allocate_default_counters()
2582 } else if (mlx4_is_slave(dev) && err == -EINVAL) { in mlx4_allocate_default_counters()
2583 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev); in mlx4_allocate_default_counters()
2595 __func__, priv->def_counter[port], port + 1); in mlx4_allocate_default_counters()
2605 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) in __mlx4_counter_alloc()
2606 return -ENOENT; in __mlx4_counter_alloc()
2608 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); in __mlx4_counter_alloc()
2609 if (*idx == -1) { in __mlx4_counter_alloc()
2611 return -ENOSPC; in __mlx4_counter_alloc()
2629 if (WARN_ON(err == -ENOSPC)) in mlx4_counter_alloc()
2630 err = -EINVAL; in mlx4_counter_alloc()
2648 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0, in __mlx4_clear_if_stat()
2658 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) in __mlx4_counter_free()
2666 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); in __mlx4_counter_free()
2689 return priv->def_counter[port - 1]; in mlx4_get_default_counter_index()
2697 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; in mlx4_set_admin_guid()
2705 return priv->mfunc.master.vf_admin[entry].vport[port].guid; in mlx4_get_admin_guid()
2721 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid; in mlx4_set_random_admin_guid()
2737 err = mlx4_uar_alloc(dev, &priv->driver_uar); in mlx4_setup_hca()
2743 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); in mlx4_setup_hca()
2744 if (!priv->kar) { in mlx4_setup_hca()
2746 err = -ENOMEM; in mlx4_setup_hca()
2789 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); in mlx4_setup_hca()
2795 if (dev->flags & MLX4_FLAG_MSI_X) { in mlx4_setup_hca()
2796 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", in mlx4_setup_hca()
2797 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); in mlx4_setup_hca()
2798 mlx4_warn(dev, "Trying again without MSI-X\n"); in mlx4_setup_hca()
2801 priv->eq_table.eq[MLX4_EQ_ASYNC].irq); in mlx4_setup_hca()
2830 if (err && err != -ENOENT) { in mlx4_setup_hca()
2843 for (port = 1; port <= dev->caps.num_ports; port++) { in mlx4_setup_hca()
2850 dev->caps.ib_port_def_cap[port] = ib_port_default_caps; in mlx4_setup_hca()
2852 /* initialize per-slave default ib port capabilities */ in mlx4_setup_hca()
2855 for (i = 0; i < dev->num_slaves; i++) { in mlx4_setup_hca()
2858 priv->mfunc.master.slave_state[i].ib_cap_mask[port] = in mlx4_setup_hca()
2864 dev->caps.port_ib_mtu[port] = IB_MTU_2048; in mlx4_setup_hca()
2866 dev->caps.port_ib_mtu[port] = IB_MTU_4096; in mlx4_setup_hca()
2869 dev->caps.pkey_table_len[port] : -1); in mlx4_setup_hca()
2916 iounmap(priv->kar); in mlx4_setup_hca()
2919 mlx4_uar_free(dev, &priv->driver_uar); in mlx4_setup_hca()
2934 if (eqn > dev->caps.num_comp_vectors) in mlx4_init_affinity_hint()
2935 return -EINVAL; in mlx4_init_affinity_hint()
2940 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC); in mlx4_init_affinity_hint()
2946 eq = &priv->eq_table.eq[eqn]; in mlx4_init_affinity_hint()
2948 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL)) in mlx4_init_affinity_hint()
2949 return -ENOMEM; in mlx4_init_affinity_hint()
2951 cpumask_set_cpu(requested_cpu, eq->affinity_mask); in mlx4_init_affinity_hint()
2964 int nreq = min3(dev->caps.num_ports * in mlx4_enable_msi_x()
2966 dev->caps.num_eqs - dev->caps.reserved_eqs, in mlx4_enable_msi_x()
2979 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2, in mlx4_enable_msi_x()
2987 dev->caps.num_comp_vectors = nreq - 1; in mlx4_enable_msi_x()
2989 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector; in mlx4_enable_msi_x()
2990 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports, in mlx4_enable_msi_x()
2991 dev->caps.num_ports); in mlx4_enable_msi_x()
2993 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) { in mlx4_enable_msi_x()
2997 priv->eq_table.eq[i].irq = in mlx4_enable_msi_x()
2998 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector; in mlx4_enable_msi_x()
3000 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) { in mlx4_enable_msi_x()
3001 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, in mlx4_enable_msi_x()
3002 dev->caps.num_ports); in mlx4_enable_msi_x()
3008 priv->eq_table.eq[i].actv_ports.ports); in mlx4_enable_msi_x()
3014 * (dev->caps.num_comp_vectors / dev->caps.num_ports) in mlx4_enable_msi_x()
3022 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) && in mlx4_enable_msi_x()
3024 (dev->caps.num_comp_vectors / dev->caps.num_ports)) == in mlx4_enable_msi_x()
3026 /* If dev->caps.num_comp_vectors < dev->caps.num_ports, in mlx4_enable_msi_x()
3032 dev->flags |= MLX4_FLAG_MSI_X; in mlx4_enable_msi_x()
3039 dev->caps.num_comp_vectors = 1; in mlx4_enable_msi_x()
3043 priv->eq_table.eq[i].irq = dev->persist->pdev->irq; in mlx4_enable_msi_x()
3045 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports, in mlx4_enable_msi_x()
3046 dev->caps.num_ports); in mlx4_enable_msi_x()
3070 return -EOPNOTSUPP; in mlx4_devlink_port_type_set()
3083 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; in mlx4_init_port_info()
3086 err = devl_port_register_with_ops(devlink, &info->devlink_port, port, in mlx4_init_port_info()
3096 dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) in mlx4_init_port_info()
3097 devlink_port_type_eth_set(&info->devlink_port); in mlx4_init_port_info()
3099 dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) in mlx4_init_port_info()
3100 devlink_port_type_ib_set(&info->devlink_port, NULL); in mlx4_init_port_info()
3102 info->dev = dev; in mlx4_init_port_info()
3103 info->port = port; in mlx4_init_port_info()
3105 mlx4_init_mac_table(dev, &info->mac_table); in mlx4_init_port_info()
3106 mlx4_init_vlan_table(dev, &info->vlan_table); in mlx4_init_port_info()
3107 mlx4_init_roce_gid_table(dev, &info->gid_table); in mlx4_init_port_info()
3108 info->base_qpn = mlx4_get_base_qpn(dev, port); in mlx4_init_port_info()
3111 sprintf(info->dev_name, "mlx4_port%d", port); in mlx4_init_port_info()
3112 info->port_attr.attr.name = info->dev_name; in mlx4_init_port_info()
3114 info->port_attr.attr.mode = 0444; in mlx4_init_port_info()
3116 info->port_attr.attr.mode = 0644; in mlx4_init_port_info()
3117 info->port_attr.store = set_port_type; in mlx4_init_port_info()
3119 info->port_attr.show = show_port_type; in mlx4_init_port_info()
3120 sysfs_attr_init(&info->port_attr.attr); in mlx4_init_port_info()
3122 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr); in mlx4_init_port_info()
3125 devlink_port_type_clear(&info->devlink_port); in mlx4_init_port_info()
3126 devl_port_unregister(&info->devlink_port); in mlx4_init_port_info()
3127 info->port = -1; in mlx4_init_port_info()
3131 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); in mlx4_init_port_info()
3132 info->port_mtu_attr.attr.name = info->dev_mtu_name; in mlx4_init_port_info()
3134 info->port_mtu_attr.attr.mode = 0444; in mlx4_init_port_info()
3136 info->port_mtu_attr.attr.mode = 0644; in mlx4_init_port_info()
3137 info->port_mtu_attr.store = set_port_ib_mtu; in mlx4_init_port_info()
3139 info->port_mtu_attr.show = show_port_ib_mtu; in mlx4_init_port_info()
3140 sysfs_attr_init(&info->port_mtu_attr.attr); in mlx4_init_port_info()
3142 err = device_create_file(&dev->persist->pdev->dev, in mlx4_init_port_info()
3143 &info->port_mtu_attr); in mlx4_init_port_info()
3146 device_remove_file(&info->dev->persist->pdev->dev, in mlx4_init_port_info()
3147 &info->port_attr); in mlx4_init_port_info()
3148 devlink_port_type_clear(&info->devlink_port); in mlx4_init_port_info()
3149 devl_port_unregister(&info->devlink_port); in mlx4_init_port_info()
3150 info->port = -1; in mlx4_init_port_info()
3159 if (info->port < 0) in mlx4_cleanup_port_info()
3162 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr); in mlx4_cleanup_port_info()
3163 device_remove_file(&info->dev->persist->pdev->dev, in mlx4_cleanup_port_info()
3164 &info->port_mtu_attr); in mlx4_cleanup_port_info()
3165 devlink_port_type_clear(&info->devlink_port); in mlx4_cleanup_port_info()
3166 devl_port_unregister(&info->devlink_port); in mlx4_cleanup_port_info()
3169 free_irq_cpu_rmap(info->rmap); in mlx4_cleanup_port_info()
3170 info->rmap = NULL; in mlx4_cleanup_port_info()
3177 int num_entries = dev->caps.num_ports; in mlx4_init_steering()
3180 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer), in mlx4_init_steering()
3182 if (!priv->steer) in mlx4_init_steering()
3183 return -ENOMEM; in mlx4_init_steering()
3187 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); in mlx4_init_steering()
3188 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); in mlx4_init_steering()
3198 int num_entries = dev->caps.num_ports; in mlx4_clear_steering()
3204 &priv->steer[i].promisc_qps[j], in mlx4_clear_steering()
3206 list_del(&pqp->list); in mlx4_clear_steering()
3210 &priv->steer[i].steer_entries[j], in mlx4_clear_steering()
3212 list_del(&entry->list); in mlx4_clear_steering()
3214 &entry->duplicates, in mlx4_clear_steering()
3216 list_del(&pqp->list); in mlx4_clear_steering()
3223 kfree(priv->steer); in mlx4_clear_steering()
3228 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); in extended_func_num()
3239 if (pci_channel_offline(dev->persist->pdev)) in mlx4_get_ownership()
3240 return -EIO; in mlx4_get_ownership()
3242 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + in mlx4_get_ownership()
3247 return -ENOMEM; in mlx4_get_ownership()
3259 if (pci_channel_offline(dev->persist->pdev)) in mlx4_free_ownership()
3262 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) + in mlx4_free_ownership()
3280 u64 dev_flags = dev->flags; in mlx4_enable_sriov()
3286 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), in mlx4_enable_sriov()
3288 if (!dev->dev_vfs) in mlx4_enable_sriov()
3294 if (dev->flags & MLX4_FLAG_SRIOV) { in mlx4_enable_sriov()
3296 … mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n", in mlx4_enable_sriov()
3302 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL); in mlx4_enable_sriov()
3303 if (NULL == dev->dev_vfs) { in mlx4_enable_sriov()
3308 if (!(dev->flags & MLX4_FLAG_SRIOV)) { in mlx4_enable_sriov()
3312 err = -ENOMEM; in mlx4_enable_sriov()
3315 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs); in mlx4_enable_sriov()
3319 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", in mlx4_enable_sriov()
3327 dev->persist->num_vfs = total_vfs; in mlx4_enable_sriov()
3334 dev->persist->num_vfs = 0; in mlx4_enable_sriov()
3335 kfree(dev->dev_vfs); in mlx4_enable_sriov()
3336 dev->dev_vfs = NULL; in mlx4_enable_sriov()
3341 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3349 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) && in mlx4_check_dev_cap()
3360 struct pci_dev *pdev = dev->persist->pdev; in mlx4_pci_enable_device()
3363 mutex_lock(&dev->persist->pci_status_mutex); in mlx4_pci_enable_device()
3364 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) { in mlx4_pci_enable_device()
3367 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED; in mlx4_pci_enable_device()
3369 mutex_unlock(&dev->persist->pci_status_mutex); in mlx4_pci_enable_device()
3376 struct pci_dev *pdev = dev->persist->pdev; in mlx4_pci_disable_device()
3378 mutex_lock(&dev->persist->pci_status_mutex); in mlx4_pci_disable_device()
3379 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) { in mlx4_pci_disable_device()
3381 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED; in mlx4_pci_disable_device()
3383 mutex_unlock(&dev->persist->pci_status_mutex); in mlx4_pci_disable_device()
3400 dev = &priv->dev; in mlx4_load_one()
3406 ATOMIC_INIT_NOTIFIER_HEAD(&priv->event_nh); in mlx4_load_one()
3408 mutex_init(&priv->port_mutex); in mlx4_load_one()
3409 mutex_init(&priv->bond_mutex); in mlx4_load_one()
3411 INIT_LIST_HEAD(&priv->pgdir_list); in mlx4_load_one()
3412 mutex_init(&priv->pgdir_mutex); in mlx4_load_one()
3413 spin_lock_init(&priv->cmd.context_lock); in mlx4_load_one()
3415 INIT_LIST_HEAD(&priv->bf_list); in mlx4_load_one()
3416 mutex_init(&priv->bf_mutex); in mlx4_load_one()
3418 dev->rev_id = pdev->revision; in mlx4_load_one()
3419 dev->numa_node = dev_to_node(&pdev->dev); in mlx4_load_one()
3423 mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); in mlx4_load_one()
3424 dev->flags |= MLX4_FLAG_SLAVE; in mlx4_load_one()
3428 * if already taken, skip -- do not allow multiple PFs */ in mlx4_load_one()
3434 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); in mlx4_load_one()
3435 err = -EINVAL; in mlx4_load_one()
3440 atomic_set(&priv->opreq_count, 0); in mlx4_load_one()
3441 INIT_WORK(&priv->opreq_task, mlx4_opreq_action); in mlx4_load_one()
3455 dev->flags = MLX4_FLAG_MASTER; in mlx4_load_one()
3458 dev->flags |= MLX4_FLAG_SRIOV; in mlx4_load_one()
3459 dev->persist->num_vfs = total_vfs; in mlx4_load_one()
3466 dev->persist->state = MLX4_DEVICE_STATE_UP; in mlx4_load_one()
3480 dev->num_slaves = MLX4_MAX_NUM_SLAVES; in mlx4_load_one()
3483 dev->num_slaves = 0; in mlx4_load_one()
3504 err = -ENOMEM; in mlx4_load_one()
3517 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { in mlx4_load_one()
3525 dev->flags = dev_flags; in mlx4_load_one()
3526 if (!SRIOV_VALID_STATE(dev->flags)) { in mlx4_load_one()
3556 if (err == -EACCES) { in mlx4_load_one()
3561 if (dev->flags & MLX4_FLAG_SRIOV) { in mlx4_load_one()
3566 dev->flags &= ~MLX4_FLAG_SRIOV; in mlx4_load_one()
3570 dev->flags |= MLX4_FLAG_SLAVE; in mlx4_load_one()
3571 dev->flags &= ~MLX4_FLAG_MASTER; in mlx4_load_one()
3577 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) { in mlx4_load_one()
3581 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) { in mlx4_load_one()
3583 dev->flags = dev_flags; in mlx4_load_one()
3593 dev->flags = dev_flags; in mlx4_load_one()
3596 if (!SRIOV_VALID_STATE(dev->flags)) { in mlx4_load_one()
3598 err = -EINVAL; in mlx4_load_one()
3605 * express device capabilities are under-satisfied by the bus. in mlx4_load_one()
3608 pcie_print_link_status(dev->persist->pdev); in mlx4_load_one()
3613 if (dev->caps.num_ports < 2 && in mlx4_load_one()
3615 err = -EINVAL; in mlx4_load_one()
3618 dev->caps.num_ports); in mlx4_load_one()
3621 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs)); in mlx4_load_one()
3624 i < sizeof(dev->persist->nvfs)/ in mlx4_load_one()
3625 sizeof(dev->persist->nvfs[0]); i++) { in mlx4_load_one()
3628 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) { in mlx4_load_one()
3629 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1; in mlx4_load_one()
3630 dev->dev_vfs[sum].n_ports = i < 2 ? 1 : in mlx4_load_one()
3631 dev->caps.num_ports; in mlx4_load_one()
3649 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX); in mlx4_load_one()
3650 mutex_init(&priv->msix_ctl.pool_lock); in mlx4_load_one()
3654 !(dev->flags & MLX4_FLAG_MSI_X)) { in mlx4_load_one()
3655 err = -EOPNOTSUPP; in mlx4_load_one()
3656 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); in mlx4_load_one()
3669 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && in mlx4_load_one()
3671 dev->flags &= ~MLX4_FLAG_MSI_X; in mlx4_load_one()
3672 dev->caps.num_comp_vectors = 1; in mlx4_load_one()
3692 for (port = 1; port <= dev->caps.num_ports; port++) { in mlx4_load_one()
3698 priv->v2p.port1 = 1; in mlx4_load_one()
3699 priv->v2p.port2 = 2; in mlx4_load_one()
3708 priv->removed = 0; in mlx4_load_one()
3710 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) in mlx4_load_one()
3717 for (--port; port >= 1; --port) in mlx4_load_one()
3718 mlx4_cleanup_port_info(&priv->port[port]); in mlx4_load_one()
3739 if (dev->flags & MLX4_FLAG_MSI_X) in mlx4_load_one()
3768 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) { in mlx4_load_one()
3770 dev->flags &= ~MLX4_FLAG_SRIOV; in mlx4_load_one()
3773 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow) in mlx4_load_one()
3776 kfree(priv->dev.dev_vfs); in mlx4_load_one()
3801 err = mlx4_pci_enable_device(&priv->dev); in __mlx4_init_one()
3803 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in __mlx4_init_one()
3812 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { in __mlx4_init_one()
3813 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; in __mlx4_init_one()
3815 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); in __mlx4_init_one()
3816 err = -EINVAL; in __mlx4_init_one()
3822 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; in __mlx4_init_one()
3824 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); in __mlx4_init_one()
3825 err = -EINVAL; in __mlx4_init_one()
3830 dev_err(&pdev->dev, in __mlx4_init_one()
3833 err = -EINVAL; in __mlx4_init_one()
3839 dev_err(&pdev->dev, in __mlx4_init_one()
3843 err = -EINVAL; in __mlx4_init_one()
3851 …dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\… in __mlx4_init_one()
3853 err = -ENODEV; in __mlx4_init_one()
3857 dev_err(&pdev->dev, "Missing UAR, aborting\n"); in __mlx4_init_one()
3858 err = -ENODEV; in __mlx4_init_one()
3864 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); in __mlx4_init_one()
3870 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in __mlx4_init_one()
3872 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); in __mlx4_init_one()
3873 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in __mlx4_init_one()
3875 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); in __mlx4_init_one()
3881 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); in __mlx4_init_one()
3895 err = -ENODEV; in __mlx4_init_one()
3898 if ((extended_func_num(pdev) - vfs_offset) in __mlx4_init_one()
3900 dev_warn(&pdev->dev, "Skipping virtual function:%d\n", in __mlx4_init_one()
3902 err = -ENODEV; in __mlx4_init_one()
3908 err = mlx4_crdump_init(&priv->dev); in __mlx4_init_one()
3912 err = mlx4_catas_init(&priv->dev); in __mlx4_init_one()
3923 mlx4_catas_end(&priv->dev); in __mlx4_init_one()
3926 mlx4_crdump_end(&priv->dev); in __mlx4_init_one()
3932 mlx4_pci_disable_device(&priv->dev); in __mlx4_init_one()
3939 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_param_load_driverinit_values()
3940 struct mlx4_fw_crdump *crdump = &dev->persist->crdump; in mlx4_devlink_param_load_driverinit_values()
3971 if (!err && crdump->snapshot_enable != saved_value.vbool) { in mlx4_devlink_param_load_driverinit_values()
3972 crdump->snapshot_enable = saved_value.vbool; in mlx4_devlink_param_load_driverinit_values()
3988 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_reload_down()
3989 struct mlx4_dev_persistent *persist = dev->persist; in mlx4_devlink_reload_down()
3993 return -EOPNOTSUPP; in mlx4_devlink_reload_down()
3995 if (persist->num_vfs) in mlx4_devlink_reload_down()
3996 …mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n… in mlx4_devlink_reload_down()
3997 mlx4_restart_one_down(persist->pdev); in mlx4_devlink_reload_down()
4006 struct mlx4_dev *dev = &priv->dev; in mlx4_devlink_reload_up()
4007 struct mlx4_dev_persistent *persist = dev->persist; in mlx4_devlink_reload_up()
4011 err = mlx4_restart_one_up(persist->pdev, true, devlink); in mlx4_devlink_reload_up()
4013 mlx4_err(persist->dev, "mlx4_restart_one_up failed, ret=%d\n", in mlx4_devlink_reload_up()
4034 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv), &pdev->dev); in mlx4_init_one()
4036 return -ENOMEM; in mlx4_init_one()
4040 dev = &priv->dev; in mlx4_init_one()
4041 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL); in mlx4_init_one()
4042 if (!dev->persist) { in mlx4_init_one()
4043 ret = -ENOMEM; in mlx4_init_one()
4046 dev->persist->pdev = pdev; in mlx4_init_one()
4047 dev->persist->dev = dev; in mlx4_init_one()
4048 pci_set_drvdata(pdev, dev->persist); in mlx4_init_one()
4049 priv->pci_dev_data = id->driver_data; in mlx4_init_one()
4050 mutex_init(&dev->persist->device_state_mutex); in mlx4_init_one()
4051 mutex_init(&dev->persist->interface_state_mutex); in mlx4_init_one()
4052 mutex_init(&dev->persist->pci_status_mutex); in mlx4_init_one()
4059 ret = __mlx4_init_one(pdev, id->driver_data, priv); in mlx4_init_one()
4072 kfree(dev->persist); in mlx4_init_one()
4081 struct mlx4_dev_persistent *persist = dev->persist; in mlx4_clean_dev()
4083 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS); in mlx4_clean_dev()
4086 priv->dev.persist = persist; in mlx4_clean_dev()
4087 priv->dev.flags = flags; in mlx4_clean_dev()
4093 struct mlx4_dev *dev = persist->dev; in mlx4_unload_one()
4101 if (priv->removed) in mlx4_unload_one()
4105 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_unload_one()
4106 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1]; in mlx4_unload_one()
4107 dev->persist->curr_port_poss_type[i] = dev->caps. in mlx4_unload_one()
4111 pci_dev_data = priv->pci_dev_data; in mlx4_unload_one()
4116 for (p = 1; p <= dev->caps.num_ports; p++) { in mlx4_unload_one()
4117 mlx4_cleanup_port_info(&priv->port[p]); in mlx4_unload_one()
4142 iounmap(priv->kar); in mlx4_unload_one()
4143 mlx4_uar_free(dev, &priv->driver_uar); in mlx4_unload_one()
4156 if (dev->flags & MLX4_FLAG_MSI_X) in mlx4_unload_one()
4163 kfree(dev->dev_vfs); in mlx4_unload_one()
4168 priv->pci_dev_data = pci_dev_data; in mlx4_unload_one()
4169 priv->removed = 1; in mlx4_unload_one()
4175 struct mlx4_dev *dev = persist->dev; in mlx4_remove_one()
4184 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT; in mlx4_remove_one()
4186 mutex_lock(&persist->interface_state_mutex); in mlx4_remove_one()
4187 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION; in mlx4_remove_one()
4188 mutex_unlock(&persist->interface_state_mutex); in mlx4_remove_one()
4190 /* Disabling SR-IOV is not allowed while there are active vf's */ in mlx4_remove_one()
4191 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) { in mlx4_remove_one()
4195 pr_warn("Will not disable SR-IOV.\n"); in mlx4_remove_one()
4202 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) in mlx4_remove_one()
4208 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) { in mlx4_remove_one()
4209 mlx4_warn(dev, "Disabling SR-IOV\n"); in mlx4_remove_one()
4217 kfree(dev->persist); in mlx4_remove_one()
4231 mutex_lock(&priv->port_mutex); in restore_current_port_types()
4232 for (i = 0; i < dev->caps.num_ports; i++) in restore_current_port_types()
4233 dev->caps.possible_type[i + 1] = poss_types[i]; in restore_current_port_types()
4236 mutex_unlock(&priv->port_mutex); in restore_current_port_types()
4250 struct mlx4_dev *dev = persist->dev; in mlx4_restart_one_up()
4255 pci_dev_data = priv->pci_dev_data; in mlx4_restart_one_up()
4256 total_vfs = dev->persist->num_vfs; in mlx4_restart_one_up()
4257 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); in mlx4_restart_one_up()
4268 err = restore_current_port_types(dev, dev->persist->curr_port_type, in mlx4_restart_one_up()
4269 dev->persist->curr_port_poss_type); in mlx4_restart_one_up()
4297 /* MT25458 ConnectX EN 10GBASE-T */
4306 /* MT25400 Family [ConnectX-2] */
4309 /* MT27500 Family [ConnectX-3] */
4339 struct mlx4_dev *dev = persist->dev; in mlx4_pci_err_detected()
4342 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n"); in mlx4_pci_err_detected()
4347 mutex_lock(&persist->interface_state_mutex); in mlx4_pci_err_detected()
4348 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) in mlx4_pci_err_detected()
4351 mutex_unlock(&persist->interface_state_mutex); in mlx4_pci_err_detected()
4356 mlx4_pci_disable_device(persist->dev); in mlx4_pci_err_detected()
4363 struct mlx4_dev *dev = persist->dev; in mlx4_pci_slot_reset()
4369 mlx4_err(dev, "Can not re-enable device, err=%d\n", err); in mlx4_pci_slot_reset()
4382 struct mlx4_dev *dev = persist->dev; in mlx4_pci_resume()
4390 total_vfs = dev->persist->num_vfs; in mlx4_pci_resume()
4391 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); in mlx4_pci_resume()
4395 mutex_lock(&persist->interface_state_mutex); in mlx4_pci_resume()
4396 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { in mlx4_pci_resume()
4397 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs, in mlx4_pci_resume()
4405 err = restore_current_port_types(dev, dev->persist-> in mlx4_pci_resume()
4406 curr_port_type, dev->persist-> in mlx4_pci_resume()
4412 mutex_unlock(&persist->interface_state_mutex); in mlx4_pci_resume()
4419 struct mlx4_dev *dev = persist->dev; in mlx4_shutdown()
4422 mlx4_info(persist->dev, "mlx4_shutdown was called\n"); in mlx4_shutdown()
4425 mutex_lock(&persist->interface_state_mutex); in mlx4_shutdown()
4426 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) in mlx4_shutdown()
4428 mutex_unlock(&persist->interface_state_mutex); in mlx4_shutdown()
4443 struct mlx4_dev *dev = persist->dev; in mlx4_suspend()
4449 mutex_lock(&persist->interface_state_mutex); in mlx4_suspend()
4450 if (persist->interface_state & MLX4_INTERFACE_STATE_UP) in mlx4_suspend()
4452 mutex_unlock(&persist->interface_state_mutex); in mlx4_suspend()
4462 struct mlx4_dev *dev = persist->dev; in mlx4_resume()
4470 total_vfs = dev->persist->num_vfs; in mlx4_resume()
4471 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs)); in mlx4_resume()
4475 mutex_lock(&persist->interface_state_mutex); in mlx4_resume()
4476 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) { in mlx4_resume()
4477 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, in mlx4_resume()
4481 dev->persist->curr_port_type, in mlx4_resume()
4482 dev->persist->curr_port_poss_type); in mlx4_resume()
4487 mutex_unlock(&persist->interface_state_mutex); in mlx4_resume()
4509 return -1; in mlx4_verify_params()
4514 return -1; in mlx4_verify_params()
4518 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n", in mlx4_verify_params()
4522 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n"); in mlx4_verify_params()
4527 return -1; in mlx4_verify_params()
4536 if (mlx4_log_num_mgm_entry_size < -7 || in mlx4_verify_params()
4540 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n", in mlx4_verify_params()
4544 return -1; in mlx4_verify_params()
4558 return -EINVAL; in mlx4_init()
4563 return -ENOMEM; in mlx4_init()