Lines Matching +full:multi +full:- +full:ported
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
98 /* Multi Function device support required: */
142 [CMD_STAT_INTERNAL_ERR] = -EIO, in mlx4_status_to_errno()
143 [CMD_STAT_BAD_OP] = -EPERM, in mlx4_status_to_errno()
144 [CMD_STAT_BAD_PARAM] = -EINVAL, in mlx4_status_to_errno()
145 [CMD_STAT_BAD_SYS_STATE] = -ENXIO, in mlx4_status_to_errno()
146 [CMD_STAT_BAD_RESOURCE] = -EBADF, in mlx4_status_to_errno()
147 [CMD_STAT_RESOURCE_BUSY] = -EBUSY, in mlx4_status_to_errno()
148 [CMD_STAT_EXCEED_LIM] = -ENOMEM, in mlx4_status_to_errno()
149 [CMD_STAT_BAD_RES_STATE] = -EBADF, in mlx4_status_to_errno()
150 [CMD_STAT_BAD_INDEX] = -EBADF, in mlx4_status_to_errno()
151 [CMD_STAT_BAD_NVMEM] = -EFAULT, in mlx4_status_to_errno()
152 [CMD_STAT_ICM_ERROR] = -ENFILE, in mlx4_status_to_errno()
153 [CMD_STAT_BAD_QP_STATE] = -EINVAL, in mlx4_status_to_errno()
154 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT, in mlx4_status_to_errno()
155 [CMD_STAT_REG_BOUND] = -EBUSY, in mlx4_status_to_errno()
156 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN, in mlx4_status_to_errno()
157 [CMD_STAT_BAD_PKT] = -EINVAL, in mlx4_status_to_errno()
158 [CMD_STAT_BAD_SIZE] = -ENOMEM, in mlx4_status_to_errno()
159 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES, in mlx4_status_to_errno()
164 return -EIO; in mlx4_status_to_errno()
172 case -EPERM: in mlx4_errno_to_status()
174 case -EINVAL: in mlx4_errno_to_status()
176 case -ENXIO: in mlx4_errno_to_status()
178 case -EBUSY: in mlx4_errno_to_status()
180 case -ENOMEM: in mlx4_errno_to_status()
182 case -ENFILE: in mlx4_errno_to_status()
248 mlx4_enter_error_state(dev->persist); in mlx4_cmd_reset_flow()
258 u32 status = readl(&priv->mfunc.comm->slave_read); in comm_pending()
260 return (swab32(status) >> 31) != priv->cmd.comm_toggle; in comm_pending()
273 mutex_lock(&dev->persist->device_state_mutex); in mlx4_comm_cmd_post()
275 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { in mlx4_comm_cmd_post()
276 mutex_unlock(&dev->persist->device_state_mutex); in mlx4_comm_cmd_post()
277 return -EIO; in mlx4_comm_cmd_post()
280 priv->cmd.comm_toggle ^= 1; in mlx4_comm_cmd_post()
281 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31); in mlx4_comm_cmd_post()
283 &priv->mfunc.comm->slave_write); in mlx4_comm_cmd_post()
284 mutex_unlock(&dev->persist->device_state_mutex); in mlx4_comm_cmd_post()
298 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n", in mlx4_comm_cmd_poll()
299 priv->cmd.comm_toggle, cmd); in mlx4_comm_cmd_poll()
300 return -EAGAIN; in mlx4_comm_cmd_poll()
304 down(&priv->cmd.poll_sem); in mlx4_comm_cmd_poll()
319 * FLR process. The only non-zero result in the RESET command in mlx4_comm_cmd_poll()
332 mlx4_enter_error_state(dev->persist); in mlx4_comm_cmd_poll()
334 up(&priv->cmd.poll_sem); in mlx4_comm_cmd_poll()
341 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; in mlx4_comm_cmd_wait()
346 down(&cmd->event_sem); in mlx4_comm_cmd_wait()
348 spin_lock(&cmd->context_lock); in mlx4_comm_cmd_wait()
349 BUG_ON(cmd->free_head < 0); in mlx4_comm_cmd_wait()
350 context = &cmd->context[cmd->free_head]; in mlx4_comm_cmd_wait()
351 context->token += cmd->token_mask + 1; in mlx4_comm_cmd_wait()
352 cmd->free_head = context->next; in mlx4_comm_cmd_wait()
353 spin_unlock(&cmd->context_lock); in mlx4_comm_cmd_wait()
355 reinit_completion(&context->done); in mlx4_comm_cmd_wait()
365 if (!wait_for_completion_timeout(&context->done, in mlx4_comm_cmd_wait()
372 err = context->result; in mlx4_comm_cmd_wait()
373 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) { in mlx4_comm_cmd_wait()
375 vhcr_cmd, context->fw_status); in mlx4_comm_cmd_wait()
376 if (mlx4_closing_cmd_fatal_error(op, context->fw_status)) in mlx4_comm_cmd_wait()
387 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) { in mlx4_comm_cmd_wait()
396 mlx4_enter_error_state(dev->persist); in mlx4_comm_cmd_wait()
398 spin_lock(&cmd->context_lock); in mlx4_comm_cmd_wait()
399 context->next = cmd->free_head; in mlx4_comm_cmd_wait()
400 cmd->free_head = context - cmd->context; in mlx4_comm_cmd_wait()
401 spin_unlock(&cmd->context_lock); in mlx4_comm_cmd_wait()
403 up(&cmd->event_sem); in mlx4_comm_cmd_wait()
410 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) in mlx4_comm_cmd()
413 if (mlx4_priv(dev)->cmd.use_events) in mlx4_comm_cmd()
422 if (pci_channel_offline(dev->persist->pdev)) in cmd_pending()
423 return -EIO; in cmd_pending()
425 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET); in cmd_pending()
428 (mlx4_priv(dev)->cmd.toggle == in cmd_pending()
436 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; in mlx4_cmd_post()
437 u32 __iomem *hcr = cmd->hcr; in mlx4_cmd_post()
438 int ret = -EIO; in mlx4_cmd_post()
441 mutex_lock(&dev->persist->device_state_mutex); in mlx4_cmd_post()
447 if (pci_channel_offline(dev->persist->pdev) || in mlx4_cmd_post()
448 (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) { in mlx4_cmd_post()
461 if (pci_channel_offline(dev->persist->pdev)) { in mlx4_cmd_post()
493 (cmd->toggle << HCR_T_BIT) | in mlx4_cmd_post()
498 cmd->toggle = cmd->toggle ^ 1; in mlx4_cmd_post()
506 mutex_unlock(&dev->persist->device_state_mutex); in mlx4_cmd_post()
516 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr; in mlx4_slave_cmd()
519 mutex_lock(&priv->cmd.slave_cmd_mutex); in mlx4_slave_cmd()
521 vhcr->in_param = cpu_to_be64(in_param); in mlx4_slave_cmd()
522 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0; in mlx4_slave_cmd()
523 vhcr->in_modifier = cpu_to_be32(in_modifier); in mlx4_slave_cmd()
524 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff)); in mlx4_slave_cmd()
525 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN); in mlx4_slave_cmd()
526 vhcr->status = 0; in mlx4_slave_cmd()
527 vhcr->flags = !!(priv->cmd.use_events) << 6; in mlx4_slave_cmd()
530 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr); in mlx4_slave_cmd()
535 be64_to_cpu(vhcr->out_param); in mlx4_slave_cmd()
539 vhcr->status = CMD_STAT_BAD_PARAM; in mlx4_slave_cmd()
542 ret = mlx4_status_to_errno(vhcr->status); in mlx4_slave_cmd()
545 dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) in mlx4_slave_cmd()
554 be64_to_cpu(vhcr->out_param); in mlx4_slave_cmd()
558 vhcr->status = CMD_STAT_BAD_PARAM; in mlx4_slave_cmd()
561 ret = mlx4_status_to_errno(vhcr->status); in mlx4_slave_cmd()
563 if (dev->persist->state & in mlx4_slave_cmd()
572 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_slave_cmd()
581 void __iomem *hcr = priv->cmd.hcr; in mlx4_cmd_poll()
586 down(&priv->cmd.poll_sem); in mlx4_cmd_poll()
588 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { in mlx4_cmd_poll()
600 err = -EINVAL; in mlx4_cmd_poll()
611 if (pci_channel_offline(dev->persist->pdev)) { in mlx4_cmd_poll()
616 err = -EIO; in mlx4_cmd_poll()
620 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { in mlx4_cmd_poll()
631 err = -EIO; in mlx4_cmd_poll()
656 up(&priv->cmd.poll_sem); in mlx4_cmd_poll()
664 &priv->cmd.context[token & priv->cmd.token_mask]; in mlx4_cmd_event()
667 if (token != context->token) in mlx4_cmd_event()
670 context->fw_status = status; in mlx4_cmd_event()
671 context->result = mlx4_status_to_errno(status); in mlx4_cmd_event()
672 context->out_param = out_param; in mlx4_cmd_event()
674 complete(&context->done); in mlx4_cmd_event()
681 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; in mlx4_cmd_wait()
686 down(&cmd->event_sem); in mlx4_cmd_wait()
688 spin_lock(&cmd->context_lock); in mlx4_cmd_wait()
689 BUG_ON(cmd->free_head < 0); in mlx4_cmd_wait()
690 context = &cmd->context[cmd->free_head]; in mlx4_cmd_wait()
691 context->token += cmd->token_mask + 1; in mlx4_cmd_wait()
692 cmd->free_head = context->next; in mlx4_cmd_wait()
693 spin_unlock(&cmd->context_lock); in mlx4_cmd_wait()
698 err = -EINVAL; in mlx4_cmd_wait()
702 reinit_completion(&context->done); in mlx4_cmd_wait()
705 in_modifier, op_modifier, op, context->token, 1); in mlx4_cmd_wait()
711 wait_for_completion_interruptible_timeout(&context->done, in mlx4_cmd_wait()
714 context->fw_status = 0; in mlx4_cmd_wait()
715 context->out_param = 0; in mlx4_cmd_wait()
716 context->result = 0; in mlx4_cmd_wait()
719 ret_wait = (long)wait_for_completion_timeout(&context->done, in mlx4_cmd_wait()
726 err = -EBUSY; in mlx4_cmd_wait()
729 err = -EIO; in mlx4_cmd_wait()
734 err = context->result; in mlx4_cmd_wait()
739 * specific command/input_mod/opcode_mod/fw-status to be debug. in mlx4_cmd_wait()
744 context->fw_status == CMD_STAT_BAD_SIZE) in mlx4_cmd_wait()
746 op, context->fw_status); in mlx4_cmd_wait()
749 op, context->fw_status); in mlx4_cmd_wait()
750 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) in mlx4_cmd_wait()
752 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status)) in mlx4_cmd_wait()
759 *out_param = context->out_param; in mlx4_cmd_wait()
765 spin_lock(&cmd->context_lock); in mlx4_cmd_wait()
766 context->next = cmd->free_head; in mlx4_cmd_wait()
767 cmd->free_head = context - cmd->context; in mlx4_cmd_wait()
768 spin_unlock(&cmd->context_lock); in mlx4_cmd_wait()
770 up(&cmd->event_sem); in mlx4_cmd_wait()
778 if (pci_channel_offline(dev->persist->pdev)) in __mlx4_cmd()
779 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO); in __mlx4_cmd()
784 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) in __mlx4_cmd()
787 down_read(&mlx4_priv(dev)->cmd.switch_sem); in __mlx4_cmd()
788 if (mlx4_priv(dev)->cmd.use_events) in __mlx4_cmd()
797 up_read(&mlx4_priv(dev)->cmd.switch_sem); in __mlx4_cmd()
821 …mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n", in mlx4_ACCESS_MEM()
823 return -EINVAL; in mlx4_ACCESS_MEM()
828 out_param = (u64) dev->caps.function | master_addr; in mlx4_ACCESS_MEM()
830 in_param = (u64) dev->caps.function | master_addr; in mlx4_ACCESS_MEM()
843 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf); in query_pkey_block()
844 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf); in query_pkey_block()
849 return -EINVAL; in query_pkey_block()
851 in_mad->attr_mod = cpu_to_be32(index / 32); in query_pkey_block()
853 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3, in query_pkey_block()
860 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]); in query_pkey_block()
872 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) { in get_full_pkey_table()
897 struct ib_smp *smp = inbox->buf; in mlx4_MAD_IFC_wrapper()
906 struct ib_smp *outsmp = outbox->buf; in mlx4_MAD_IFC_wrapper()
907 __be16 *outtab = (__be16 *)(outsmp->data); in mlx4_MAD_IFC_wrapper()
911 slave_port = vhcr->in_modifier; in mlx4_MAD_IFC_wrapper()
914 /* network-view bit is for driver use only, and should not be passed to FW */ in mlx4_MAD_IFC_wrapper()
915 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */ in mlx4_MAD_IFC_wrapper()
916 network_view = !!(vhcr->op_modifier & 0x8); in mlx4_MAD_IFC_wrapper()
918 if (smp->base_version == 1 && in mlx4_MAD_IFC_wrapper()
919 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED && in mlx4_MAD_IFC_wrapper()
920 smp->class_version == 1) { in mlx4_MAD_IFC_wrapper()
922 if (!network_view && smp->method == IB_MGMT_METHOD_GET) { in mlx4_MAD_IFC_wrapper()
923 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) { in mlx4_MAD_IFC_wrapper()
924 index = be32_to_cpu(smp->attr_mod); in mlx4_MAD_IFC_wrapper()
925 if (port < 1 || port > dev->caps.num_ports) in mlx4_MAD_IFC_wrapper()
926 return -EINVAL; in mlx4_MAD_IFC_wrapper()
927 table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1, in mlx4_MAD_IFC_wrapper()
931 return -ENOMEM; in mlx4_MAD_IFC_wrapper()
938 pidx = priv->virt2phys_pkey[slave][port - 1][vidx]; in mlx4_MAD_IFC_wrapper()
945 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) { in mlx4_MAD_IFC_wrapper()
948 smp->attr_mod = cpu_to_be32(port); in mlx4_MAD_IFC_wrapper()
949 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, in mlx4_MAD_IFC_wrapper()
951 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); in mlx4_MAD_IFC_wrapper()
954 u8 *state = outsmp->data + PORT_STATE_OFFSET; in mlx4_MAD_IFC_wrapper()
957 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port]; in mlx4_MAD_IFC_wrapper()
958 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4); in mlx4_MAD_IFC_wrapper()
962 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) { in mlx4_MAD_IFC_wrapper()
970 smp->attr_mod = 0; in mlx4_MAD_IFC_wrapper()
972 inbox->dma, in mlx4_MAD_IFC_wrapper()
973 outbox->dma, in mlx4_MAD_IFC_wrapper()
974 vhcr->in_modifier, in mlx4_MAD_IFC_wrapper()
976 vhcr->op, in mlx4_MAD_IFC_wrapper()
982 *(__be64 *)outsmp-> in mlx4_MAD_IFC_wrapper()
985 memcpy(outsmp->data, &guid, 8); in mlx4_MAD_IFC_wrapper()
989 memset(outsmp->data + 8, 0, 56); in mlx4_MAD_IFC_wrapper()
992 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) { in mlx4_MAD_IFC_wrapper()
993 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, in mlx4_MAD_IFC_wrapper()
995 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); in mlx4_MAD_IFC_wrapper()
998 memcpy(outsmp->data + 12, &slave_node_guid, 8); in mlx4_MAD_IFC_wrapper()
1005 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs. in mlx4_MAD_IFC_wrapper()
1010 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED && in mlx4_MAD_IFC_wrapper()
1011 smp->method == IB_MGMT_METHOD_GET) || network_view) { in mlx4_MAD_IFC_wrapper()
1013 slave, smp->mgmt_class, smp->method, in mlx4_MAD_IFC_wrapper()
1015 be16_to_cpu(smp->attr_id)); in mlx4_MAD_IFC_wrapper()
1016 return -EPERM; in mlx4_MAD_IFC_wrapper()
1020 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, in mlx4_MAD_IFC_wrapper()
1021 vhcr->in_modifier, opcode_modifier, in mlx4_MAD_IFC_wrapper()
1022 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); in mlx4_MAD_IFC_wrapper()
1031 return -EPERM; in mlx4_CMD_EPERM_wrapper()
1044 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param; in mlx4_DMA_wrapper()
1045 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param; in mlx4_DMA_wrapper()
1046 if (cmd->encode_slave_id) { in mlx4_DMA_wrapper()
1051 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm, in mlx4_DMA_wrapper()
1052 vhcr->in_modifier, vhcr->op_modifier, vhcr->op, in mlx4_DMA_wrapper()
1055 if (cmd->out_is_imm) in mlx4_DMA_wrapper()
1056 vhcr->out_param = out_param; in mlx4_DMA_wrapper()
1666 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr; in mlx4_master_process_vhcr()
1679 return -ENOMEM; in mlx4_master_process_vhcr()
1683 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, in mlx4_master_process_vhcr()
1684 priv->mfunc.master.slave_state[slave].vhcr_dma, in mlx4_master_process_vhcr()
1688 if (!(dev->persist->state & in mlx4_master_process_vhcr()
1698 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param); in mlx4_master_process_vhcr()
1699 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param); in mlx4_master_process_vhcr()
1700 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier); in mlx4_master_process_vhcr()
1701 vhcr->token = be16_to_cpu(vhcr_cmd->token); in mlx4_master_process_vhcr()
1702 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff; in mlx4_master_process_vhcr()
1703 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12); in mlx4_master_process_vhcr()
1704 vhcr->e_bit = vhcr_cmd->flags & (1 << 6); in mlx4_master_process_vhcr()
1708 if (vhcr->op == cmd_info[i].opcode) { in mlx4_master_process_vhcr()
1715 vhcr->op, slave); in mlx4_master_process_vhcr()
1716 vhcr_cmd->status = CMD_STAT_BAD_PARAM; in mlx4_master_process_vhcr()
1721 if (cmd->has_inbox) { in mlx4_master_process_vhcr()
1722 vhcr->in_param &= INBOX_MASK; in mlx4_master_process_vhcr()
1725 vhcr_cmd->status = CMD_STAT_BAD_SIZE; in mlx4_master_process_vhcr()
1730 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave, in mlx4_master_process_vhcr()
1731 vhcr->in_param, in mlx4_master_process_vhcr()
1734 if (!(dev->persist->state & in mlx4_master_process_vhcr()
1737 __func__, cmd->opcode); in mlx4_master_process_vhcr()
1738 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR; in mlx4_master_process_vhcr()
1744 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) { in mlx4_master_process_vhcr()
1746 vhcr->op, slave, vhcr->in_modifier); in mlx4_master_process_vhcr()
1747 vhcr_cmd->status = CMD_STAT_BAD_OP; in mlx4_master_process_vhcr()
1752 if (cmd->has_outbox) { in mlx4_master_process_vhcr()
1755 vhcr_cmd->status = CMD_STAT_BAD_SIZE; in mlx4_master_process_vhcr()
1762 if (cmd->wrapper) { in mlx4_master_process_vhcr()
1763 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox, in mlx4_master_process_vhcr()
1765 if (cmd->out_is_imm) in mlx4_master_process_vhcr()
1766 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param); in mlx4_master_process_vhcr()
1768 in_param = cmd->has_inbox ? (u64) inbox->dma : in mlx4_master_process_vhcr()
1769 vhcr->in_param; in mlx4_master_process_vhcr()
1770 out_param = cmd->has_outbox ? (u64) outbox->dma : in mlx4_master_process_vhcr()
1771 vhcr->out_param; in mlx4_master_process_vhcr()
1773 cmd->out_is_imm, vhcr->in_modifier, in mlx4_master_process_vhcr()
1774 vhcr->op_modifier, vhcr->op, in mlx4_master_process_vhcr()
1778 if (cmd->out_is_imm) { in mlx4_master_process_vhcr()
1779 vhcr->out_param = out_param; in mlx4_master_process_vhcr()
1780 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param); in mlx4_master_process_vhcr()
1785 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) { in mlx4_master_process_vhcr()
1786 if (vhcr->op == MLX4_CMD_ALLOC_RES && in mlx4_master_process_vhcr()
1787 (vhcr->in_modifier & 0xff) == RES_COUNTER && in mlx4_master_process_vhcr()
1788 err == -EDQUOT) in mlx4_master_process_vhcr()
1794 vhcr->op, slave, vhcr->errno, err); in mlx4_master_process_vhcr()
1796 vhcr_cmd->status = mlx4_errno_to_status(err); in mlx4_master_process_vhcr()
1802 if (cmd->has_outbox && !vhcr_cmd->status) { in mlx4_master_process_vhcr()
1803 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave, in mlx4_master_process_vhcr()
1804 vhcr->out_param, in mlx4_master_process_vhcr()
1810 if (!(dev->persist->state & in mlx4_master_process_vhcr()
1820 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave, in mlx4_master_process_vhcr()
1821 priv->mfunc.master.slave_state[slave].vhcr_dma, in mlx4_master_process_vhcr()
1828 else if (vhcr->e_bit && in mlx4_master_process_vhcr()
1829 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe)) in mlx4_master_process_vhcr()
1847 struct mlx4_dev *dev = &(priv->dev); in mlx4_master_immediate_activate_vlan_qos()
1851 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_master_immediate_activate_vlan_qos()
1852 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_master_immediate_activate_vlan_qos()
1854 if (vp_oper->state.default_vlan == vp_admin->default_vlan && in mlx4_master_immediate_activate_vlan_qos()
1855 vp_oper->state.default_qos == vp_admin->default_qos && in mlx4_master_immediate_activate_vlan_qos()
1856 vp_oper->state.vlan_proto == vp_admin->vlan_proto && in mlx4_master_immediate_activate_vlan_qos()
1857 vp_oper->state.link_state == vp_admin->link_state && in mlx4_master_immediate_activate_vlan_qos()
1858 vp_oper->state.qos_vport == vp_admin->qos_vport) in mlx4_master_immediate_activate_vlan_qos()
1861 if (!(priv->mfunc.master.slave_state[slave].active && in mlx4_master_immediate_activate_vlan_qos()
1862 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) { in mlx4_master_immediate_activate_vlan_qos()
1866 vp_oper->state.link_state = vp_admin->link_state; in mlx4_master_immediate_activate_vlan_qos()
1867 return -1; in mlx4_master_immediate_activate_vlan_qos()
1873 vp_admin->default_vlan, vp_admin->default_qos, in mlx4_master_immediate_activate_vlan_qos()
1874 vp_admin->link_state); in mlx4_master_immediate_activate_vlan_qos()
1878 return -ENOMEM; in mlx4_master_immediate_activate_vlan_qos()
1880 if (vp_oper->state.default_vlan != vp_admin->default_vlan) { in mlx4_master_immediate_activate_vlan_qos()
1881 if (MLX4_VGT != vp_admin->default_vlan) { in mlx4_master_immediate_activate_vlan_qos()
1882 err = __mlx4_register_vlan(&priv->dev, port, in mlx4_master_immediate_activate_vlan_qos()
1883 vp_admin->default_vlan, in mlx4_master_immediate_activate_vlan_qos()
1887 mlx4_warn(&priv->dev, in mlx4_master_immediate_activate_vlan_qos()
1895 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN; in mlx4_master_immediate_activate_vlan_qos()
1896 mlx4_dbg(&priv->dev, in mlx4_master_immediate_activate_vlan_qos()
1898 (int)(vp_admin->default_vlan), in mlx4_master_immediate_activate_vlan_qos()
1903 work->orig_vlan_id = vp_oper->state.default_vlan; in mlx4_master_immediate_activate_vlan_qos()
1904 work->orig_vlan_ix = vp_oper->vlan_idx; in mlx4_master_immediate_activate_vlan_qos()
1907 if (vp_oper->state.default_qos != vp_admin->default_qos) in mlx4_master_immediate_activate_vlan_qos()
1908 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS; in mlx4_master_immediate_activate_vlan_qos()
1910 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN) in mlx4_master_immediate_activate_vlan_qos()
1911 vp_oper->vlan_idx = admin_vlan_ix; in mlx4_master_immediate_activate_vlan_qos()
1913 vp_oper->state.default_vlan = vp_admin->default_vlan; in mlx4_master_immediate_activate_vlan_qos()
1914 vp_oper->state.default_qos = vp_admin->default_qos; in mlx4_master_immediate_activate_vlan_qos()
1915 vp_oper->state.vlan_proto = vp_admin->vlan_proto; in mlx4_master_immediate_activate_vlan_qos()
1916 vp_oper->state.link_state = vp_admin->link_state; in mlx4_master_immediate_activate_vlan_qos()
1917 vp_oper->state.qos_vport = vp_admin->qos_vport; in mlx4_master_immediate_activate_vlan_qos()
1919 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE) in mlx4_master_immediate_activate_vlan_qos()
1920 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE; in mlx4_master_immediate_activate_vlan_qos()
1923 work->port = port; in mlx4_master_immediate_activate_vlan_qos()
1924 work->slave = slave; in mlx4_master_immediate_activate_vlan_qos()
1925 work->qos = vp_oper->state.default_qos; in mlx4_master_immediate_activate_vlan_qos()
1926 work->qos_vport = vp_oper->state.qos_vport; in mlx4_master_immediate_activate_vlan_qos()
1927 work->vlan_id = vp_oper->state.default_vlan; in mlx4_master_immediate_activate_vlan_qos()
1928 work->vlan_ix = vp_oper->vlan_idx; in mlx4_master_immediate_activate_vlan_qos()
1929 work->vlan_proto = vp_oper->state.vlan_proto; in mlx4_master_immediate_activate_vlan_qos()
1930 work->priv = priv; in mlx4_master_immediate_activate_vlan_qos()
1931 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler); in mlx4_master_immediate_activate_vlan_qos()
1932 queue_work(priv->mfunc.master.comm_wq, &work->work); in mlx4_master_immediate_activate_vlan_qos()
1942 port_qos_ctl = &priv->mfunc.master.qos_ctl[port]; in mlx4_set_default_port_qos()
1943 bitmap_zero(port_qos_ctl->priority_bm, MLX4_NUM_UP); in mlx4_set_default_port_qos()
1946 set_bit(MLX4_DEFAULT_QOS_PRIO, port_qos_ctl->priority_bm); in mlx4_set_default_port_qos()
1965 port_qos = &priv->mfunc.master.qos_ctl[port]; in mlx4_allocate_port_vpps()
1967 bitmap_weight(port_qos->priority_bm, MLX4_NUM_UP)); in mlx4_allocate_port_vpps()
1970 if (test_bit(i, port_qos->priority_bm)) in mlx4_allocate_port_vpps()
1987 port_qos->num_of_qos_vfs = num_vfs; in mlx4_allocate_port_vpps()
2001 &priv->mfunc.master.slave_state[slave]; in mlx4_master_activate_admin_state()
2003 &priv->dev, slave); in mlx4_master_activate_admin_state()
2005 for_each_set_bit(p, actv_ports.ports, priv->dev.caps.num_ports) { in mlx4_master_activate_admin_state()
2007 priv->mfunc.master.vf_oper[slave].smi_enabled[port] = in mlx4_master_activate_admin_state()
2008 priv->mfunc.master.vf_admin[slave].enable_smi[port]; in mlx4_master_activate_admin_state()
2009 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_master_activate_admin_state()
2010 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_master_activate_admin_state()
2011 if (vp_admin->vlan_proto != htons(ETH_P_8021AD) || in mlx4_master_activate_admin_state()
2012 slave_state->vst_qinq_supported) { in mlx4_master_activate_admin_state()
2013 vp_oper->state.vlan_proto = vp_admin->vlan_proto; in mlx4_master_activate_admin_state()
2014 vp_oper->state.default_vlan = vp_admin->default_vlan; in mlx4_master_activate_admin_state()
2015 vp_oper->state.default_qos = vp_admin->default_qos; in mlx4_master_activate_admin_state()
2017 vp_oper->state.link_state = vp_admin->link_state; in mlx4_master_activate_admin_state()
2018 vp_oper->state.mac = vp_admin->mac; in mlx4_master_activate_admin_state()
2019 vp_oper->state.spoofchk = vp_admin->spoofchk; in mlx4_master_activate_admin_state()
2020 vp_oper->state.tx_rate = vp_admin->tx_rate; in mlx4_master_activate_admin_state()
2021 vp_oper->state.qos_vport = vp_admin->qos_vport; in mlx4_master_activate_admin_state()
2022 vp_oper->state.guid = vp_admin->guid; in mlx4_master_activate_admin_state()
2024 if (MLX4_VGT != vp_admin->default_vlan) { in mlx4_master_activate_admin_state()
2025 err = __mlx4_register_vlan(&priv->dev, port, in mlx4_master_activate_admin_state()
2026 vp_admin->default_vlan, &(vp_oper->vlan_idx)); in mlx4_master_activate_admin_state()
2028 vp_oper->vlan_idx = NO_INDX; in mlx4_master_activate_admin_state()
2029 vp_oper->state.default_vlan = MLX4_VGT; in mlx4_master_activate_admin_state()
2030 vp_oper->state.vlan_proto = htons(ETH_P_8021Q); in mlx4_master_activate_admin_state()
2031 mlx4_warn(&priv->dev, in mlx4_master_activate_admin_state()
2036 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n", in mlx4_master_activate_admin_state()
2037 (int)(vp_oper->state.default_vlan), in mlx4_master_activate_admin_state()
2038 vp_oper->vlan_idx, slave, port); in mlx4_master_activate_admin_state()
2040 if (vp_admin->spoofchk) { in mlx4_master_activate_admin_state()
2041 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev, in mlx4_master_activate_admin_state()
2043 vp_admin->mac); in mlx4_master_activate_admin_state()
2044 if (0 > vp_oper->mac_idx) { in mlx4_master_activate_admin_state()
2045 err = vp_oper->mac_idx; in mlx4_master_activate_admin_state()
2046 vp_oper->mac_idx = NO_INDX; in mlx4_master_activate_admin_state()
2047 mlx4_warn(&priv->dev, in mlx4_master_activate_admin_state()
2052 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n", in mlx4_master_activate_admin_state()
2053 vp_oper->state.mac, vp_oper->mac_idx, slave, port); in mlx4_master_activate_admin_state()
2064 &priv->dev, slave); in mlx4_master_deactivate_admin_state()
2066 for_each_set_bit(p, actv_ports.ports, priv->dev.caps.num_ports) { in mlx4_master_deactivate_admin_state()
2068 priv->mfunc.master.vf_oper[slave].smi_enabled[port] = in mlx4_master_deactivate_admin_state()
2070 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_master_deactivate_admin_state()
2071 if (NO_INDX != vp_oper->vlan_idx) { in mlx4_master_deactivate_admin_state()
2072 __mlx4_unregister_vlan(&priv->dev, in mlx4_master_deactivate_admin_state()
2073 port, vp_oper->state.default_vlan); in mlx4_master_deactivate_admin_state()
2074 vp_oper->vlan_idx = NO_INDX; in mlx4_master_deactivate_admin_state()
2076 if (NO_INDX != vp_oper->mac_idx) { in mlx4_master_deactivate_admin_state()
2077 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac); in mlx4_master_deactivate_admin_state()
2078 vp_oper->mac_idx = NO_INDX; in mlx4_master_deactivate_admin_state()
2088 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; in mlx4_master_do_cmd()
2108 slave_state[slave].event_eq[i].eqn = -1; in mlx4_master_do_cmd()
2136 priv->mfunc.master.slave_state[slave].cookie = 0; in mlx4_master_do_cmd()
2165 mutex_lock(&priv->cmd.slave_cmd_mutex); in mlx4_master_do_cmd()
2169 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_master_do_cmd()
2172 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_master_do_cmd()
2178 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2183 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2190 &priv->mfunc.comm[slave].slave_read); in mlx4_master_do_cmd()
2196 if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP) in mlx4_master_do_cmd()
2209 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2212 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); in mlx4_master_do_cmd()
2218 &priv->mfunc.comm[slave].slave_read); in mlx4_master_do_cmd()
2233 struct mlx4_dev *dev = &priv->dev; in mlx4_master_comm_channel()
2245 lbit_vec[i] = be32_to_cpu(master->comm_arm_bit_vector[i]); in mlx4_master_comm_channel()
2246 nmbr_bits = dev->persist->num_vfs + 1; in mlx4_master_comm_channel()
2247 if (++master->next_slave >= nmbr_bits) in mlx4_master_comm_channel()
2248 master->next_slave = 0; in mlx4_master_comm_channel()
2249 slave = master->next_slave; in mlx4_master_comm_channel()
2252 if (!first && slave >= master->next_slave) in mlx4_master_comm_channel()
2262 comm_cmd = swab32(readl(&mfunc->comm[slave].slave_write)); in mlx4_master_comm_channel()
2263 slt = swab32(readl(&mfunc->comm[slave].slave_read)) >> 31; in mlx4_master_comm_channel()
2266 if (master->slave_state[slave].comm_toggle in mlx4_master_comm_channel()
2270 master->slave_state[slave].comm_toggle); in mlx4_master_comm_channel()
2271 master->slave_state[slave].comm_toggle = in mlx4_master_comm_channel()
2297 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)); in sync_toggles()
2304 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)); in sync_toggles()
2311 if (dev->persist->interface_state & in sync_toggles()
2315 return -EIO; in sync_toggles()
2319 wr_toggle = swab32(readl(&priv->mfunc.comm-> in sync_toggles()
2325 priv->cmd.comm_toggle = rd_toggle >> 31; in sync_toggles()
2338 mlx4_warn(dev, "recovering from previously mis-behaved VM\n"); in sync_toggles()
2339 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read); in sync_toggles()
2340 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write); in sync_toggles()
2341 priv->cmd.comm_toggle = 0; in sync_toggles()
2353 priv->mfunc.comm = in mlx4_multi_func_init()
2354 ioremap(pci_resource_start(dev->persist->pdev, in mlx4_multi_func_init()
2355 priv->fw.comm_bar) + in mlx4_multi_func_init()
2356 priv->fw.comm_base, MLX4_COMM_PAGESIZE); in mlx4_multi_func_init()
2358 priv->mfunc.comm = in mlx4_multi_func_init()
2359 ioremap(pci_resource_start(dev->persist->pdev, 2) + in mlx4_multi_func_init()
2361 if (!priv->mfunc.comm) { in mlx4_multi_func_init()
2370 priv->mfunc.master.slave_state = in mlx4_multi_func_init()
2371 kcalloc(dev->num_slaves, in mlx4_multi_func_init()
2374 if (!priv->mfunc.master.slave_state) in mlx4_multi_func_init()
2377 priv->mfunc.master.vf_admin = in mlx4_multi_func_init()
2378 kcalloc(dev->num_slaves, in mlx4_multi_func_init()
2381 if (!priv->mfunc.master.vf_admin) in mlx4_multi_func_init()
2384 priv->mfunc.master.vf_oper = in mlx4_multi_func_init()
2385 kcalloc(dev->num_slaves, in mlx4_multi_func_init()
2388 if (!priv->mfunc.master.vf_oper) in mlx4_multi_func_init()
2391 priv->mfunc.master.next_slave = 0; in mlx4_multi_func_init()
2393 for (i = 0; i < dev->num_slaves; ++i) { in mlx4_multi_func_init()
2394 vf_admin = &priv->mfunc.master.vf_admin[i]; in mlx4_multi_func_init()
2395 vf_oper = &priv->mfunc.master.vf_oper[i]; in mlx4_multi_func_init()
2396 s_state = &priv->mfunc.master.slave_state[i]; in mlx4_multi_func_init()
2397 s_state->last_cmd = MLX4_COMM_CMD_RESET; in mlx4_multi_func_init()
2398 s_state->vst_qinq_supported = false; in mlx4_multi_func_init()
2399 mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]); in mlx4_multi_func_init()
2401 s_state->event_eq[j].eqn = -1; in mlx4_multi_func_init()
2403 &priv->mfunc.comm[i].slave_write); in mlx4_multi_func_init()
2405 &priv->mfunc.comm[i].slave_read); in mlx4_multi_func_init()
2410 s_state->vlan_filter[port] = in mlx4_multi_func_init()
2413 if (!s_state->vlan_filter[port]) { in mlx4_multi_func_init()
2414 if (--port) in mlx4_multi_func_init()
2415 kfree(s_state->vlan_filter[port]); in mlx4_multi_func_init()
2419 admin_vport = &vf_admin->vport[port]; in mlx4_multi_func_init()
2420 oper_vport = &vf_oper->vport[port].state; in mlx4_multi_func_init()
2421 INIT_LIST_HEAD(&s_state->mcast_filters[port]); in mlx4_multi_func_init()
2422 admin_vport->default_vlan = MLX4_VGT; in mlx4_multi_func_init()
2423 oper_vport->default_vlan = MLX4_VGT; in mlx4_multi_func_init()
2424 admin_vport->qos_vport = in mlx4_multi_func_init()
2426 oper_vport->qos_vport = MLX4_VPP_DEFAULT_VPORT; in mlx4_multi_func_init()
2427 admin_vport->vlan_proto = htons(ETH_P_8021Q); in mlx4_multi_func_init()
2428 oper_vport->vlan_proto = htons(ETH_P_8021Q); in mlx4_multi_func_init()
2429 vf_oper->vport[port].vlan_idx = NO_INDX; in mlx4_multi_func_init()
2430 vf_oper->vport[port].mac_idx = NO_INDX; in mlx4_multi_func_init()
2433 spin_lock_init(&s_state->lock); in mlx4_multi_func_init()
2436 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP) { in mlx4_multi_func_init()
2437 for (port = 1; port <= dev->caps.num_ports; port++) { in mlx4_multi_func_init()
2445 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe)); in mlx4_multi_func_init()
2446 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD; in mlx4_multi_func_init()
2447 INIT_WORK(&priv->mfunc.master.comm_work, in mlx4_multi_func_init()
2449 INIT_WORK(&priv->mfunc.master.slave_event_work, in mlx4_multi_func_init()
2451 INIT_WORK(&priv->mfunc.master.slave_flr_event_work, in mlx4_multi_func_init()
2453 spin_lock_init(&priv->mfunc.master.slave_state_lock); in mlx4_multi_func_init()
2454 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock); in mlx4_multi_func_init()
2455 priv->mfunc.master.comm_wq = in mlx4_multi_func_init()
2457 if (!priv->mfunc.master.comm_wq) in mlx4_multi_func_init()
2473 destroy_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_init()
2475 while (i--) { in mlx4_multi_func_init()
2477 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); in mlx4_multi_func_init()
2479 kfree(priv->mfunc.master.vf_oper); in mlx4_multi_func_init()
2481 kfree(priv->mfunc.master.vf_admin); in mlx4_multi_func_init()
2483 kfree(priv->mfunc.master.slave_state); in mlx4_multi_func_init()
2485 iounmap(priv->mfunc.comm); in mlx4_multi_func_init()
2486 priv->mfunc.comm = NULL; in mlx4_multi_func_init()
2488 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, in mlx4_multi_func_init()
2489 priv->mfunc.vhcr, in mlx4_multi_func_init()
2490 priv->mfunc.vhcr_dma); in mlx4_multi_func_init()
2491 priv->mfunc.vhcr = NULL; in mlx4_multi_func_init()
2492 return -ENOMEM; in mlx4_multi_func_init()
2500 if (!priv->cmd.initialized) { in mlx4_cmd_init()
2501 init_rwsem(&priv->cmd.switch_sem); in mlx4_cmd_init()
2502 mutex_init(&priv->cmd.slave_cmd_mutex); in mlx4_cmd_init()
2503 sema_init(&priv->cmd.poll_sem, 1); in mlx4_cmd_init()
2504 priv->cmd.use_events = 0; in mlx4_cmd_init()
2505 priv->cmd.toggle = 1; in mlx4_cmd_init()
2506 priv->cmd.initialized = 1; in mlx4_cmd_init()
2510 if (!mlx4_is_slave(dev) && !priv->cmd.hcr) { in mlx4_cmd_init()
2511 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev, in mlx4_cmd_init()
2513 if (!priv->cmd.hcr) { in mlx4_cmd_init()
2520 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) { in mlx4_cmd_init()
2521 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev, in mlx4_cmd_init()
2523 &priv->mfunc.vhcr_dma, in mlx4_cmd_init()
2525 if (!priv->mfunc.vhcr) in mlx4_cmd_init()
2531 if (!priv->cmd.pool) { in mlx4_cmd_init()
2532 priv->cmd.pool = dma_pool_create("mlx4_cmd", in mlx4_cmd_init()
2533 &dev->persist->pdev->dev, in mlx4_cmd_init()
2536 if (!priv->cmd.pool) in mlx4_cmd_init()
2546 return -ENOMEM; in mlx4_cmd_init()
2559 if (!priv->mfunc.comm) in mlx4_report_internal_err_comm_event()
2565 for (slave = 0; slave < dev->num_slaves; slave++) { in mlx4_report_internal_err_comm_event()
2566 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read)); in mlx4_report_internal_err_comm_event()
2569 &priv->mfunc.comm[slave].slave_read); in mlx4_report_internal_err_comm_event()
2579 destroy_workqueue(priv->mfunc.master.comm_wq); in mlx4_multi_func_cleanup()
2580 for (i = 0; i < dev->num_slaves; i++) { in mlx4_multi_func_cleanup()
2582 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]); in mlx4_multi_func_cleanup()
2584 kfree(priv->mfunc.master.slave_state); in mlx4_multi_func_cleanup()
2585 kfree(priv->mfunc.master.vf_admin); in mlx4_multi_func_cleanup()
2586 kfree(priv->mfunc.master.vf_oper); in mlx4_multi_func_cleanup()
2587 dev->num_slaves = 0; in mlx4_multi_func_cleanup()
2590 iounmap(priv->mfunc.comm); in mlx4_multi_func_cleanup()
2591 priv->mfunc.comm = NULL; in mlx4_multi_func_cleanup()
2598 if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) { in mlx4_cmd_cleanup()
2599 dma_pool_destroy(priv->cmd.pool); in mlx4_cmd_cleanup()
2600 priv->cmd.pool = NULL; in mlx4_cmd_cleanup()
2603 if (!mlx4_is_slave(dev) && priv->cmd.hcr && in mlx4_cmd_cleanup()
2605 iounmap(priv->cmd.hcr); in mlx4_cmd_cleanup()
2606 priv->cmd.hcr = NULL; in mlx4_cmd_cleanup()
2608 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr && in mlx4_cmd_cleanup()
2610 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, in mlx4_cmd_cleanup()
2611 priv->mfunc.vhcr, priv->mfunc.vhcr_dma); in mlx4_cmd_cleanup()
2612 priv->mfunc.vhcr = NULL; in mlx4_cmd_cleanup()
2614 if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT)) in mlx4_cmd_cleanup()
2615 priv->cmd.initialized = 0; in mlx4_cmd_cleanup()
2628 priv->cmd.context = kmalloc_array(priv->cmd.max_cmds, in mlx4_cmd_use_events()
2631 if (!priv->cmd.context) in mlx4_cmd_use_events()
2632 return -ENOMEM; in mlx4_cmd_use_events()
2635 mutex_lock(&priv->cmd.slave_cmd_mutex); in mlx4_cmd_use_events()
2636 down_write(&priv->cmd.switch_sem); in mlx4_cmd_use_events()
2637 for (i = 0; i < priv->cmd.max_cmds; ++i) { in mlx4_cmd_use_events()
2638 priv->cmd.context[i].token = i; in mlx4_cmd_use_events()
2639 priv->cmd.context[i].next = i + 1; in mlx4_cmd_use_events()
2644 init_completion(&priv->cmd.context[i].done); in mlx4_cmd_use_events()
2647 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1; in mlx4_cmd_use_events()
2648 priv->cmd.free_head = 0; in mlx4_cmd_use_events()
2650 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds); in mlx4_cmd_use_events()
2652 for (priv->cmd.token_mask = 1; in mlx4_cmd_use_events()
2653 priv->cmd.token_mask < priv->cmd.max_cmds; in mlx4_cmd_use_events()
2654 priv->cmd.token_mask <<= 1) in mlx4_cmd_use_events()
2656 --priv->cmd.token_mask; in mlx4_cmd_use_events()
2658 down(&priv->cmd.poll_sem); in mlx4_cmd_use_events()
2659 priv->cmd.use_events = 1; in mlx4_cmd_use_events()
2660 up_write(&priv->cmd.switch_sem); in mlx4_cmd_use_events()
2662 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_cmd_use_events()
2676 mutex_lock(&priv->cmd.slave_cmd_mutex); in mlx4_cmd_use_polling()
2677 down_write(&priv->cmd.switch_sem); in mlx4_cmd_use_polling()
2678 priv->cmd.use_events = 0; in mlx4_cmd_use_polling()
2680 for (i = 0; i < priv->cmd.max_cmds; ++i) in mlx4_cmd_use_polling()
2681 down(&priv->cmd.event_sem); in mlx4_cmd_use_polling()
2683 kfree(priv->cmd.context); in mlx4_cmd_use_polling()
2684 priv->cmd.context = NULL; in mlx4_cmd_use_polling()
2686 up(&priv->cmd.poll_sem); in mlx4_cmd_use_polling()
2687 up_write(&priv->cmd.switch_sem); in mlx4_cmd_use_polling()
2689 mutex_unlock(&priv->cmd.slave_cmd_mutex); in mlx4_cmd_use_polling()
2698 return ERR_PTR(-ENOMEM); in mlx4_alloc_cmd_mailbox()
2700 mailbox->buf = dma_pool_zalloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL, in mlx4_alloc_cmd_mailbox()
2701 &mailbox->dma); in mlx4_alloc_cmd_mailbox()
2702 if (!mailbox->buf) { in mlx4_alloc_cmd_mailbox()
2704 return ERR_PTR(-ENOMEM); in mlx4_alloc_cmd_mailbox()
2717 dma_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma); in mlx4_free_cmd_mailbox()
2729 if ((vf < 0) || (vf >= dev->persist->num_vfs)) { in mlx4_get_slave_indx()
2731 vf, dev->persist->num_vfs); in mlx4_get_slave_indx()
2732 return -EINVAL; in mlx4_get_slave_indx()
2740 if (slave < 1 || slave > dev->persist->num_vfs) { in mlx4_get_vf_indx()
2743 slave, dev->num_slaves); in mlx4_get_vf_indx()
2744 return -EINVAL; in mlx4_get_vf_indx()
2746 return slave - 1; in mlx4_get_vf_indx()
2755 spin_lock(&priv->cmd.context_lock); in mlx4_cmd_wake_completions()
2756 if (priv->cmd.context) { in mlx4_cmd_wake_completions()
2757 for (i = 0; i < priv->cmd.max_cmds; ++i) { in mlx4_cmd_wake_completions()
2758 context = &priv->cmd.context[i]; in mlx4_cmd_wake_completions()
2759 context->fw_status = CMD_STAT_INTERNAL_ERR; in mlx4_cmd_wake_completions()
2760 context->result = in mlx4_cmd_wake_completions()
2762 complete(&context->done); in mlx4_cmd_wake_completions()
2765 spin_unlock(&priv->cmd.context_lock); in mlx4_cmd_wake_completions()
2776 bitmap_fill(actv_ports.ports, dev->caps.num_ports); in mlx4_get_active_ports()
2784 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1, in mlx4_get_active_ports()
2785 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports, in mlx4_get_active_ports()
2786 dev->caps.num_ports)); in mlx4_get_active_ports()
2796 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports); in mlx4_slave_convert_port()
2799 return -EINVAL; in mlx4_slave_convert_port()
2801 n = find_first_bit(actv_ports.ports, dev->caps.num_ports); in mlx4_slave_convert_port()
2812 if (test_bit(port - 1, actv_ports.ports)) in mlx4_phys_to_slave_port()
2813 return port - in mlx4_phys_to_slave_port()
2814 find_first_bit(actv_ports.ports, dev->caps.num_ports); in mlx4_phys_to_slave_port()
2816 return -1; in mlx4_phys_to_slave_port()
2828 if (port <= 0 || port > dev->caps.num_ports) in mlx4_phys_to_slaves_pport()
2831 for (i = 0; i < dev->persist->num_vfs + 1; i++) { in mlx4_phys_to_slaves_pport()
2834 if (test_bit(port - 1, actv_ports.ports)) in mlx4_phys_to_slaves_pport()
2851 for (i = 0; i < dev->persist->num_vfs + 1; i++) { in mlx4_phys_to_slaves_pport_actv()
2854 if (bitmap_equal(crit_ports->ports, actv_ports.ports, in mlx4_phys_to_slaves_pport_actv()
2855 dev->caps.num_ports)) in mlx4_phys_to_slaves_pport_actv()
2866 int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports) in mlx4_slaves_closest_port()
2869 bitmap_weight(actv_ports.ports, dev->caps.num_ports); in mlx4_slaves_closest_port()
2874 port = max_port - 1; in mlx4_slaves_closest_port()
2885 struct mlx4_dev *dev = &priv->dev; in mlx4_set_vport_qos()
2888 port_qos = &priv->mfunc.master.qos_ctl[port]; in mlx4_set_vport_qos()
2891 if (slave > port_qos->num_of_qos_vfs) { in mlx4_set_vport_qos()
2893 return -EINVAL; in mlx4_set_vport_qos()
2904 if (test_bit(i, port_qos->priority_bm) && max_tx_rate) { in mlx4_set_vport_qos()
2932 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP)) in mlx4_is_vf_vst_and_prio_qos()
2935 info = &priv->mfunc.master.qos_ctl[port]; in mlx4_is_vf_vst_and_prio_qos()
2937 if (vf_admin->default_vlan != MLX4_VGT && in mlx4_is_vf_vst_and_prio_qos()
2938 test_bit(vf_admin->default_qos, info->priority_bm)) in mlx4_is_vf_vst_and_prio_qos()
2951 !vf_admin->tx_rate) in mlx4_valid_vf_state_change()
2983 return -EPROTONOSUPPORT; in mlx4_set_vf_mac()
2986 return -EINVAL; in mlx4_set_vf_mac()
2990 return -EINVAL; in mlx4_set_vf_mac()
2993 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_mac()
2995 if (s_info->spoofchk && is_zero_ether_addr(mac)) { in mlx4_set_vf_mac()
2997 return -EPERM; in mlx4_set_vf_mac()
3000 s_info->mac = ether_addr_to_u64(mac); in mlx4_set_vf_mac()
3002 vf, port, s_info->mac); in mlx4_set_vf_mac()
3018 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL)) in mlx4_set_vf_vlan()
3019 return -EPROTONOSUPPORT; in mlx4_set_vf_vlan()
3022 return -EINVAL; in mlx4_set_vf_vlan()
3025 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP)) in mlx4_set_vf_vlan()
3026 return -EPROTONOSUPPORT; in mlx4_set_vf_vlan()
3030 return -EINVAL; in mlx4_set_vf_vlan()
3034 return -EINVAL; in mlx4_set_vf_vlan()
3038 return -EINVAL; in mlx4_set_vf_vlan()
3040 slave_state = &priv->mfunc.master.slave_state[slave]; in mlx4_set_vf_vlan()
3041 if ((proto == htons(ETH_P_8021AD)) && (slave_state->active) && in mlx4_set_vf_vlan()
3042 (!slave_state->vst_qinq_supported)) { in mlx4_set_vf_vlan()
3044 return -EPROTONOSUPPORT; in mlx4_set_vf_vlan()
3047 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_vlan()
3048 vf_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_set_vf_vlan()
3051 return -EPERM; in mlx4_set_vf_vlan()
3054 vf_admin->default_vlan = MLX4_VGT; in mlx4_set_vf_vlan()
3056 vf_admin->default_vlan = vlan; in mlx4_set_vf_vlan()
3057 vf_admin->default_qos = qos; in mlx4_set_vf_vlan()
3058 vf_admin->vlan_proto = proto; in mlx4_set_vf_vlan()
3061 * in vf_admin->rate and now, if priority supported we enforce the QoS in mlx4_set_vf_vlan()
3064 vf_admin->tx_rate) in mlx4_set_vf_vlan()
3065 vf_admin->qos_vport = slave; in mlx4_set_vf_vlan()
3071 vf_oper->state.vlan_proto != proto) || in mlx4_set_vf_vlan()
3089 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP)) in mlx4_set_vf_rate()
3090 return -EPROTONOSUPPORT; in mlx4_set_vf_rate()
3094 return -EPROTONOSUPPORT; in mlx4_set_vf_rate()
3099 return -EINVAL; in mlx4_set_vf_rate()
3102 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_rate()
3111 vf_admin->tx_rate = max_tx_rate; in mlx4_set_vf_rate()
3121 if (vf_admin->default_vlan != MLX4_VGT) in mlx4_set_vf_rate()
3133 vf_admin->qos_vport = max_tx_rate ? slave : MLX4_VPP_DEFAULT_VPORT; in mlx4_set_vf_rate()
3135 if (priv->mfunc.master.slave_state[slave].active && in mlx4_set_vf_rate()
3136 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP) in mlx4_set_vf_rate()
3143 /* mlx4_get_slave_default_vlan -
3155 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port]; in mlx4_get_slave_default_vlan()
3157 if (MLX4_VGT != vp_oper->state.default_vlan) { in mlx4_get_slave_default_vlan()
3159 *vlan = vp_oper->state.default_vlan; in mlx4_get_slave_default_vlan()
3161 *qos = vp_oper->state.default_qos; in mlx4_get_slave_default_vlan()
3176 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM)) in mlx4_set_vf_spoofchk()
3177 return -EPROTONOSUPPORT; in mlx4_set_vf_spoofchk()
3181 return -EINVAL; in mlx4_set_vf_spoofchk()
3184 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_spoofchk()
3186 u64_to_ether_addr(s_info->mac, mac); in mlx4_set_vf_spoofchk()
3189 return -EPERM; in mlx4_set_vf_spoofchk()
3192 s_info->spoofchk = setting; in mlx4_set_vf_spoofchk()
3205 return -EPROTONOSUPPORT; in mlx4_get_vf_config()
3209 return -EINVAL; in mlx4_get_vf_config()
3211 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_get_vf_config()
3212 ivf->vf = vf; in mlx4_get_vf_config()
3215 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff); in mlx4_get_vf_config()
3216 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff); in mlx4_get_vf_config()
3217 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff); in mlx4_get_vf_config()
3218 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff); in mlx4_get_vf_config()
3219 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff); in mlx4_get_vf_config()
3220 ivf->mac[5] = ((s_info->mac) & 0xff); in mlx4_get_vf_config()
3222 ivf->vlan = s_info->default_vlan; in mlx4_get_vf_config()
3223 ivf->qos = s_info->default_qos; in mlx4_get_vf_config()
3224 ivf->vlan_proto = s_info->vlan_proto; in mlx4_get_vf_config()
3227 ivf->max_tx_rate = s_info->tx_rate; in mlx4_get_vf_config()
3229 ivf->max_tx_rate = 0; in mlx4_get_vf_config()
3231 ivf->min_tx_rate = 0; in mlx4_get_vf_config()
3232 ivf->spoofchk = s_info->spoofchk; in mlx4_get_vf_config()
3233 ivf->linkstate = s_info->link_state; in mlx4_get_vf_config()
3248 return -EINVAL; in mlx4_set_vf_link_state()
3254 if (!priv->sense.do_sense_port[port]) in mlx4_set_vf_link_state()
3271 return -EINVAL; in mlx4_set_vf_link_state()
3273 s_info = &priv->mfunc.master.vf_admin[slave].vport[port]; in mlx4_set_vf_link_state()
3274 s_info->link_state = link_state; in mlx4_set_vf_link_state()
3296 return -EINVAL; in mlx4_get_counter_stats()
3305 memset(mailbox->buf, 0, sizeof(struct mlx4_counter)); in mlx4_get_counter_stats()
3309 err = mlx4_cmd_box(dev, 0, mailbox->dma, in mlx4_get_counter_stats()
3319 tmp_counter = (struct mlx4_counter *)mailbox->buf; in mlx4_get_counter_stats()
3320 counter_stats->counter_mode = tmp_counter->counter_mode; in mlx4_get_counter_stats()
3321 if (counter_stats->counter_mode == 0) { in mlx4_get_counter_stats()
3322 counter_stats->rx_frames = in mlx4_get_counter_stats()
3323 cpu_to_be64(be64_to_cpu(counter_stats->rx_frames) + in mlx4_get_counter_stats()
3324 be64_to_cpu(tmp_counter->rx_frames)); in mlx4_get_counter_stats()
3325 counter_stats->tx_frames = in mlx4_get_counter_stats()
3326 cpu_to_be64(be64_to_cpu(counter_stats->tx_frames) + in mlx4_get_counter_stats()
3327 be64_to_cpu(tmp_counter->tx_frames)); in mlx4_get_counter_stats()
3328 counter_stats->rx_bytes = in mlx4_get_counter_stats()
3329 cpu_to_be64(be64_to_cpu(counter_stats->rx_bytes) + in mlx4_get_counter_stats()
3330 be64_to_cpu(tmp_counter->rx_bytes)); in mlx4_get_counter_stats()
3331 counter_stats->tx_bytes = in mlx4_get_counter_stats()
3332 cpu_to_be64(be64_to_cpu(counter_stats->tx_bytes) + in mlx4_get_counter_stats()
3333 be64_to_cpu(tmp_counter->tx_bytes)); in mlx4_get_counter_stats()
3351 return -EINVAL; in mlx4_get_vf_stats()
3354 return -EPROTONOSUPPORT; in mlx4_get_vf_stats()
3358 return -EINVAL; in mlx4_get_vf_stats()
3363 vf_stats->rx_packets = be64_to_cpu(tmp_vf_stats.rx_frames); in mlx4_get_vf_stats()
3364 vf_stats->tx_packets = be64_to_cpu(tmp_vf_stats.tx_frames); in mlx4_get_vf_stats()
3365 vf_stats->rx_bytes = be64_to_cpu(tmp_vf_stats.rx_bytes); in mlx4_get_vf_stats()
3366 vf_stats->tx_bytes = be64_to_cpu(tmp_vf_stats.tx_bytes); in mlx4_get_vf_stats()
3377 if (slave < 1 || slave >= dev->num_slaves || in mlx4_vf_smi_enabled()
3381 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] == in mlx4_vf_smi_enabled()
3393 if (slave < 1 || slave >= dev->num_slaves || in mlx4_vf_get_enable_smi_admin()
3397 return priv->mfunc.master.vf_admin[slave].enable_smi[port] == in mlx4_vf_get_enable_smi_admin()
3407 &priv->dev, slave); in mlx4_vf_set_enable_smi_admin()
3409 priv->dev.caps.num_ports) + 1; in mlx4_vf_set_enable_smi_admin()
3410 int max_port = min_port - 1 + in mlx4_vf_set_enable_smi_admin()
3411 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports); in mlx4_vf_set_enable_smi_admin()
3416 if (slave < 1 || slave >= dev->num_slaves || in mlx4_vf_set_enable_smi_admin()
3419 return -EINVAL; in mlx4_vf_set_enable_smi_admin()
3421 if (min_port == max_port && dev->caps.num_ports > 1) { in mlx4_vf_set_enable_smi_admin()
3422 mlx4_info(dev, "SMI access disallowed for single ported VFs\n"); in mlx4_vf_set_enable_smi_admin()
3423 return -EPROTONOSUPPORT; in mlx4_vf_set_enable_smi_admin()
3426 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled; in mlx4_vf_set_enable_smi_admin()