24 #define MTK_PCIE_BASE(n)		(0x1a143000 + (n) * 0x2000)
38 #define MTK_WED_MAX_GROUP_SIZE		0x100
39 #define MTK_WED_VLD_GROUP_SIZE		0x40
61 		.tx_bm_tkid		= 0x088,
62 		.wpdma_rx_ring0		= 0x770,
63 		.reset_idx_tx_mask	= GENMASK(3, 0),
72 		.tx_bm_tkid		= 0x0c8,
73 		.wpdma_rx_ring0		= 0x770,
74 		.reset_idx_tx_mask	= GENMASK(1, 0),
83 		.tx_bm_tkid		= 0x0c8,
84 		.wpdma_rx_ring0		= 0x7d0,
85 		.reset_idx_tx_mask	= GENMASK(1, 0),
101 	return wed_m32(dev, reg, 0, mask);  in wed_set()
107 	return wed_m32(dev, reg, mask, 0);  in wed_clr()
119 	wdma_m32(dev, reg, 0, mask);  in wdma_set()
125 	wdma_m32(dev, reg, mask, 0);  in wdma_clr()
165 			      0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG))  in mtk_wdma_v3_rx_reset()
170 			      0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG))  in mtk_wdma_v3_rx_reset()
178 			      0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG))  in mtk_wdma_v3_rx_reset()
183 			      0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG))  in mtk_wdma_v3_rx_reset()
213 	wdma_w32(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0),  in mtk_wdma_v3_rx_reset()
218 	wdma_clr(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0),  in mtk_wdma_v3_rx_reset()
244 				 !(status & mask), 0, 10000);  in mtk_wdma_rx_reset()
250 	wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);  in mtk_wdma_rx_reset()
252 	for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++) {  in mtk_wdma_rx_reset()
257 			 MTK_WDMA_RING_RX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);  in mtk_wdma_rx_reset()
293 			      0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG))  in mtk_wdma_v3_tx_reset()
298 			      0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG))  in mtk_wdma_v3_tx_reset()
306 			      0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG))  in mtk_wdma_v3_tx_reset()
311 			      0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG))  in mtk_wdma_v3_tx_reset()
335 	wdma_w32(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0),  in mtk_wdma_v3_tx_reset()
340 	wdma_clr(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0),  in mtk_wdma_v3_tx_reset()
366 			       !(status & mask), 0, 10000))  in mtk_wdma_tx_reset()
371 	wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);  in mtk_wdma_tx_reset()
373 	for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)  in mtk_wdma_tx_reset()
375 			 MTK_WDMA_RING_TX(i) + MTK_WED_RING_OFS_CPU_IDX, 0);  in mtk_wdma_tx_reset()
385 			       !(status & mask), 0, 1000))  in mtk_wed_reset()
420 	case 0:  in mtk_wed_wo_reset()
444 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {  in mtk_wed_fe_reset()
471 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {  in mtk_wed_fe_reset_complete()
508 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {  in mtk_wed_assign()
529 		return 0;  in mtk_wed_amsdu_buffer_alloc()
536 	for (i = 0; i < MTK_WED_AMSDU_NPAGES; i++) {  in mtk_wed_amsdu_buffer_alloc()
556 	return 0;  in mtk_wed_amsdu_buffer_alloc()
559 	for (i--; i >= 0; i--)  in mtk_wed_amsdu_buffer_alloc()
574 	for (i = 0; i < MTK_WED_AMSDU_NPAGES; i++) {  in mtk_wed_amsdu_free_buffer()
589 		return 0;  in mtk_wed_amsdu_init()
591 	for (i = 0; i < MTK_WED_AMSDU_NPAGES; i++)  in mtk_wed_amsdu_init()
625 	if (dev->wlan.id == 0x7991)  in mtk_wed_amsdu_init()
630 	return 0;  in mtk_wed_amsdu_init()
637 	int i, page_idx = 0, n_pages, ring_size;  in mtk_wed_tx_buffer_alloc()
667 	for (i = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {  in mtk_wed_tx_buffer_alloc()
677 		page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,  in mtk_wed_tx_buffer_alloc()
692 		for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {  in mtk_wed_tx_buffer_alloc()
712 				desc->info = 0;  in mtk_wed_tx_buffer_alloc()
727 	return 0;  in mtk_wed_tx_buffer_alloc()
735 	int i, page_idx = 0;  in mtk_wed_free_tx_buffer()
743 	for (i = 0; i < dev->tx_buf_ring.size; i += MTK_WED_BUF_PER_PAGE) {  in mtk_wed_free_tx_buffer()
771 	int i, page_idx = 0;  in mtk_wed_hwrro_buffer_alloc()
774 		return 0;  in mtk_wed_hwrro_buffer_alloc()
791 	for (i = 0; i < MTK_WED_RX_PG_BM_CNT; i += MTK_WED_RX_BUF_PER_PAGE) {  in mtk_wed_hwrro_buffer_alloc()
800 		page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,  in mtk_wed_hwrro_buffer_alloc()
813 		for (s = 0; s < MTK_WED_RX_BUF_PER_PAGE; s++) {  in mtk_wed_hwrro_buffer_alloc()
824 	return 0;  in mtk_wed_hwrro_buffer_alloc()
852 	int i, page_idx = 0;  in mtk_wed_hwrro_free_buffer()
863 	for (i = 0; i < MTK_WED_RX_PG_BM_CNT; i += MTK_WED_RX_BUF_PER_PAGE) {  in mtk_wed_hwrro_free_buffer()
926 		FIELD_PREP(MTK_WED_RX_BM_DYN_ALLOC_TH_H, 0xffff));  in mtk_wed_rx_buffer_hw_init()
954 	for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)  in mtk_wed_free_tx_rings()
956 	for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)  in mtk_wed_free_tx_rings()
986 	wed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0);  in mtk_wed_set_ext_int()
999 			FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103));  in mtk_wed_set_512_support()
1002 			FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100));  in mtk_wed_set_512_support()
1013 	for (i = 0; i < 3; i++) {  in mtk_wed_check_wfdma_rx_fill()
1027 	return 0;  in mtk_wed_check_wfdma_rx_fill()
1049 		regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);  in mtk_wed_dma_disable()
1080 	wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);  in mtk_wed_stop()
1081 	wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);  in mtk_wed_stop()
1082 	wdma_w32(dev, MTK_WDMA_INT_MASK, 0);  in mtk_wed_stop()
1083 	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);  in mtk_wed_stop()
1088 	wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);  in mtk_wed_stop()
1089 	wed_w32(dev, MTK_WED_EXT_INT_MASK2, 0);  in mtk_wed_stop()
1154 	memset(dev, 0, sizeof(*dev));  in __mtk_wed_detach()
1183 			regmap_update_bits(regs, 0, BIT(0), BIT(0));  in mtk_wed_bus_init()
1188 				dev->hw->pcie_base | 0xc08);  in mtk_wed_bus_init()
1190 				dev->hw->pcie_base | 0xc04);  in mtk_wed_bus_init()
1194 				dev->hw->pcie_base | 0x180);  in mtk_wed_bus_init()
1196 				dev->hw->pcie_base | 0x184);  in mtk_wed_bus_init()
1214 			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0));  in mtk_wed_bus_init()
1247 	wed_w32(dev, MTK_WED_RRO_RX_D_CFG(0), dev->wlan.wpdma_rx_rro[0]);  in mtk_wed_set_wpdma()
1249 	for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++)  in mtk_wed_set_wpdma()
1251 			dev->wlan.wpdma_rx_pg + i * 0x10);  in mtk_wed_set_wpdma()
1273 		u32 offset = dev->hw->index ? 0x04000400 : 0;  in mtk_wed_hw_init_early()
1280 		wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);  in mtk_wed_hw_init_early()
1281 		wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);  in mtk_wed_hw_init_early()
1295 				   MTK_WDMA_RING_TX(0)) |  in mtk_wed_hw_init_early()
1297 				   MTK_WDMA_RING_RX(0)));  in mtk_wed_hw_init_early()
1314 	return 0;  in mtk_wed_rro_ring_alloc()
1327 	if (index < 0)  in mtk_wed_rro_alloc()
1360 		.ring[0] = {  in mtk_wed_rro_cfg()
1382 		FIELD_PREP(MTK_WED_RROQM_MIOD_MID_DW, 0x70 >> 2) |  in mtk_wed_rro_hw_init()
1383 		FIELD_PREP(MTK_WED_RROQM_MIOD_MOD_DW, 0x10 >> 2) |  in mtk_wed_rro_hw_init()
1393 	wed_w32(dev, MTK_WED_RROQM_FDBK_CTRL2, 0);  in mtk_wed_rro_hw_init()
1400 	wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);  in mtk_wed_rro_hw_init()
1422 				   0x3 + dev->hw->index));  in mtk_wed_route_qm_hw_init()
1427 				   0x3 + dev->hw->index));  in mtk_wed_route_qm_hw_init()
1463 			FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |  in mtk_wed_hw_init()
1466 			FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |  in mtk_wed_hw_init()
1512 		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);  in mtk_wed_hw_init()
1529 		wed_w32(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG, 0);  in mtk_wed_hw_init()
1547 	for (i = 0; i < size; i++) {  in mtk_wed_ring_reset()
1551 		desc->buf0 = 0;  in mtk_wed_ring_reset()
1556 		desc->buf1 = 0;  in mtk_wed_ring_reset()
1557 		desc->info = 0;  in mtk_wed_ring_reset()
1612 		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);  in mtk_wed_rx_reset()
1625 		wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);  in mtk_wed_rx_reset()
1656 		wed_set(dev, MTK_WED_RTQM_RST, BIT(0));  in mtk_wed_rx_reset()
1657 		wed_clr(dev, MTK_WED_RTQM_RST, BIT(0));  in mtk_wed_rx_reset()
1685 		wed_w32(dev, MTK_WED_RESET_IDX, 0);  in mtk_wed_rx_reset()
1711 	for (i = 0; i < ARRAY_SIZE(dev->rx_ring); i++) {  in mtk_wed_rx_reset()
1721 	return 0;  in mtk_wed_rx_reset()
1731 	for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) {  in mtk_wed_reset_dma()
1748 		wed_w32(dev, MTK_WED_RESET_IDX, 0);  in mtk_wed_reset_dma()
1790 		wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);  in mtk_wed_reset_dma()
1802 	for (i = 0; i < 100; i++) {  in mtk_wed_reset_dma()
1809 		if (val == 0x40)  in mtk_wed_reset_dma()
1832 			wed_w32(dev, MTK_WED_RX1_CTRL2, 0);  in mtk_wed_reset_dma()
1837 		wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);  in mtk_wed_reset_dma()
1846 		wed_w32(dev, MTK_WED_RESET_IDX, 0);  in mtk_wed_reset_dma()
1872 	return 0;  in mtk_wed_ring_alloc()
1893 	wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);  in mtk_wed_wdma_rx_ring_setup()
1900 	return 0;  in mtk_wed_wdma_rx_ring_setup()
1921 		for (i = 0; i < MTK_WED_WDMA_RING_SIZE; i++) {  in mtk_wed_wdma_tx_ring_setup()
1922 			desc->buf0 = 0;  in mtk_wed_wdma_tx_ring_setup()
1924 			desc->buf1 = 0;  in mtk_wed_wdma_tx_ring_setup()
1927 			desc->buf0 = 0;  in mtk_wed_wdma_tx_ring_setup()
1929 			desc->buf1 = 0;  in mtk_wed_wdma_tx_ring_setup()
1939 	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);  in mtk_wed_wdma_tx_ring_setup()
1940 	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);  in mtk_wed_wdma_tx_ring_setup()
1951 			0);  in mtk_wed_wdma_tx_ring_setup()
1953 			0);  in mtk_wed_wdma_tx_ring_setup()
1956 	return 0;  in mtk_wed_wdma_tx_ring_setup()
1972 	skb_set_mac_header(skb, 0);  in mtk_wed_ppe_check()
1981 	u32 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));  in mtk_wed_configure_irq()
2010 				   dev->wlan.tx_tbit[0]) |  in mtk_wed_configure_irq()
2028 					   dev->wlan.rx_tbit[0]) |  in mtk_wed_configure_irq()
2033 						GENMASK(1, 0));  in mtk_wed_configure_irq()
2094 			FIELD_PREP(MTK_WED_WDMA_RX_PREF_BURST_SIZE, 0x10) |  in mtk_wed_dma_enable()
2095 			FIELD_PREP(MTK_WED_WDMA_RX_PREF_LOW_THRES, 0x8));  in mtk_wed_dma_enable()
2125 		FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |  in mtk_wed_dma_enable()
2126 		FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL, 0x2));  in mtk_wed_dma_enable()
2131 			FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE, 0x10) |  in mtk_wed_dma_enable()
2132 			FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_LOW_THRES, 0x8));  in mtk_wed_dma_enable()
2139 	for (i = 0; i < MTK_WED_RX_QUEUES; i++) {  in mtk_wed_dma_enable()
2188 			   dev->wlan.rro_rx_tbit[0]) |  in mtk_wed_start_hw_rro()
2200 			   dev->wlan.rx_pg_tbit[0]) |  in mtk_wed_start_hw_rro()
2212 	for (i = 0; i < MTK_WED_RX_QUEUES; i++) {  in mtk_wed_start_hw_rro()
2223 	for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++) {  in mtk_wed_start_hw_rro()
2267 	int i, count = 0;  in mtk_wed_ind_rx_ring_setup()
2271 		readl(regs) & 0xfffffff0);  in mtk_wed_ind_rx_ring_setup()
2289 	for (i = 0; i < dev->wlan.ind_cmd.se_group_nums; i++) {  in mtk_wed_ind_rx_ring_setup()
2293 			MTK_WED_ADDR_ELEM_TBL_WR | (i & 0x7f));  in mtk_wed_ind_rx_ring_setup()
2304 	for (i = 0; i < dev->wlan.ind_cmd.particular_sid; i++) {  in mtk_wed_ind_rx_ring_setup()
2311 		count = 0;  in mtk_wed_ind_rx_ring_setup()
2323 	return 0;  in mtk_wed_ind_rx_ring_setup()
2334 	for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)  in mtk_wed_start()
2348 		val |= BIT(0) | (BIT(1) * !!dev->hw->index);  in mtk_wed_start()
2383 	int ret = 0;  in mtk_wed_attach()
2441 				   BIT(hw->index), 0);  in mtk_wed_attach()
2504 		wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, 0);  in mtk_wed_tx_ring_setup()
2510 	wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_CPU_IDX, 0);  in mtk_wed_tx_ring_setup()
2516 	wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);  in mtk_wed_tx_ring_setup()
2518 	return 0;  in mtk_wed_tx_ring_setup()
2535 	for (i = 0; i < 12; i += 4) {  in mtk_wed_txfree_ring_setup()
2542 	return 0;  in mtk_wed_txfree_ring_setup()
2575 	return 0;  in mtk_wed_rx_ring_setup()
2614 	int ret = 0;  in mtk_wed_flow_add()
2705 			return 0;  in mtk_wed_setup_tc_block()
2723 		return 0;  in mtk_wed_setup_tc_block()
2735 		return 0;  in mtk_wed_setup_tc_block()
2798 	irq = platform_get_irq(pdev, 0);  in mtk_wed_add_hw()
2799 	if (irq < 0)  in mtk_wed_add_hw()
2846 			regmap_write(hw->mirror, 0, 0);  in mtk_wed_add_hw()
2847 			regmap_write(hw->mirror, 4, 0);  in mtk_wed_add_hw()
2877 	for (i = 0; i < ARRAY_SIZE(hw_list); i++) {  in mtk_wed_exit()