Lines Matching +full:pdma +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2009-2016 John Crispin <[email protected]>
5 * Copyright (C) 2009-2016 Felix Fietkau <[email protected]>
6 * Copyright (C) 2013-2016 Michael Lee <[email protected]>
12 #include <linux/dma-mapping.h>
57 #define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
62 #define MTK_PP_MAX_BUF_SIZE (PAGE_SIZE - MTK_PP_PAD)
71 #define MTK_HW_LRO_TIMER_UNIT 1 /* 20 us */
72 #define MTK_HW_LRO_REFRESH_TIME 50000 /* 1 sec. */
74 #define MTK_HW_LRO_AGE_TIME 50 /* 1ms */
100 /* PDMA HW LRO Alter Flow Timer Register */
136 /* Unicast Filter MAC Address Register - Low */
140 /* Unicast Filter MAC Address Register - High */
157 #define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))
160 #define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2))
170 /* PDMA HW LRO Control Registers */
189 #define MTK_PDMA_SIZE_8DWORDS (1 << 4)
191 /* PDMA Global Configuration Register */
195 /* PDMA Reset Index Register */
199 /* PDMA Delay Interrupt Register */
213 /* PDMA HW LRO Alter Flow Delta Register */
216 /* PDMA HW LRO IP Setting Registers */
221 /* PDMA HW LRO Ring Control Registers */
264 #define MTK_TX_DMA_BUSY BIT(1)
291 #define MTK_TX_DONE_INT1 BIT(1)
332 #define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
333 #define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len)
345 /* PDMA on MT7628 */
353 #define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
354 #define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
378 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
381 /* PDMA descriptor rxd5 */
389 /* PDMA V2 descriptor rxd3 */
409 #define PHY_IAC_CMD_WRITE FIELD_PREP(PHY_IAC_CMD_MASK, 1)
414 #define PHY_IAC_START_C22 FIELD_PREP(PHY_IAC_START_MASK, 1)
430 #define MTK_USXGMII_PCS_MODE GENMASK(3, 1)
460 #define MAC_MCR_FORCE_DPX BIT(1)
473 #define MAC_MSR_DPX BIT(1)
503 #define TRGMII_MODE BIT(1)
562 #define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
568 #define GEPHY_MAC_SEL BIT(1)
572 #define QPHY_SEL_MASK GENMASK(1, 0)
655 /* struct mtk_hw_stats - the structure that holds the traffic statistics.
686 /* PDMA descriptor can point at 1-2 segments. This enum allows us to
855 /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
875 /* struct mtk_tx_ring - This struct holds info describing a TX ring
896 struct mtk_tx_dma *dma_pdma; /* For MT7628/88 PDMA handling */
901 /* PDMA rx ring mode */
908 /* struct mtk_rx_ring - This struct holds info describing a RX ring
1017 /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
1020 /* 0: GMAC2 -> GEPHY, 1: GMAC0 -> GePHY */
1024 /* 0: U3 -> QPHY, 1: GMAC2 -> QPHY */
1028 /* 2: GMAC1 -> SGMII, 3: GMAC2 -> SGMII */
1033 /* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
1076 u8 gso:1;
1077 u8 csum:1;
1078 u8 vlan:1;
1079 u8 first:1;
1080 u8 last:1;
1097 } pdma; member
1128 /* struct mtk_eth_data - This is the structure holding all differences
1186 /* struct mtk_eth - This is the main datasructure for holding the state
1195 * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
1205 * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
1299 /* struct mtk_mac - the structure that holds the info about the MACs of the
1328 return eth->soc->version == 1; in mtk_is_netsys_v1()
1333 return eth->soc->version > 1; in mtk_is_netsys_v2_or_greater()
1338 return eth->soc->version > 2; in mtk_is_netsys_v3_or_greater()
1344 const struct mtk_soc_data *soc = ppe->eth->soc; in mtk_foe_get_entry()
1346 return ppe->foe_table + hash * soc->foe_entry_size; in mtk_foe_get_entry()