Lines Matching +full:0 +full:x000e000e
35 module_param_named(msg_level, mtk_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
46 .tx_irq_mask = 0x1a1c,
47 .tx_irq_status = 0x1a18,
49 .rx_ptr = 0x0900,
50 .rx_cnt_cfg = 0x0904,
51 .pcrx_ptr = 0x0908,
52 .glo_cfg = 0x0a04,
53 .rst_idx = 0x0a08,
54 .delay_irq = 0x0a0c,
55 .irq_status = 0x0a20,
56 .irq_mask = 0x0a28,
57 .adma_rx_dbg0 = 0x0a38,
58 .int_grp = 0x0a50,
61 .qtx_cfg = 0x1800,
62 .qtx_sch = 0x1804,
63 .rx_ptr = 0x1900,
64 .rx_cnt_cfg = 0x1904,
65 .qcrx_ptr = 0x1908,
66 .glo_cfg = 0x1a04,
67 .rst_idx = 0x1a08,
68 .delay_irq = 0x1a0c,
69 .fc_th = 0x1a10,
70 .tx_sch_rate = 0x1a14,
71 .int_grp = 0x1a20,
72 .hred = 0x1a44,
73 .ctx_ptr = 0x1b00,
74 .dtx_ptr = 0x1b04,
75 .crx_ptr = 0x1b10,
76 .drx_ptr = 0x1b14,
77 .fq_head = 0x1b20,
78 .fq_tail = 0x1b24,
79 .fq_count = 0x1b28,
80 .fq_blen = 0x1b2c,
82 .gdm1_cnt = 0x2400,
84 [0] = 0x4444,
86 .ppe_base = 0x0c00,
88 [0] = 0x2800,
89 [1] = 0x2c00,
91 .pse_iq_sta = 0x0110,
92 .pse_oq_sta = 0x0118,
96 .tx_irq_mask = 0x0a28,
97 .tx_irq_status = 0x0a20,
99 .rx_ptr = 0x0900,
100 .rx_cnt_cfg = 0x0904,
101 .pcrx_ptr = 0x0908,
102 .glo_cfg = 0x0a04,
103 .rst_idx = 0x0a08,
104 .delay_irq = 0x0a0c,
105 .irq_status = 0x0a20,
106 .irq_mask = 0x0a28,
107 .int_grp = 0x0a50,
112 .tx_irq_mask = 0x461c,
113 .tx_irq_status = 0x4618,
115 .rx_ptr = 0x4100,
116 .rx_cnt_cfg = 0x4104,
117 .pcrx_ptr = 0x4108,
118 .glo_cfg = 0x4204,
119 .rst_idx = 0x4208,
120 .delay_irq = 0x420c,
121 .irq_status = 0x4220,
122 .irq_mask = 0x4228,
123 .adma_rx_dbg0 = 0x4238,
124 .int_grp = 0x4250,
127 .qtx_cfg = 0x4400,
128 .qtx_sch = 0x4404,
129 .rx_ptr = 0x4500,
130 .rx_cnt_cfg = 0x4504,
131 .qcrx_ptr = 0x4508,
132 .glo_cfg = 0x4604,
133 .rst_idx = 0x4608,
134 .delay_irq = 0x460c,
135 .fc_th = 0x4610,
136 .int_grp = 0x4620,
137 .hred = 0x4644,
138 .ctx_ptr = 0x4700,
139 .dtx_ptr = 0x4704,
140 .crx_ptr = 0x4710,
141 .drx_ptr = 0x4714,
142 .fq_head = 0x4720,
143 .fq_tail = 0x4724,
144 .fq_count = 0x4728,
145 .fq_blen = 0x472c,
146 .tx_sch_rate = 0x4798,
148 .gdm1_cnt = 0x1c00,
150 [0] = 0x3333,
151 [1] = 0x4444,
153 .ppe_base = 0x2000,
155 [0] = 0x4800,
156 [1] = 0x4c00,
158 .pse_iq_sta = 0x0180,
159 .pse_oq_sta = 0x01a0,
163 .tx_irq_mask = 0x461c,
164 .tx_irq_status = 0x4618,
166 .rx_ptr = 0x6900,
167 .rx_cnt_cfg = 0x6904,
168 .pcrx_ptr = 0x6908,
169 .glo_cfg = 0x6a04,
170 .rst_idx = 0x6a08,
171 .delay_irq = 0x6a0c,
172 .irq_status = 0x6a20,
173 .irq_mask = 0x6a28,
174 .adma_rx_dbg0 = 0x6a38,
175 .int_grp = 0x6a50,
178 .qtx_cfg = 0x4400,
179 .qtx_sch = 0x4404,
180 .rx_ptr = 0x4500,
181 .rx_cnt_cfg = 0x4504,
182 .qcrx_ptr = 0x4508,
183 .glo_cfg = 0x4604,
184 .rst_idx = 0x4608,
185 .delay_irq = 0x460c,
186 .fc_th = 0x4610,
187 .int_grp = 0x4620,
188 .hred = 0x4644,
189 .ctx_ptr = 0x4700,
190 .dtx_ptr = 0x4704,
191 .crx_ptr = 0x4710,
192 .drx_ptr = 0x4714,
193 .fq_head = 0x4720,
194 .fq_tail = 0x4724,
195 .fq_count = 0x4728,
196 .fq_blen = 0x472c,
197 .tx_sch_rate = 0x4798,
199 .gdm1_cnt = 0x1c00,
201 [0] = 0x3333,
202 [1] = 0x4444,
203 [2] = 0xcccc,
205 .ppe_base = 0x2000,
207 [0] = 0x4800,
208 [1] = 0x4c00,
209 [2] = 0x5000,
211 .pse_iq_sta = 0x0180,
212 .pse_oq_sta = 0x01a0,
319 return 0; in mtk_mdio_busy_wait()
335 if (ret < 0) in _mtk_mdio_write_c22()
347 if (ret < 0) in _mtk_mdio_write_c22()
350 return 0; in _mtk_mdio_write_c22()
359 if (ret < 0) in _mtk_mdio_write_c45()
371 if (ret < 0) in _mtk_mdio_write_c45()
383 if (ret < 0) in _mtk_mdio_write_c45()
386 return 0; in _mtk_mdio_write_c45()
394 if (ret < 0) in _mtk_mdio_read_c22()
405 if (ret < 0) in _mtk_mdio_read_c22()
417 if (ret < 0) in _mtk_mdio_read_c45()
429 if (ret < 0) in _mtk_mdio_read_c45()
440 if (ret < 0) in _mtk_mdio_read_c45()
483 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; in mt7621_gmac0_rgmii_adjust()
488 return 0; in mt7621_gmac0_rgmii_adjust()
510 mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), in mtk_setup_bridge_switch()
531 0 : mac->id; in mtk_mac_select_pcs()
545 int val, ge_mode, err = 0; in mtk_mac_config()
599 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) in mtk_mac_config()
605 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, in mtk_mac_config()
607 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); in mtk_mac_config()
617 ge_mode = 0; in mtk_mac_config()
695 return 0; in mtk_mac_finish()
835 mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); in mtk_mdio_config()
961 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
967 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], in mtk_set_mac_address()
975 return 0; in mtk_set_mac_address()
998 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); in mtk_stats_update_mac()
1002 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); in mtk_stats_update_mac()
1004 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); in mtk_stats_update_mac()
1006 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); in mtk_stats_update_mac()
1008 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); in mtk_stats_update_mac()
1010 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); in mtk_stats_update_mac()
1012 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); in mtk_stats_update_mac()
1014 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); in mtk_stats_update_mac()
1018 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); in mtk_stats_update_mac()
1020 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); in mtk_stats_update_mac()
1022 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); in mtk_stats_update_mac()
1023 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); in mtk_stats_update_mac()
1027 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); in mtk_stats_update_mac()
1030 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); in mtk_stats_update_mac()
1032 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); in mtk_stats_update_mac()
1034 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); in mtk_stats_update_mac()
1035 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); in mtk_stats_update_mac()
1039 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); in mtk_stats_update_mac()
1050 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_stats_update()
1165 for (j = 0; j < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); j++) { in mtk_init_fq_dma()
1179 for (i = 0; i < len; i++) { in mtk_init_fq_dma()
1192 txd->txd4 = 0; in mtk_init_fq_dma()
1194 txd->txd5 = 0; in mtk_init_fq_dma()
1195 txd->txd6 = 0; in mtk_init_fq_dma()
1196 txd->txd7 = 0; in mtk_init_fq_dma()
1197 txd->txd8 = 0; in mtk_init_fq_dma()
1207 return 0; in mtk_init_fq_dma()
1284 tx_buf->flags = 0; in mtk_tx_unmap()
1376 data = 0; in mtk_tx_set_dma_desc_v2()
1388 data = 0; in mtk_tx_set_dma_desc_v2()
1393 WRITE_ONCE(desc->txd7, 0); in mtk_tx_set_dma_desc_v2()
1394 WRITE_ONCE(desc->txd8, 0); in mtk_tx_set_dma_desc_v2()
1431 int k = 0; in mtk_tx_map()
1440 memset(itx_buf, 0, sizeof(*itx_buf)); in mtk_tx_map()
1458 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_tx_map()
1460 unsigned int offset = 0; in mtk_tx_map()
1467 (i & 0x1)) { in mtk_tx_map()
1478 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); in mtk_tx_map()
1495 memset(tx_buf, 0, sizeof(*tx_buf)); in mtk_tx_map()
1513 if (k & 0x1) in mtk_tx_map()
1541 return 0; in mtk_tx_map()
1567 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in mtk_cal_txd_req()
1583 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_queue_stopped()
1590 return 0; in mtk_queue_stopped()
1597 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_wake_queue()
1633 if (skb_cow_head(skb, 0)) { in mtk_start_xmit()
1646 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) in mtk_start_xmit()
1670 return ð->rx_ring[0]; in mtk_get_rx_ring()
1672 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { in mtk_get_rx_ring()
1693 ring = ð->rx_ring[0]; in mtk_update_rx_cpu_idx()
1696 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { in mtk_update_rx_cpu_idx()
1716 .order = 0, in mtk_create_page_pool()
1735 if (err < 0) in mtk_create_page_pool()
1808 return 0; in mtk_xdp_frame_map()
1824 int err, index = 0, n_desc = 1, nr_frags; in mtk_xdp_submit_frame()
1832 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; in mtk_xdp_submit_frame()
1846 memset(tx_buf, 0, sizeof(*tx_buf)); in mtk_xdp_submit_frame()
1852 if (err < 0) in mtk_xdp_submit_frame()
1858 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { in mtk_xdp_submit_frame()
1865 memset(tx_buf, 0, sizeof(*tx_buf)); in mtk_xdp_submit_frame()
1869 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); in mtk_xdp_submit_frame()
1909 return 0; in mtk_xdp_submit_frame()
1937 int i, nxmit = 0; in mtk_xdp_xmit()
1942 for (i = 0; i < num_frame; i++) { in mtk_xdp_xmit()
2027 u64 addr64 = 0; in mtk_poll_rx()
2030 int done = 0, bytes = 0; in mtk_poll_rx()
2032 int ppe_idx = 0; in mtk_poll_rx()
2038 int mac = 0; in mtk_poll_rx()
2071 if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || in mtk_poll_rx()
2169 skb_set_hash(skb, jhash_1word(hash, 0), in mtk_poll_rx()
2176 skb_set_hash(skb, jhash_1word(hash, 0), in mtk_poll_rx()
2192 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); in mtk_poll_rx()
2202 skb_record_rx_queue(skb, 0); in mtk_poll_rx()
2301 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) in mtk_poll_tx_qdma()
2351 mtk_poll_tx_done(eth, state, 0, tx_buf->data); in mtk_poll_tx_pdma()
2409 int tx_done = 0; in mtk_napi_tx()
2418 "done tx %d, intr 0x%08x/0x%x\n", tx_done, in mtk_napi_tx()
2439 int rx_done_total = 0; in mtk_napi_rx()
2453 "done rx %d, intr 0x%08x/0x%x\n", rx_done, in mtk_napi_rx()
2500 for (i = 0; i < ring_size; i++) { in mtk_tx_alloc()
2507 txd->txd4 = 0; in mtk_tx_alloc()
2509 txd->txd5 = 0; in mtk_tx_alloc()
2510 txd->txd6 = 0; in mtk_tx_alloc()
2511 txd->txd7 = 0; in mtk_tx_alloc()
2512 txd->txd8 = 0; in mtk_tx_alloc()
2526 for (i = 0; i < ring_size; i++) { in mtk_tx_alloc()
2528 ring->dma_pdma[i].txd4 = 0; in mtk_tx_alloc()
2552 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { in mtk_tx_alloc()
2573 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); in mtk_tx_alloc()
2577 return 0; in mtk_tx_alloc()
2590 for (i = 0; i < ring->dma_size; i++) in mtk_tx_clean()
2674 for (i = 0; i < rx_dma_size; i++) { in mtk_rx_alloc()
2714 rxd->rxd3 = 0; in mtk_rx_alloc()
2715 rxd->rxd4 = 0; in mtk_rx_alloc()
2717 rxd->rxd5 = 0; in mtk_rx_alloc()
2718 rxd->rxd6 = 0; in mtk_rx_alloc()
2719 rxd->rxd7 = 0; in mtk_rx_alloc()
2720 rxd->rxd8 = 0; in mtk_rx_alloc()
2755 return 0; in mtk_rx_alloc()
2760 u64 addr64 = 0; in mtk_rx_clean()
2764 for (i = 0; i < ring->dma_size; i++) { in mtk_rx_clean()
2803 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; in mtk_hwlro_rx_init()
2804 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; in mtk_hwlro_rx_init()
2846 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); in mtk_hwlro_rx_init()
2857 return 0; in mtk_hwlro_rx_init()
2869 for (i = 0; i < 10; i++) { in mtk_hwlro_rx_uninit()
2880 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); in mtk_hwlro_rx_uninit()
2883 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); in mtk_hwlro_rx_uninit()
2910 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); in mtk_hwlro_inval_ipaddr()
2915 int cnt = 0; in mtk_hwlro_get_ip_cnt()
2918 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { in mtk_hwlro_get_ip_cnt()
2947 return 0; in mtk_hwlro_add_ipaddr()
2962 mac->hwlro_ip[fsp->location] = 0; in mtk_hwlro_del_ipaddr()
2969 return 0; in mtk_hwlro_del_ipaddr()
2978 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { in mtk_hwlro_netdev_disable()
2979 mac->hwlro_ip[i] = 0; in mtk_hwlro_netdev_disable()
2985 mac->hwlro_ip_cnt = 0; in mtk_hwlro_netdev_disable()
3001 fsp->m_u.tcp_ip4_spec.ip4dst = 0; in mtk_hwlro_get_fdir_entry()
3003 fsp->h_u.tcp_ip4_spec.ip4src = 0; in mtk_hwlro_get_fdir_entry()
3004 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; in mtk_hwlro_get_fdir_entry()
3005 fsp->h_u.tcp_ip4_spec.psrc = 0; in mtk_hwlro_get_fdir_entry()
3006 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; in mtk_hwlro_get_fdir_entry()
3007 fsp->h_u.tcp_ip4_spec.pdst = 0; in mtk_hwlro_get_fdir_entry()
3008 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; in mtk_hwlro_get_fdir_entry()
3009 fsp->h_u.tcp_ip4_spec.tos = 0; in mtk_hwlro_get_fdir_entry()
3010 fsp->m_u.tcp_ip4_spec.tos = 0xff; in mtk_hwlro_get_fdir_entry()
3012 return 0; in mtk_hwlro_get_fdir_entry()
3020 int cnt = 0; in mtk_hwlro_get_fdir_all()
3023 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { in mtk_hwlro_get_fdir_all()
3035 return 0; in mtk_hwlro_get_fdir_all()
3062 return 0; in mtk_set_features()
3108 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); in mtk_dma_init()
3113 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); in mtk_dma_init()
3134 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); in mtk_dma_init()
3137 return 0; in mtk_dma_init()
3145 for (i = 0; i < MTK_MAX_DEVS; i++) in mtk_dma_free()
3153 eth->phy_scratch_ring = 0; in mtk_dma_free()
3156 mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM)); in mtk_dma_free()
3165 for (i = 0; i < DIV_ROUND_UP(soc->tx.fq_dma_size, MTK_FQ_DMA_LENGTH); i++) { in mtk_dma_free()
3258 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; in mtk_start_dma()
3292 return 0; in mtk_start_dma()
3305 val &= ~0xffff; in mtk_gdm_config()
3356 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) in mtk_device_event()
3363 if (mac->speed > 0 && mac->speed <= s.base.speed) in mtk_device_event()
3364 s.base.speed = 0; in mtk_device_event()
3380 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); in mtk_open()
3399 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_open()
3402 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_open()
3408 target_mac->ppe_idx = 0; in mtk_open()
3417 target_mac->ppe_idx = 0; in mtk_open()
3418 gdm_config = soc->reg_map->gdma_to_ppe[0]; in mtk_open()
3424 mtk_w32(eth, 0, MTK_RST_GL); in mtk_open()
3439 return 0; in mtk_open()
3442 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_open()
3448 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, in mtk_open()
3465 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); in mtk_open()
3468 return 0; in mtk_open()
3484 for (i = 0; i < 10; i++) { in mtk_stop_dma()
3508 return 0; in mtk_stop()
3510 for (i = 0; i < MTK_MAX_DEVS; i++) in mtk_stop()
3527 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_stop()
3530 return 0; in mtk_stop()
3562 return 0; in mtk_xdp_setup()
3592 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) in mtk_clk_disable()
3600 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { in mtk_clk_enable()
3606 return 0; in mtk_clk_enable()
3609 while (--clk >= 0) in mtk_clk_enable()
3706 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3731 0x6f8ff); in mtk_hw_reset()
3734 0x3ffffff); in mtk_hw_reset()
3806 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); in mtk_hw_check_dma_hang()
3808 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); in mtk_hw_check_dma_hang()
3811 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); in mtk_hw_check_dma_hang()
3815 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && in mtk_hw_check_dma_hang()
3816 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); in mtk_hw_check_dma_hang()
3820 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
3827 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); in mtk_hw_check_dma_hang()
3828 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); in mtk_hw_check_dma_hang()
3830 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; in mtk_hw_check_dma_hang()
3831 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; in mtk_hw_check_dma_hang()
3832 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; in mtk_hw_check_dma_hang()
3834 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); in mtk_hw_check_dma_hang()
3835 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); in mtk_hw_check_dma_hang()
3841 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
3848 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); in mtk_hw_check_dma_hang()
3850 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && in mtk_hw_check_dma_hang()
3855 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
3861 eth->reset.wdma_hang_count = 0; in mtk_hw_check_dma_hang()
3862 eth->reset.qdma_hang_count = 0; in mtk_hw_check_dma_hang()
3863 eth->reset.adma_hang_count = 0; in mtk_hw_check_dma_hang()
3896 return 0; in mtk_hw_init()
3923 mtk_tx_irq_disable(eth, ~0); in mtk_hw_init()
3924 mtk_rx_irq_disable(eth, ~0); in mtk_hw_init()
3926 return 0; in mtk_hw_init()
3948 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); in mtk_hw_init()
3951 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); in mtk_hw_init()
3954 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); in mtk_hw_init()
3961 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_hw_init()
3989 mtk_tx_irq_disable(eth, ~0); in mtk_hw_init()
3990 mtk_rx_irq_disable(eth, ~0); in mtk_hw_init()
3997 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); in mtk_hw_init()
4001 mtk_w32(eth, 0x00000302, PSE_DROP_CFG); in mtk_hw_init()
4004 mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); in mtk_hw_init()
4005 mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); in mtk_hw_init()
4008 mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); in mtk_hw_init()
4014 for (i = 0; i < 0x80; i += 0x4) in mtk_hw_init()
4015 mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); in mtk_hw_init()
4018 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); in mtk_hw_init()
4021 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); in mtk_hw_init()
4024 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); in mtk_hw_init()
4027 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); in mtk_hw_init()
4028 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); in mtk_hw_init()
4029 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); in mtk_hw_init()
4030 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); in mtk_hw_init()
4031 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); in mtk_hw_init()
4032 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); in mtk_hw_init()
4033 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); in mtk_hw_init()
4034 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); in mtk_hw_init()
4037 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); in mtk_hw_init()
4038 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); in mtk_hw_init()
4039 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); in mtk_hw_init()
4040 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); in mtk_hw_init()
4041 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); in mtk_hw_init()
4042 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); in mtk_hw_init()
4043 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); in mtk_hw_init()
4044 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); in mtk_hw_init()
4047 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); in mtk_hw_init()
4048 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); in mtk_hw_init()
4049 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); in mtk_hw_init()
4050 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); in mtk_hw_init()
4051 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); in mtk_hw_init()
4052 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); in mtk_hw_init()
4055 return 0; in mtk_hw_init()
4069 return 0; in mtk_hw_deinit()
4076 return 0; in mtk_hw_deinit()
4085 mtk_tx_irq_disable(eth, ~0); in mtk_uninit()
4086 mtk_rx_irq_disable(eth, ~0); in mtk_uninit()
4104 return 0; in mtk_change_mtu()
4141 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) in mtk_prepare_for_reset()
4145 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); in mtk_prepare_for_reset()
4148 for (i = 0; i < 2; i++) { in mtk_prepare_for_reset()
4157 unsigned long restart = 0; in mtk_pending_work()
4172 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_pending_work()
4188 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_pending_work()
4223 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_free_dev()
4229 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { in mtk_free_dev()
4235 return 0; in mtk_free_dev()
4242 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_unreg_dev()
4252 return 0; in mtk_unreg_dev()
4259 for (i = 0; i < MTK_MAX_DEVS; i++) in mtk_sgmii_destroy()
4271 return 0; in mtk_cleanup()
4341 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) in mtk_get_strings()
4373 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { in mtk_ethtool_pp_stats()
4409 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) in mtk_get_ethtool_stats()
4425 ret = 0; in mtk_get_rxnfc()
4433 ret = 0; in mtk_get_rxnfc()
4490 unsigned int queue = 0; in mtk_select_queue()
4498 queue = 0; in mtk_select_queue()
4593 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); in mtk_add_mac()
4594 mac->hwlro_ip_cnt = 0; in mtk_add_mac()
4608 mac->hw_stats->reg_offset = id * 0x80; in mtk_add_mac()
4610 mac->hw_stats->reg_offset = id * 0x40; in mtk_add_mac()
4632 if (!mac->hw->soc->disable_pll_modes || mac->id != 0) { in mtk_add_mac()
4699 eth->netdev[id]->irq = eth->irq[0]; in mtk_add_mac()
4718 return 0; in mtk_add_mac()
4733 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_eth_set_dma_device()
4761 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_sgmii_init()
4767 flags = 0; in mtk_sgmii_init()
4781 return 0; in mtk_sgmii_init()
4799 eth->base = devm_platform_ioremap_resource(pdev, 0); in mtk_probe()
4868 regmap_write(cci, 0, 3); in mtk_probe()
4889 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in mtk_probe()
4909 for (i = 0;; i++) { in mtk_probe()
4923 wdma_phy = res ? res->start + wdma_base : 0; in mtk_probe()
4929 for (i = 0; i < 3; i++) { in mtk_probe()
4930 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) in mtk_probe()
4931 eth->irq[i] = eth->irq[0]; in mtk_probe()
4934 if (eth->irq[i] < 0) { in mtk_probe()
4940 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { in mtk_probe()
4983 err = devm_request_irq(eth->dev, eth->irq[0], in mtk_probe()
4984 mtk_handle_irq, 0, in mtk_probe()
4988 mtk_handle_irq_tx, 0, in mtk_probe()
4994 mtk_handle_irq_rx, 0, in mtk_probe()
5011 for (i = 0; i < ppe_num; i++) { in mtk_probe()
5014 ppe_addr += (i == 2 ? 0xc00 : i * 0x400); in mtk_probe()
5028 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_probe()
5038 "mediatek frame engine at 0x%08lx, irq %d\n", in mtk_probe()
5039 eth->netdev[i]->base_addr, eth->irq[0]); in mtk_probe()
5045 eth->dummy_dev = alloc_netdev_dummy(0); in mtk_probe()
5058 return 0; in mtk_probe()
5084 for (i = 0; i < MTK_MAX_DEVS; i++) { in mtk_remove()
5156 .ana_rgc3 = 0x2028,
5215 .ana_rgc3 = 0x128,
5241 .ana_rgc3 = 0x128,
5271 .ana_rgc3 = 0x128,
5301 .ana_rgc3 = 0x128,