292 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)  in mtk_w32()
304 	u32 val;  in mtk_m32()  local
447 			      int phy_reg, u16 val)  in mtk_mdio_write_c22()
455 			      int devad, int phy_reg, u16 val)  in mtk_mdio_write_c45()
480 	u32 val;  in mt7621_gmac0_rgmii_adjust()  local
545 	int val, ge_mode, err = 0;  in mtk_mac_config()  local
713 	u32 ofs, val;  in mtk_set_queue_speed()  local
828 	u32 val;  in mtk_mdio_config()  local
847 	u32 val;  in mtk_mdio_init()  local
905 	u32 val;  in mtk_tx_irq_disable()  local
916 	u32 val;  in mtk_tx_irq_enable()  local
927 	u32 val;  in mtk_rx_irq_disable()  local
938 	u32 val;  in mtk_rx_irq_enable()  local
1061 			    struct rtnl_link_stats64 *storage)  in mtk_get_stats64()
2053 			u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);  in mtk_poll_rx()  local
2477 	u32 ofs, val;  in mtk_tx_alloc()  local
2863 	u32 val;  in mtk_hwlro_rx_uninit()  local
3070 	u32 val;  in mtk_dma_busy_wait()  local
3173 	u32 val = mtk_r32(eth, MTK_INT_STATUS2);  in mtk_hw_reset_check()  local
3258 	u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0;  in mtk_start_dma()  local
3297 	u32 val;  in mtk_gdm_config()  local
3460 		u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL);  in mtk_open()  local
3473 	u32 val;  in mtk_stop_dma()  local
3621 	u32 val, cur;  in mtk_dim_rx()  local
3652 	u32 val, cur;  in mtk_dim_tx()  local
3677 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val)  in mtk_set_mcr_max_rx()
3703 	u32 val;  in mtk_hw_reset()  local
3739 	u32 val;  in mtk_hw_reset_read()  local
3747 	u32 rst_mask, val;  in mtk_hw_warm_reset()  local
3798 	u32 wdidx, val, gdm1_fc, gdm2_fc;  in mtk_hw_check_dma_hang()  local
3893 	int i, val, ret;  in mtk_hw_init()  local
4125 	u32 val;  in mtk_prepare_for_reset()  local
4158 	u32 val;  in mtk_pending_work()  local
4550 	u32 val;  in mtk_add_mac()  local