Lines Matching full:pe
22 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
28 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
32 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
35 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
37 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]); in mvpp2_prs_hw_write()
40 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
42 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]); in mvpp2_prs_hw_write()
49 struct mvpp2_prs_entry *pe, int tid) in __mvpp2_prs_init_from_hw() argument
58 memset(pe, 0, sizeof(*pe)); in __mvpp2_prs_init_from_hw()
59 pe->index = tid; in __mvpp2_prs_init_from_hw()
62 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in __mvpp2_prs_init_from_hw()
64 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in __mvpp2_prs_init_from_hw()
66 if (pe->tcam[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in __mvpp2_prs_init_from_hw()
70 pe->tcam[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in __mvpp2_prs_init_from_hw()
73 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in __mvpp2_prs_init_from_hw()
75 pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in __mvpp2_prs_init_from_hw()
80 int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe, in mvpp2_prs_init_from_hw() argument
86 err = __mvpp2_prs_init_from_hw(priv, pe, tid); in mvpp2_prs_init_from_hw()
117 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument
119 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
120 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
121 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU(lu & MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
122 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
126 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_set() argument
130 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(BIT(port)); in mvpp2_prs_tcam_port_set()
132 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(BIT(port)); in mvpp2_prs_tcam_port_set()
136 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_map_set() argument
139 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT(MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
140 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
141 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(~ports & MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
145 unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_port_map_get() argument
147 return (~pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] >> 24) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
151 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_set() argument
157 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(0xff << pos); in mvpp2_prs_tcam_data_byte_set()
158 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(MVPP2_PRS_TCAM_EN(0xff) << pos); in mvpp2_prs_tcam_data_byte_set()
159 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= byte << pos; in mvpp2_prs_tcam_data_byte_set()
160 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= MVPP2_PRS_TCAM_EN(enable << pos); in mvpp2_prs_tcam_data_byte_set()
164 void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_get() argument
170 *byte = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> pos) & 0xff; in mvpp2_prs_tcam_data_byte_get()
171 *enable = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> (pos + 16)) & 0xff; in mvpp2_prs_tcam_data_byte_get()
175 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, in mvpp2_prs_tcam_data_cmp() argument
180 tcam_data = pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] & 0xffff; in mvpp2_prs_tcam_data_cmp()
185 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_ai_update() argument
195 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= BIT(i); in mvpp2_prs_tcam_ai_update()
197 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] &= ~BIT(i); in mvpp2_prs_tcam_ai_update()
200 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= MVPP2_PRS_TCAM_AI_EN(enable); in mvpp2_prs_tcam_ai_update()
204 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_ai_get() argument
206 return pe->tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK; in mvpp2_prs_tcam_ai_get()
210 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_etype() argument
213 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); in mvpp2_prs_match_etype()
214 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); in mvpp2_prs_match_etype()
218 static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_vid() argument
221 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf); in mvpp2_prs_match_vid()
222 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff); in mvpp2_prs_match_vid()
226 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_set() argument
229 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] |= (val << (MVPP2_BIT_IN_WORD(bit_num))); in mvpp2_prs_sram_bits_set()
233 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_clear() argument
236 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] &= ~(val << (MVPP2_BIT_IN_WORD(bit_num))); in mvpp2_prs_sram_bits_clear()
240 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ri_update() argument
250 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_OFFS + i, in mvpp2_prs_sram_ri_update()
253 mvpp2_prs_sram_bits_clear(pe, in mvpp2_prs_sram_ri_update()
257 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ri_update()
262 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ri_get() argument
264 return pe->sram[MVPP2_PRS_SRAM_RI_WORD]; in mvpp2_prs_sram_ri_get()
268 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ai_update() argument
278 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_OFFS + i, in mvpp2_prs_sram_ai_update()
281 mvpp2_prs_sram_bits_clear(pe, in mvpp2_prs_sram_ai_update()
285 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ai_update()
290 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ai_get() argument
297 bits = (pe->sram[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
298 (pe->sram[ai_off + 1] << (32 - ai_shift)); in mvpp2_prs_sram_ai_get()
306 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_next_lu_set() argument
311 mvpp2_prs_sram_bits_clear(pe, sram_next_off, in mvpp2_prs_sram_next_lu_set()
313 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set()
319 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, in mvpp2_prs_sram_shift_set() argument
324 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
327 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
331 pe->sram[MVPP2_BIT_TO_WORD(MVPP2_PRS_SRAM_SHIFT_OFFS)] |= in mvpp2_prs_sram_shift_set()
335 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, in mvpp2_prs_sram_shift_set()
337 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); in mvpp2_prs_sram_shift_set()
340 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_shift_set()
346 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_offset_set() argument
352 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
355 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
359 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
361 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
365 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, in mvpp2_prs_sram_offset_set()
367 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); in mvpp2_prs_sram_offset_set()
370 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
372 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
376 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_offset_set()
382 struct mvpp2_prs_entry pe; in mvpp2_prs_flow_find() local
393 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_flow_find()
394 bits = mvpp2_prs_sram_ai_get(&pe); in mvpp2_prs_flow_find()
425 struct mvpp2_prs_entry pe; in mvpp2_prs_drop_fc() local
428 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_drop_fc()
431 pe.index = MVPP2_PE_FC_DROP; in mvpp2_prs_drop_fc()
432 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_drop_fc()
437 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff); in mvpp2_prs_drop_fc()
439 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_drop_fc()
442 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_drop_fc()
443 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_drop_fc()
446 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_drop_fc()
449 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_drop_fc()
450 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_drop_fc()
456 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_drop_all_set() local
460 __mvpp2_prs_init_from_hw(priv, &pe, MVPP2_PE_DROP_ALL); in mvpp2_prs_mac_drop_all_set()
463 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_drop_all_set()
464 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
465 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
468 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_drop_all_set()
471 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_drop_all_set()
472 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_drop_all_set()
475 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
478 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_drop_all_set()
482 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
484 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_drop_all_set()
492 struct mvpp2_prs_entry pe; in __mvpp2_prs_mac_promisc_set() local
511 __mvpp2_prs_init_from_hw(priv, &pe, tid); in __mvpp2_prs_mac_promisc_set()
513 memset(&pe, 0, sizeof(pe)); in __mvpp2_prs_mac_promisc_set()
514 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in __mvpp2_prs_mac_promisc_set()
515 pe.index = tid; in __mvpp2_prs_mac_promisc_set()
518 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in __mvpp2_prs_mac_promisc_set()
521 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK); in __mvpp2_prs_mac_promisc_set()
524 mvpp2_prs_tcam_data_byte_set(&pe, 0, cast_match, in __mvpp2_prs_mac_promisc_set()
528 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in __mvpp2_prs_mac_promisc_set()
532 mvpp2_prs_tcam_port_map_set(&pe, 0); in __mvpp2_prs_mac_promisc_set()
535 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in __mvpp2_prs_mac_promisc_set()
539 mvpp2_prs_tcam_port_set(&pe, port, add); in __mvpp2_prs_mac_promisc_set()
541 mvpp2_prs_hw_write(priv, &pe); in __mvpp2_prs_mac_promisc_set()
556 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_set() local
569 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_dsa_tag_set()
572 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_tag_set()
573 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
574 pe.index = tid; in mvpp2_prs_dsa_tag_set()
577 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
581 mvpp2_prs_tcam_data_byte_set(&pe, 0, in mvpp2_prs_dsa_tag_set()
587 mvpp2_prs_sram_ai_update(&pe, 1, in mvpp2_prs_dsa_tag_set()
590 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_set()
594 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_dsa_tag_set()
597 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_dsa_tag_set()
600 mvpp2_prs_sram_shift_set(&pe, shift, in mvpp2_prs_dsa_tag_set()
604 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_set()
606 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_set()
610 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_dsa_tag_set()
614 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_set()
616 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_set()
623 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_ethertype_set() local
640 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_dsa_tag_ethertype_set()
643 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_tag_ethertype_set()
644 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
645 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
648 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); in mvpp2_prs_dsa_tag_ethertype_set()
649 mvpp2_prs_match_etype(&pe, 2, 0); in mvpp2_prs_dsa_tag_ethertype_set()
651 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, in mvpp2_prs_dsa_tag_ethertype_set()
654 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, in mvpp2_prs_dsa_tag_ethertype_set()
658 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
662 mvpp2_prs_tcam_data_byte_set(&pe, in mvpp2_prs_dsa_tag_ethertype_set()
667 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_ethertype_set()
670 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_ethertype_set()
673 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_ethertype_set()
675 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_ethertype_set()
678 mvpp2_prs_tcam_port_map_set(&pe, port_mask); in mvpp2_prs_dsa_tag_ethertype_set()
682 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_ethertype_set()
684 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
690 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_find() local
703 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vlan_find()
704 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid); in mvpp2_prs_vlan_find()
709 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_vlan_find()
713 ai_bits = mvpp2_prs_tcam_ai_get(&pe); in mvpp2_prs_vlan_find()
732 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_add() local
736 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_add()
756 __mvpp2_prs_init_from_hw(priv, &pe, tid_aux); in mvpp2_prs_vlan_add()
757 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_vlan_add()
766 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_add()
767 pe.index = tid; in mvpp2_prs_vlan_add()
768 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
770 mvpp2_prs_match_etype(&pe, 0, tpid); in mvpp2_prs_vlan_add()
773 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vlan_add()
776 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
779 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_vlan_add()
783 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_TRIPLE, in mvpp2_prs_vlan_add()
786 mvpp2_prs_tcam_ai_update(&pe, ai, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
788 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
790 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vlan_add()
793 mvpp2_prs_tcam_port_map_set(&pe, port_map); in mvpp2_prs_vlan_add()
795 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_add()
817 struct mvpp2_prs_entry pe; in mvpp2_prs_double_vlan_find() local
830 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_double_vlan_find()
832 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid1) && in mvpp2_prs_double_vlan_find()
833 mvpp2_prs_tcam_data_cmp(&pe, 4, tpid2); in mvpp2_prs_double_vlan_find()
838 ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK; in mvpp2_prs_double_vlan_find()
852 struct mvpp2_prs_entry pe; in mvpp2_prs_double_vlan_add() local
854 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_double_vlan_add()
879 __mvpp2_prs_init_from_hw(priv, &pe, tid_aux); in mvpp2_prs_double_vlan_add()
880 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_double_vlan_add()
890 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_double_vlan_add()
891 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
892 pe.index = tid; in mvpp2_prs_double_vlan_add()
896 mvpp2_prs_match_etype(&pe, 0, tpid1); in mvpp2_prs_double_vlan_add()
897 mvpp2_prs_match_etype(&pe, 4, tpid2); in mvpp2_prs_double_vlan_add()
899 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
901 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_double_vlan_add()
903 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_double_vlan_add()
905 mvpp2_prs_sram_ai_update(&pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_double_vlan_add()
908 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
910 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_double_vlan_add()
914 mvpp2_prs_tcam_port_map_set(&pe, port_map); in mvpp2_prs_double_vlan_add()
915 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_double_vlan_add()
924 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_proto() local
937 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_proto()
938 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
939 pe.index = tid; in mvpp2_prs_ip4_proto()
942 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_proto()
943 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_proto()
946 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4, in mvpp2_prs_ip4_proto()
948 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_proto()
949 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); in mvpp2_prs_ip4_proto()
951 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, in mvpp2_prs_ip4_proto()
953 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, in mvpp2_prs_ip4_proto()
956 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
957 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_proto()
960 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_proto()
963 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
964 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
972 pe.index = tid; in mvpp2_prs_ip4_proto()
974 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_ip4_proto()
975 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_ip4_proto()
976 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip4_proto()
978 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE, in mvpp2_prs_ip4_proto()
981 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0); in mvpp2_prs_ip4_proto()
982 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0); in mvpp2_prs_ip4_proto()
985 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
986 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
994 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_cast() local
1002 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_cast()
1003 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
1004 pe.index = tid; in mvpp2_prs_ip4_cast()
1008 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, in mvpp2_prs_ip4_cast()
1010 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip4_cast()
1015 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); in mvpp2_prs_ip4_cast()
1016 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); in mvpp2_prs_ip4_cast()
1017 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); in mvpp2_prs_ip4_cast()
1018 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); in mvpp2_prs_ip4_cast()
1019 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, in mvpp2_prs_ip4_cast()
1027 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
1029 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_cast()
1033 mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_cast()
1035 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_cast()
1038 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_cast()
1041 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
1042 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_cast()
1051 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_proto() local
1063 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_proto()
1064 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
1065 pe.index = tid; in mvpp2_prs_ip6_proto()
1068 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_proto()
1069 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_proto()
1070 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip6_proto()
1071 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_proto()
1075 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip6_proto()
1076 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_proto()
1079 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_proto()
1082 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
1083 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_proto()
1091 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_cast() local
1102 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_cast()
1103 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1104 pe.index = tid; in mvpp2_prs_ip6_cast()
1107 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1108 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip6_cast()
1110 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_cast()
1113 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_cast()
1115 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, in mvpp2_prs_ip6_cast()
1117 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_cast()
1119 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_cast()
1122 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1123 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_cast()
1158 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow_init() local
1162 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_def_flow_init()
1163 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1164 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1167 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_def_flow_init()
1170 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
1171 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow_init()
1174 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1175 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_def_flow_init()
1182 struct mvpp2_prs_entry pe; in mvpp2_prs_mh_init() local
1184 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mh_init()
1186 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
1187 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1188 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
1190 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mh_init()
1193 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mh_init()
1196 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1197 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
1200 pe.index = MVPP2_PE_MH_SKIP_PRS; in mvpp2_prs_mh_init()
1201 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1202 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
1204 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mh_init()
1205 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mh_init()
1208 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mh_init()
1211 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1212 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
1220 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_init() local
1222 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_init()
1225 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
1226 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1228 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_init()
1230 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_init()
1231 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_init()
1234 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mac_init()
1237 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1238 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_init()
1250 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_init() local
1283 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_init()
1284 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_init()
1285 pe.index = MVPP2_PE_DSA_DEFAULT; in mvpp2_prs_dsa_init()
1286 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_init()
1289 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_dsa_init()
1290 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_dsa_init()
1293 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_dsa_init()
1296 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_dsa_init()
1298 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_init()
1304 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_init() local
1306 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_init()
1309 pe.index = MVPP2_PE_VID_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1310 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1312 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT); in mvpp2_prs_vid_init()
1315 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_vid_init()
1319 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_init()
1321 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_init()
1324 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vid_init()
1327 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1328 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_init()
1331 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_init()
1334 pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1335 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1337 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT, in mvpp2_prs_vid_init()
1341 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN, in mvpp2_prs_vid_init()
1345 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_init()
1347 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_init()
1350 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vid_init()
1353 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1354 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_init()
1360 struct mvpp2_prs_entry pe; in mvpp2_prs_etype_init() local
1369 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1370 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1371 pe.index = tid; in mvpp2_prs_etype_init()
1373 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); in mvpp2_prs_etype_init()
1375 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, in mvpp2_prs_etype_init()
1377 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_etype_init()
1378 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
1382 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1383 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1384 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1385 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
1387 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1395 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1396 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1397 pe.index = tid; in mvpp2_prs_etype_init()
1399 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); in mvpp2_prs_etype_init()
1402 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1403 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1404 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
1407 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1412 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1413 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1414 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1415 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
1417 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1425 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1426 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1427 pe.index = tid; in mvpp2_prs_etype_init()
1429 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); in mvpp2_prs_etype_init()
1432 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1433 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1434 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1439 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1444 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1445 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1446 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1447 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1451 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1460 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1461 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1462 pe.index = tid; in mvpp2_prs_etype_init()
1464 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); in mvpp2_prs_etype_init()
1465 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
1470 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_etype_init()
1471 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
1474 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + in mvpp2_prs_etype_init()
1478 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_etype_init()
1483 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1484 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1485 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1486 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
1488 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1497 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1498 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1499 pe.index = tid; in mvpp2_prs_etype_init()
1501 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); in mvpp2_prs_etype_init()
1504 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_etype_init()
1507 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_etype_init()
1508 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
1511 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1515 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1516 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1517 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1518 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
1520 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1523 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
1524 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1525 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
1528 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_etype_init()
1531 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1532 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1533 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
1536 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1541 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1542 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1543 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1544 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
1546 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1560 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_init() local
1588 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_init()
1589 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1590 pe.index = MVPP2_PE_VLAN_DBL; in mvpp2_prs_vlan_init()
1592 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vlan_init()
1595 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_init()
1596 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_vlan_init()
1599 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_vlan_init()
1602 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
1605 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1606 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
1609 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_init()
1610 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1611 pe.index = MVPP2_PE_VLAN_NONE; in mvpp2_prs_vlan_init()
1613 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
1614 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_vlan_init()
1618 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
1621 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1622 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
1630 struct mvpp2_prs_entry pe; in mvpp2_prs_pppoe_init() local
1640 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1641 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1642 pe.index = tid; in mvpp2_prs_pppoe_init()
1644 mvpp2_prs_match_etype(&pe, 0, PPP_IP); in mvpp2_prs_pppoe_init()
1645 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_pppoe_init()
1650 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_pppoe_init()
1651 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_pppoe_init()
1654 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + in mvpp2_prs_pppoe_init()
1658 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1662 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_pppoe_init()
1667 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1668 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1677 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1678 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1679 pe.index = tid; in mvpp2_prs_pppoe_init()
1681 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); in mvpp2_prs_pppoe_init()
1683 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_pppoe_init()
1684 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_pppoe_init()
1687 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_pppoe_init()
1691 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1696 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1697 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1705 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1706 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1707 pe.index = tid; in mvpp2_prs_pppoe_init()
1709 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_pppoe_init()
1713 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_pppoe_init()
1714 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_pppoe_init()
1716 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1721 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1722 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1730 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_init() local
1763 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_init()
1764 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1765 pe.index = MVPP2_PE_IP4_PROTO_UN; in mvpp2_prs_ip4_init()
1768 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_init()
1769 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_init()
1772 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4, in mvpp2_prs_ip4_init()
1774 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_init()
1775 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip4_init()
1778 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
1781 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
1784 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1785 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
1788 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_init()
1789 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1790 pe.index = MVPP2_PE_IP4_ADDR_UN; in mvpp2_prs_ip4_init()
1793 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1795 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
1799 mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_init()
1801 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip4_init()
1803 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_init()
1806 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
1809 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1810 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
1818 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_init() local
1861 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_init()
1862 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1863 pe.index = tid; in mvpp2_prs_ip6_init()
1866 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1867 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1868 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | in mvpp2_prs_ip6_init()
1873 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); in mvpp2_prs_ip6_init()
1874 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1878 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1879 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1882 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_init()
1883 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1884 pe.index = MVPP2_PE_IP6_PROTO_UN; in mvpp2_prs_ip6_init()
1887 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1888 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1889 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
1892 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_init()
1896 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1899 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1902 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1903 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1906 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
1907 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1908 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; in mvpp2_prs_ip6_init()
1911 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1912 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1913 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
1916 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1919 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1922 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1923 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1926 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
1927 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1928 pe.index = MVPP2_PE_IP6_ADDR_UN; in mvpp2_prs_ip6_init()
1931 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1932 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip6_init()
1934 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1937 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_init()
1939 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_init()
1941 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1944 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1945 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1954 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_range_find() local
1965 __mvpp2_prs_init_from_hw(port->priv, &pe, tid); in mvpp2_prs_vid_range_find()
1967 mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]); in mvpp2_prs_vid_range_find()
1968 mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]); in mvpp2_prs_vid_range_find()
1989 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_entry_add() local
1992 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_entry_add()
2019 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_entry_add()
2020 pe.index = tid; in mvpp2_prs_vid_entry_add()
2023 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_vid_entry_add()
2025 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vid_entry_add()
2029 mvpp2_prs_tcam_port_set(&pe, port->id, true); in mvpp2_prs_vid_entry_add()
2032 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_entry_add()
2035 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_vid_entry_add()
2038 mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid); in mvpp2_prs_vid_entry_add()
2041 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_entry_add()
2044 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_entry_add()
2045 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_entry_add()
2110 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_enable_filtering() local
2115 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_enable_filtering()
2119 pe.index = tid; in mvpp2_prs_vid_enable_filtering()
2127 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_enable_filtering()
2130 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_vid_enable_filtering()
2133 mvpp2_prs_tcam_port_set(&pe, port->id, true); in mvpp2_prs_vid_enable_filtering()
2136 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_enable_filtering()
2139 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_vid_enable_filtering()
2142 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_vid_enable_filtering()
2146 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_enable_filtering()
2149 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_enable_filtering()
2150 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_enable_filtering()
2218 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, in mvpp2_prs_mac_range_equals() argument
2225 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
2241 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_da_range_find() local
2254 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_da_range_find()
2255 entry_pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_da_range_find()
2257 if (mvpp2_prs_mac_range_equals(&pe, da, mask) && in mvpp2_prs_mac_da_range_find()
2272 struct mvpp2_prs_entry pe; in __mvpp2_prs_mac_da_accept() local
2275 memset(&pe, 0, sizeof(pe)); in __mvpp2_prs_mac_da_accept()
2294 pe.index = tid; in __mvpp2_prs_mac_da_accept()
2297 mvpp2_prs_tcam_port_map_set(&pe, 0); in __mvpp2_prs_mac_da_accept()
2299 __mvpp2_prs_init_from_hw(priv, &pe, tid); in __mvpp2_prs_mac_da_accept()
2302 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in __mvpp2_prs_mac_da_accept()
2305 mvpp2_prs_tcam_port_set(&pe, port->id, add); in __mvpp2_prs_mac_da_accept()
2308 pmap = mvpp2_prs_tcam_port_map_get(&pe); in __mvpp2_prs_mac_da_accept()
2313 mvpp2_prs_hw_inv(priv, pe.index); in __mvpp2_prs_mac_da_accept()
2314 priv->prs_shadow[pe.index].valid = false; in __mvpp2_prs_mac_da_accept()
2319 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in __mvpp2_prs_mac_da_accept()
2324 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff); in __mvpp2_prs_mac_da_accept()
2338 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | in __mvpp2_prs_mac_da_accept()
2340 mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in __mvpp2_prs_mac_da_accept()
2344 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in __mvpp2_prs_mac_da_accept()
2348 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF; in __mvpp2_prs_mac_da_accept()
2349 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in __mvpp2_prs_mac_da_accept()
2350 mvpp2_prs_hw_write(priv, &pe); in __mvpp2_prs_mac_da_accept()
2390 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_del_all() local
2405 __mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_del_all()
2407 pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_del_all()
2415 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], in mvpp2_prs_mac_del_all()
2490 struct mvpp2_prs_entry pe; in mvpp2_prs_add_flow() local
2494 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_add_flow()
2506 pe.index = tid; in mvpp2_prs_add_flow()
2511 mvpp2_prs_sram_ai_update(&pe, flow, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_add_flow()
2512 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_add_flow()
2515 mvpp2_prs_tcam_data_byte_set(&pe, i, ri_byte[i], in mvpp2_prs_add_flow()
2519 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_add_flow()
2520 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_add_flow()
2521 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_add_flow()
2522 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_add_flow()
2531 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow() local
2534 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_def_flow()
2551 pe.index = tid; in mvpp2_prs_def_flow()
2554 mvpp2_prs_sram_ai_update(&pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2555 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow()
2558 mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2560 __mvpp2_prs_init_from_hw(port->priv, &pe, tid); in mvpp2_prs_def_flow()
2563 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2564 mvpp2_prs_tcam_port_map_set(&pe, (1 << port->id)); in mvpp2_prs_def_flow()
2565 mvpp2_prs_hw_write(port->priv, &pe); in mvpp2_prs_def_flow()