Lines Matching full:port
61 static void mvpp2_acpi_start(struct mvpp2_port *port);
182 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, in mvpp2_txdesc_dma_addr_get() argument
185 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_dma_addr_get()
192 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, in mvpp2_txdesc_dma_addr_set() argument
201 if (port->priv->hw_version == MVPP21) { in mvpp2_txdesc_dma_addr_set()
213 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, in mvpp2_txdesc_size_get() argument
216 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_get()
222 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, in mvpp2_txdesc_size_set() argument
226 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_set()
232 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, in mvpp2_txdesc_txq_set() argument
236 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_txq_set()
242 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, in mvpp2_txdesc_cmd_set() argument
246 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_cmd_set()
252 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, in mvpp2_txdesc_offset_get() argument
255 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_offset_get()
261 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, in mvpp2_rxdesc_dma_addr_get() argument
264 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_dma_addr_get()
271 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, in mvpp2_rxdesc_cookie_get() argument
274 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_cookie_get()
281 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, in mvpp2_rxdesc_size_get() argument
284 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_size_get()
290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, in mvpp2_rxdesc_status_get() argument
293 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_status_get()
306 static void mvpp2_txq_inc_put(struct mvpp2_port *port, in mvpp2_txq_inc_put() argument
319 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); in mvpp2_txq_inc_put()
320 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + in mvpp2_txq_inc_put()
321 mvpp2_txdesc_offset_get(port, tx_desc); in mvpp2_txq_inc_put()
347 /* Get number of physical egress port */
348 static inline int mvpp2_egress_port(struct mvpp2_port *port) in mvpp2_egress_port() argument
350 return MVPP2_MAX_TCONT + port->id; in mvpp2_egress_port()
354 static inline int mvpp2_txq_phys(int port, int txq) in mvpp2_txq_phys() argument
356 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; in mvpp2_txq_phys()
640 struct mvpp2_port *port; in mvpp2_bm_init() local
651 port = priv->port_list[i]; in mvpp2_bm_init()
652 if (port->xdp_prog) { in mvpp2_bm_init()
720 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, in mvpp2_rxq_long_pool_set() argument
727 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_long_pool_set()
729 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_long_pool_set()
734 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
737 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
741 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, in mvpp2_rxq_short_pool_set() argument
748 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_short_pool_set()
750 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_short_pool_set()
755 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_short_pool_set()
758 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_short_pool_set()
761 static void *mvpp2_buf_alloc(struct mvpp2_port *port, in mvpp2_buf_alloc() argument
781 dma_addr = dma_map_single(port->dev->dev.parent, data, in mvpp2_buf_alloc()
784 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { in mvpp2_buf_alloc()
796 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port) in mvpp2_rxq_enable_fc() argument
799 int fq = port->first_rxq; in mvpp2_rxq_enable_fc()
802 spin_lock_irqsave(&port->priv->mss_spinlock, flags); in mvpp2_rxq_enable_fc()
807 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_enable_fc()
810 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_enable_fc()
813 for (q = 0; q < port->nrxqs; q++) { in mvpp2_rxq_enable_fc()
817 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); in mvpp2_rxq_enable_fc()
819 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); in mvpp2_rxq_enable_fc()
820 /* Set RXQ port ID */ in mvpp2_rxq_enable_fc()
822 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq)); in mvpp2_rxq_enable_fc()
834 host_id = port->nqvecs; in mvpp2_rxq_enable_fc()
844 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); in mvpp2_rxq_enable_fc()
848 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_enable_fc()
851 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_enable_fc()
853 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); in mvpp2_rxq_enable_fc()
857 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port) in mvpp2_rxq_disable_fc() argument
861 int fq = port->first_rxq; in mvpp2_rxq_disable_fc()
863 spin_lock_irqsave(&port->priv->mss_spinlock, flags); in mvpp2_rxq_disable_fc()
868 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_disable_fc()
871 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_disable_fc()
874 for (q = 0; q < port->nrxqs; q++) { in mvpp2_rxq_disable_fc()
878 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); in mvpp2_rxq_disable_fc()
880 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); in mvpp2_rxq_disable_fc()
887 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); in mvpp2_rxq_disable_fc()
891 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_disable_fc()
894 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_disable_fc()
896 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); in mvpp2_rxq_disable_fc()
900 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port, in mvpp2_bm_pool_update_fc() argument
907 spin_lock_irqsave(&port->priv->mss_spinlock, flags); in mvpp2_bm_pool_update_fc()
912 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_bm_pool_update_fc()
915 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_bm_pool_update_fc()
919 /* Set BM pool start and stop thresholds per port */ in mvpp2_bm_pool_update_fc()
920 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); in mvpp2_bm_pool_update_fc()
921 val |= MSS_BUF_POOL_PORT_OFFS(port->id); in mvpp2_bm_pool_update_fc()
926 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); in mvpp2_bm_pool_update_fc()
928 /* Remove BM pool from the port */ in mvpp2_bm_pool_update_fc()
929 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); in mvpp2_bm_pool_update_fc()
930 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id); in mvpp2_bm_pool_update_fc()
933 * flow control if pool empty (not used by any port) in mvpp2_bm_pool_update_fc()
940 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); in mvpp2_bm_pool_update_fc()
944 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_bm_pool_update_fc()
947 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_bm_pool_update_fc()
949 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); in mvpp2_bm_pool_update_fc()
955 struct mvpp2_port *port; in mvpp2_bm_pool_update_priv_fc() local
959 port = priv->port_list[i]; in mvpp2_bm_pool_update_priv_fc()
960 if (port->priv->percpu_pools) { in mvpp2_bm_pool_update_priv_fc()
961 for (j = 0; j < port->nrxqs; j++) in mvpp2_bm_pool_update_priv_fc()
962 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[j], in mvpp2_bm_pool_update_priv_fc()
963 port->tx_fc & en); in mvpp2_bm_pool_update_priv_fc()
965 mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en); in mvpp2_bm_pool_update_priv_fc()
966 mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en); in mvpp2_bm_pool_update_priv_fc()
976 * flow control enabled, but still disabled per port. in mvpp2_enable_global_fc()
1000 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_put() argument
1004 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_bm_pool_put()
1007 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_bm_pool_put()
1008 spin_lock_irqsave(&port->bm_lock[thread], flags); in mvpp2_bm_pool_put()
1010 if (port->priv->hw_version >= MVPP22) { in mvpp2_bm_pool_put()
1022 mvpp2_thread_write_relaxed(port->priv, thread, in mvpp2_bm_pool_put()
1031 mvpp2_thread_write_relaxed(port->priv, thread, in mvpp2_bm_pool_put()
1033 mvpp2_thread_write_relaxed(port->priv, thread, in mvpp2_bm_pool_put()
1036 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_bm_pool_put()
1037 spin_unlock_irqrestore(&port->bm_lock[thread], flags); in mvpp2_bm_pool_put()
1043 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, in mvpp2_bm_bufs_add() argument
1052 if (port->priv->percpu_pools && in mvpp2_bm_bufs_add()
1054 netdev_err(port->dev, in mvpp2_bm_bufs_add()
1064 netdev_err(port->dev, in mvpp2_bm_bufs_add()
1070 if (port->priv->percpu_pools) in mvpp2_bm_bufs_add()
1071 pp = port->priv->page_pool[bm_pool->id]; in mvpp2_bm_bufs_add()
1073 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr, in mvpp2_bm_bufs_add()
1078 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, in mvpp2_bm_bufs_add()
1085 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
1089 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
1099 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) in mvpp2_bm_pool_use() argument
1101 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use()
1104 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) || in mvpp2_bm_pool_use()
1105 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) { in mvpp2_bm_pool_use()
1106 netdev_err(port->dev, "Invalid pool %d\n", pool); in mvpp2_bm_pool_use()
1121 if (port->priv->percpu_pools) { in mvpp2_bm_pool_use()
1122 if (pool < port->nrxqs) in mvpp2_bm_pool_use()
1130 mvpp2_bm_bufs_free(port->dev->dev.parent, in mvpp2_bm_pool_use()
1131 port->priv, new_pool, pkts_num); in mvpp2_bm_pool_use()
1140 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use()
1148 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, in mvpp2_bm_pool_use()
1155 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type, in mvpp2_bm_pool_use_percpu() argument
1158 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use_percpu()
1161 if (pool > port->nrxqs * 2) { in mvpp2_bm_pool_use_percpu()
1162 netdev_err(port->dev, "Invalid pool %d\n", pool); in mvpp2_bm_pool_use_percpu()
1179 mvpp2_bm_bufs_free(port->dev->dev.parent, in mvpp2_bm_pool_use_percpu()
1180 port->priv, new_pool, pkts_num); in mvpp2_bm_pool_use_percpu()
1188 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use_percpu()
1196 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, in mvpp2_bm_pool_use_percpu()
1203 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init_shared() argument
1208 /* If port pkt_size is higher than 1518B: in mvpp2_swf_bm_pool_init_shared()
1212 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { in mvpp2_swf_bm_pool_init_shared()
1220 if (!port->pool_long) { in mvpp2_swf_bm_pool_init_shared()
1221 port->pool_long = in mvpp2_swf_bm_pool_init_shared()
1222 mvpp2_bm_pool_use(port, long_log_pool, in mvpp2_swf_bm_pool_init_shared()
1224 if (!port->pool_long) in mvpp2_swf_bm_pool_init_shared()
1227 port->pool_long->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_shared()
1229 for (rxq = 0; rxq < port->nrxqs; rxq++) in mvpp2_swf_bm_pool_init_shared()
1230 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); in mvpp2_swf_bm_pool_init_shared()
1233 if (!port->pool_short) { in mvpp2_swf_bm_pool_init_shared()
1234 port->pool_short = in mvpp2_swf_bm_pool_init_shared()
1235 mvpp2_bm_pool_use(port, short_log_pool, in mvpp2_swf_bm_pool_init_shared()
1237 if (!port->pool_short) in mvpp2_swf_bm_pool_init_shared()
1240 port->pool_short->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_shared()
1242 for (rxq = 0; rxq < port->nrxqs; rxq++) in mvpp2_swf_bm_pool_init_shared()
1243 mvpp2_rxq_short_pool_set(port, rxq, in mvpp2_swf_bm_pool_init_shared()
1244 port->pool_short->id); in mvpp2_swf_bm_pool_init_shared()
1251 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init_percpu() argument
1256 for (i = 0; i < port->nrxqs; i++) { in mvpp2_swf_bm_pool_init_percpu()
1257 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i, in mvpp2_swf_bm_pool_init_percpu()
1262 bm_pool->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_percpu()
1263 mvpp2_rxq_short_pool_set(port, i, bm_pool->id); in mvpp2_swf_bm_pool_init_percpu()
1266 for (i = 0; i < port->nrxqs; i++) { in mvpp2_swf_bm_pool_init_percpu()
1267 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs, in mvpp2_swf_bm_pool_init_percpu()
1272 bm_pool->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_percpu()
1273 mvpp2_rxq_long_pool_set(port, i, bm_pool->id); in mvpp2_swf_bm_pool_init_percpu()
1276 port->pool_long = NULL; in mvpp2_swf_bm_pool_init_percpu()
1277 port->pool_short = NULL; in mvpp2_swf_bm_pool_init_percpu()
1282 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init() argument
1284 if (port->priv->percpu_pools) in mvpp2_swf_bm_pool_init()
1285 return mvpp2_swf_bm_pool_init_percpu(port); in mvpp2_swf_bm_pool_init()
1287 return mvpp2_swf_bm_pool_init_shared(port); in mvpp2_swf_bm_pool_init()
1290 static void mvpp2_set_hw_csum(struct mvpp2_port *port, in mvpp2_set_hw_csum() argument
1295 /* Update L4 checksum when jumbo enable/disable on port. in mvpp2_set_hw_csum()
1296 * Only port 0 supports hardware checksum offload due to in mvpp2_set_hw_csum()
1301 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { in mvpp2_set_hw_csum()
1302 port->dev->features &= ~csums; in mvpp2_set_hw_csum()
1303 port->dev->hw_features &= ~csums; in mvpp2_set_hw_csum()
1305 port->dev->features |= csums; in mvpp2_set_hw_csum()
1306 port->dev->hw_features |= csums; in mvpp2_set_hw_csum()
1312 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_bm_update_mtu() local
1316 if (port->priv->percpu_pools) in mvpp2_bm_update_mtu()
1319 /* If port MTU is higher than 1518B: in mvpp2_bm_update_mtu()
1328 if (new_long_pool != port->pool_long->id) { in mvpp2_bm_update_mtu()
1329 if (port->tx_fc) { in mvpp2_bm_update_mtu()
1331 mvpp2_bm_pool_update_fc(port, in mvpp2_bm_update_mtu()
1332 port->pool_short, in mvpp2_bm_update_mtu()
1335 mvpp2_bm_pool_update_fc(port, port->pool_long, in mvpp2_bm_update_mtu()
1339 /* Remove port from old short & long pool */ in mvpp2_bm_update_mtu()
1340 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, in mvpp2_bm_update_mtu()
1341 port->pool_long->pkt_size); in mvpp2_bm_update_mtu()
1342 port->pool_long->port_map &= ~BIT(port->id); in mvpp2_bm_update_mtu()
1343 port->pool_long = NULL; in mvpp2_bm_update_mtu()
1345 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, in mvpp2_bm_update_mtu()
1346 port->pool_short->pkt_size); in mvpp2_bm_update_mtu()
1347 port->pool_short->port_map &= ~BIT(port->id); in mvpp2_bm_update_mtu()
1348 port->pool_short = NULL; in mvpp2_bm_update_mtu()
1350 port->pkt_size = pkt_size; in mvpp2_bm_update_mtu()
1352 /* Add port to new short & long pool */ in mvpp2_bm_update_mtu()
1353 mvpp2_swf_bm_pool_init(port); in mvpp2_bm_update_mtu()
1355 mvpp2_set_hw_csum(port, new_long_pool); in mvpp2_bm_update_mtu()
1357 if (port->tx_fc) { in mvpp2_bm_update_mtu()
1359 mvpp2_bm_pool_update_fc(port, port->pool_long, in mvpp2_bm_update_mtu()
1362 mvpp2_bm_pool_update_fc(port, port->pool_short, in mvpp2_bm_update_mtu()
1366 /* Update L4 checksum when jumbo enable/disable on port */ in mvpp2_bm_update_mtu()
1367 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { in mvpp2_bm_update_mtu()
1385 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) in mvpp2_interrupts_enable() argument
1389 for (i = 0; i < port->nqvecs; i++) in mvpp2_interrupts_enable()
1390 sw_thread_mask |= port->qvecs[i].sw_thread_mask; in mvpp2_interrupts_enable()
1392 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_enable()
1396 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) in mvpp2_interrupts_disable() argument
1400 for (i = 0; i < port->nqvecs; i++) in mvpp2_interrupts_disable()
1401 sw_thread_mask |= port->qvecs[i].sw_thread_mask; in mvpp2_interrupts_disable()
1403 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_disable()
1409 struct mvpp2_port *port = qvec->port; in mvpp2_qvec_interrupt_enable() local
1411 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_enable()
1417 struct mvpp2_port *port = qvec->port; in mvpp2_qvec_interrupt_disable() local
1419 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_disable()
1429 struct mvpp2_port *port = arg; in mvpp2_interrupts_mask() local
1434 if (cpu > port->priv->nthreads) in mvpp2_interrupts_mask()
1437 thread = mvpp2_cpu_to_thread(port->priv, cpu); in mvpp2_interrupts_mask()
1439 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_mask()
1440 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); in mvpp2_interrupts_mask()
1441 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_mask()
1442 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0); in mvpp2_interrupts_mask()
1451 struct mvpp2_port *port = arg; in mvpp2_interrupts_unmask() local
1456 if (cpu >= port->priv->nthreads) in mvpp2_interrupts_unmask()
1459 thread = mvpp2_cpu_to_thread(port->priv, cpu); in mvpp2_interrupts_unmask()
1462 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); in mvpp2_interrupts_unmask()
1463 if (port->has_tx_irqs) in mvpp2_interrupts_unmask()
1466 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_unmask()
1467 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); in mvpp2_interrupts_unmask()
1468 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_unmask()
1469 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), in mvpp2_interrupts_unmask()
1474 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) in mvpp2_shared_interrupt_mask_unmask() argument
1479 if (port->priv->hw_version == MVPP21) in mvpp2_shared_interrupt_mask_unmask()
1487 for (i = 0; i < port->nqvecs; i++) { in mvpp2_shared_interrupt_mask_unmask()
1488 struct mvpp2_queue_vector *v = port->qvecs + i; in mvpp2_shared_interrupt_mask_unmask()
1493 mvpp2_thread_write(port->priv, v->sw_thread_id, in mvpp2_shared_interrupt_mask_unmask()
1494 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); in mvpp2_shared_interrupt_mask_unmask()
1495 mvpp2_thread_write(port->priv, v->sw_thread_id, in mvpp2_shared_interrupt_mask_unmask()
1496 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), in mvpp2_shared_interrupt_mask_unmask()
1501 /* Only GOP port 0 has an XLG MAC */
1502 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port) in mvpp2_port_supports_xlg() argument
1504 return port->gop_id == 0; in mvpp2_port_supports_xlg()
1507 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port) in mvpp2_port_supports_rgmii() argument
1509 return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0); in mvpp2_port_supports_rgmii()
1512 /* Port configuration routines */
1531 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) in mvpp22_gop_init_rgmii() argument
1533 struct mvpp2 *priv = port->priv; in mvpp22_gop_init_rgmii()
1541 if (port->gop_id == 2) { in mvpp22_gop_init_rgmii()
1543 } else if (port->gop_id == 3) { in mvpp22_gop_init_rgmii()
1551 if (port->phy_interface == PHY_INTERFACE_MODE_MII) in mvpp22_gop_init_rgmii()
1559 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) in mvpp22_gop_init_sgmii() argument
1561 struct mvpp2 *priv = port->priv; in mvpp22_gop_init_sgmii()
1569 if (port->gop_id > 1) { in mvpp22_gop_init_sgmii()
1571 if (port->gop_id == 2) in mvpp22_gop_init_sgmii()
1573 else if (port->gop_id == 3) in mvpp22_gop_init_sgmii()
1579 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) in mvpp22_gop_init_10gkr() argument
1581 struct mvpp2 *priv = port->priv; in mvpp22_gop_init_10gkr()
1582 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); in mvpp22_gop_init_10gkr()
1583 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); in mvpp22_gop_init_10gkr()
1602 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en) in mvpp22_gop_fca_enable_periodic() argument
1604 struct mvpp2 *priv = port->priv; in mvpp22_gop_fca_enable_periodic()
1605 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); in mvpp22_gop_fca_enable_periodic()
1615 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer) in mvpp22_gop_fca_set_timer() argument
1617 struct mvpp2 *priv = port->priv; in mvpp22_gop_fca_set_timer()
1618 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); in mvpp22_gop_fca_set_timer()
1629 * partner won't send traffic if port is in XOFF mode.
1631 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port) in mvpp22_gop_fca_set_periodic_timer() argument
1635 timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER)) in mvpp22_gop_fca_set_periodic_timer()
1638 mvpp22_gop_fca_enable_periodic(port, false); in mvpp22_gop_fca_set_periodic_timer()
1640 mvpp22_gop_fca_set_timer(port, timer); in mvpp22_gop_fca_set_periodic_timer()
1642 mvpp22_gop_fca_enable_periodic(port, true); in mvpp22_gop_fca_set_periodic_timer()
1645 static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface) in mvpp22_gop_init() argument
1647 struct mvpp2 *priv = port->priv; in mvpp22_gop_init()
1659 if (!mvpp2_port_supports_rgmii(port)) in mvpp22_gop_init()
1661 mvpp22_gop_init_rgmii(port); in mvpp22_gop_init()
1666 mvpp22_gop_init_sgmii(port); in mvpp22_gop_init()
1670 if (!mvpp2_port_supports_xlg(port)) in mvpp22_gop_init()
1672 mvpp22_gop_init_10gkr(port); in mvpp22_gop_init()
1679 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | in mvpp22_gop_init()
1680 GENCONF_PORT_CTRL1_EN(port->gop_id); in mvpp22_gop_init()
1691 mvpp22_gop_fca_set_periodic_timer(port); in mvpp22_gop_init()
1697 netdev_err(port->dev, "Invalid port configuration\n"); in mvpp22_gop_init()
1701 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) in mvpp22_gop_unmask_irq() argument
1705 if (phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp22_gop_unmask_irq()
1706 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp22_gop_unmask_irq()
1707 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp22_gop_unmask_irq()
1708 /* Enable the GMAC link status irq for this port */ in mvpp22_gop_unmask_irq()
1709 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_unmask_irq()
1711 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_unmask_irq()
1714 if (mvpp2_port_supports_xlg(port)) { in mvpp22_gop_unmask_irq()
1715 /* Enable the XLG/GIG irqs for this port */ in mvpp22_gop_unmask_irq()
1716 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_unmask_irq()
1717 if (mvpp2_is_xlg(port->phy_interface)) in mvpp22_gop_unmask_irq()
1721 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_unmask_irq()
1725 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) in mvpp22_gop_mask_irq() argument
1729 if (mvpp2_port_supports_xlg(port)) { in mvpp22_gop_mask_irq()
1730 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_mask_irq()
1733 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_mask_irq()
1736 if (phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp22_gop_mask_irq()
1737 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp22_gop_mask_irq()
1738 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp22_gop_mask_irq()
1739 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_mask_irq()
1741 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_mask_irq()
1745 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) in mvpp22_gop_setup_irq() argument
1749 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK, in mvpp22_gop_setup_irq()
1753 if (port->phylink || in mvpp22_gop_setup_irq()
1754 phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp22_gop_setup_irq()
1755 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp22_gop_setup_irq()
1756 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp22_gop_setup_irq()
1757 val = readl(port->base + MVPP22_GMAC_INT_MASK); in mvpp22_gop_setup_irq()
1759 writel(val, port->base + MVPP22_GMAC_INT_MASK); in mvpp22_gop_setup_irq()
1762 if (mvpp2_port_supports_xlg(port)) { in mvpp22_gop_setup_irq()
1763 val = readl(port->base + MVPP22_XLG_INT_MASK); in mvpp22_gop_setup_irq()
1765 writel(val, port->base + MVPP22_XLG_INT_MASK); in mvpp22_gop_setup_irq()
1767 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK, in mvpp22_gop_setup_irq()
1772 mvpp22_gop_unmask_irq(port); in mvpp22_gop_setup_irq()
1785 static int mvpp22_comphy_init(struct mvpp2_port *port, in mvpp22_comphy_init() argument
1790 if (!port->comphy) in mvpp22_comphy_init()
1793 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, interface); in mvpp22_comphy_init()
1797 return phy_power_on(port->comphy); in mvpp22_comphy_init()
1800 static void mvpp2_port_enable(struct mvpp2_port *port) in mvpp2_port_enable() argument
1804 if (mvpp2_port_supports_xlg(port) && in mvpp2_port_enable()
1805 mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_enable()
1806 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()
1809 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()
1811 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
1814 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
1818 static void mvpp2_port_disable(struct mvpp2_port *port) in mvpp2_port_disable() argument
1822 if (mvpp2_port_supports_xlg(port) && in mvpp2_port_disable()
1823 mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_disable()
1824 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()
1826 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()
1829 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
1831 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
1835 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) in mvpp2_port_periodic_xon_disable() argument
1839 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & in mvpp2_port_periodic_xon_disable()
1841 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_periodic_xon_disable()
1844 /* Configure loopback port */
1845 static void mvpp2_port_loopback_set(struct mvpp2_port *port, in mvpp2_port_loopback_set() argument
1850 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
1863 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
1882 static u64 mvpp2_read_count(struct mvpp2_port *port, in mvpp2_read_count() argument
1887 val = readl(port->stats_base + counter->offset); in mvpp2_read_count()
1889 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; in mvpp2_read_count()
1987 struct mvpp2_port *port = netdev_priv(netdev); in mvpp2_ethtool_get_strings() local
2000 for (q = 0; q < port->ntxqs; q++) in mvpp2_ethtool_get_strings()
2006 for (q = 0; q < port->nrxqs; q++) in mvpp2_ethtool_get_strings()
2017 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats) in mvpp2_get_xdp_stats() argument
2033 cpu_stats = per_cpu_ptr(port->stats, cpu); in mvpp2_get_xdp_stats()
2055 static void mvpp2_read_stats(struct mvpp2_port *port) in mvpp2_read_stats() argument
2062 pstats = port->ethtool_stats; in mvpp2_read_stats()
2065 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]); in mvpp2_read_stats()
2068 *pstats++ += mvpp2_read(port->priv, in mvpp2_read_stats()
2070 4 * port->id); in mvpp2_read_stats()
2072 for (q = 0; q < port->ntxqs; q++) in mvpp2_read_stats()
2074 *pstats++ += mvpp2_read_index(port->priv, in mvpp2_read_stats()
2075 MVPP22_CTRS_TX_CTR(port->id, q), in mvpp2_read_stats()
2079 * driver's. We need to add the port->first_rxq offset. in mvpp2_read_stats()
2081 for (q = 0; q < port->nrxqs; q++) in mvpp2_read_stats()
2083 *pstats++ += mvpp2_read_index(port->priv, in mvpp2_read_stats()
2084 port->first_rxq + q, in mvpp2_read_stats()
2088 mvpp2_get_xdp_stats(port, &xdp_stats); in mvpp2_read_stats()
2122 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, in mvpp2_gather_hw_statistics() local
2125 mutex_lock(&port->gather_stats_lock); in mvpp2_gather_hw_statistics()
2127 mvpp2_read_stats(port); in mvpp2_gather_hw_statistics()
2132 cancel_delayed_work(&port->stats_work); in mvpp2_gather_hw_statistics()
2133 queue_delayed_work(port->priv->stats_queue, &port->stats_work, in mvpp2_gather_hw_statistics()
2136 mutex_unlock(&port->gather_stats_lock); in mvpp2_gather_hw_statistics()
2142 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_stats() local
2144 /* Update statistics for the given port, then take the lock to avoid in mvpp2_ethtool_get_stats()
2147 mvpp2_gather_hw_statistics(&port->stats_work.work); in mvpp2_ethtool_get_stats()
2149 mutex_lock(&port->gather_stats_lock); in mvpp2_ethtool_get_stats()
2150 memcpy(data, port->ethtool_stats, in mvpp2_ethtool_get_stats()
2151 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); in mvpp2_ethtool_get_stats()
2152 mutex_unlock(&port->gather_stats_lock); in mvpp2_ethtool_get_stats()
2157 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_sset_count() local
2160 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); in mvpp2_ethtool_get_sset_count()
2165 static void mvpp2_mac_reset_assert(struct mvpp2_port *port) in mvpp2_mac_reset_assert() argument
2169 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | in mvpp2_mac_reset_assert()
2171 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_mac_reset_assert()
2173 if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) { in mvpp2_mac_reset_assert()
2174 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & in mvpp2_mac_reset_assert()
2176 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_reset_assert()
2180 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) in mvpp22_pcs_reset_assert() argument
2182 struct mvpp2 *priv = port->priv; in mvpp22_pcs_reset_assert()
2186 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) in mvpp22_pcs_reset_assert()
2189 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); in mvpp22_pcs_reset_assert()
2190 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); in mvpp22_pcs_reset_assert()
2201 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port, in mvpp22_pcs_reset_deassert() argument
2204 struct mvpp2 *priv = port->priv; in mvpp22_pcs_reset_deassert()
2208 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) in mvpp22_pcs_reset_deassert()
2211 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); in mvpp22_pcs_reset_deassert()
2212 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); in mvpp22_pcs_reset_deassert()
2233 /* Change maximum receive size of the port */
2234 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) in mvpp2_gmac_max_rx_size_set() argument
2238 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2240 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_gmac_max_rx_size_set()
2242 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2245 /* Change maximum receive size of the port */
2246 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) in mvpp2_xlg_max_rx_size_set() argument
2250 val = readl(port->base + MVPP22_XLG_CTRL1_REG); in mvpp2_xlg_max_rx_size_set()
2252 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_xlg_max_rx_size_set()
2254 writel(val, port->base + MVPP22_XLG_CTRL1_REG); in mvpp2_xlg_max_rx_size_set()
2257 /* Set defaults to the MVPP2 port */
2258 static void mvpp2_defaults_set(struct mvpp2_port *port) in mvpp2_defaults_set() argument
2262 if (port->priv->hw_version == MVPP21) { in mvpp2_defaults_set()
2264 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
2268 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
2272 tx_port_num = mvpp2_egress_port(port); in mvpp2_defaults_set()
2273 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
2275 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
2278 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); in mvpp2_defaults_set()
2282 mvpp2_write(port->priv, in mvpp2_defaults_set()
2288 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, in mvpp2_defaults_set()
2289 port->priv->tclk / USEC_PER_SEC); in mvpp2_defaults_set()
2290 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
2294 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
2296 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
2299 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
2304 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { in mvpp2_defaults_set()
2305 queue = port->rxqs[lrxq]->id; in mvpp2_defaults_set()
2306 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
2309 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
2313 mvpp2_interrupts_disable(port); in mvpp2_defaults_set()
2317 static void mvpp2_ingress_enable(struct mvpp2_port *port) in mvpp2_ingress_enable() argument
2322 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { in mvpp2_ingress_enable()
2323 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_enable()
2324 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
2326 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
2330 static void mvpp2_ingress_disable(struct mvpp2_port *port) in mvpp2_ingress_disable() argument
2335 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { in mvpp2_ingress_disable()
2336 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_disable()
2337 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
2339 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
2346 static void mvpp2_egress_enable(struct mvpp2_port *port) in mvpp2_egress_enable() argument
2350 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_enable()
2354 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_egress_enable()
2355 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_egress_enable()
2361 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
2362 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
2368 static void mvpp2_egress_disable(struct mvpp2_port *port) in mvpp2_egress_disable() argument
2372 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_disable()
2375 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
2376 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
2379 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
2386 netdev_warn(port->dev, in mvpp2_egress_disable()
2394 /* Check port TX Command register that all in mvpp2_egress_disable()
2397 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
2405 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) in mvpp2_rxq_received() argument
2407 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
2416 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, in mvpp2_rxq_status_update() argument
2424 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
2439 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, in mvpp2_rxq_offset_set() argument
2447 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
2454 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
2474 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) in mvpp2_aggr_txq_pend_desc_add() argument
2477 mvpp2_thread_write(port->priv, in mvpp2_aggr_txq_pend_desc_add()
2478 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), in mvpp2_aggr_txq_pend_desc_add()
2488 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, in mvpp2_aggr_desc_num_check() argument
2494 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_aggr_desc_num_check()
2495 u32 val = mvpp2_read_relaxed(port->priv, in mvpp2_aggr_desc_num_check()
2512 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, in mvpp2_txq_alloc_reserved_desc() argument
2515 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_txq_alloc_reserved_desc()
2516 struct mvpp2 *priv = port->priv; in mvpp2_txq_alloc_reserved_desc()
2530 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, in mvpp2_txq_reserved_desc_num_proc() argument
2547 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_reserved_desc_num_proc()
2562 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); in mvpp2_txq_reserved_desc_num_proc()
2622 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, in mvpp2_txq_sent_desc_proc() argument
2628 val = mvpp2_thread_read_relaxed(port->priv, in mvpp2_txq_sent_desc_proc()
2629 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), in mvpp2_txq_sent_desc_proc()
2641 struct mvpp2_port *port = arg; in mvpp2_txq_sent_counter_clear() local
2645 if (smp_processor_id() >= port->priv->nthreads) in mvpp2_txq_sent_counter_clear()
2648 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_txq_sent_counter_clear()
2649 int id = port->txqs[queue]->id; in mvpp2_txq_sent_counter_clear()
2651 mvpp2_thread_read(port->priv, in mvpp2_txq_sent_counter_clear()
2652 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), in mvpp2_txq_sent_counter_clear()
2658 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) in mvpp2_txp_max_tx_size_set() argument
2663 mtu = port->pkt_size * 8; in mvpp2_txp_max_tx_size_set()
2671 tx_port_num = mvpp2_egress_port(port); in mvpp2_txp_max_tx_size_set()
2672 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
2675 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
2678 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
2681 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
2687 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
2690 for (txq = 0; txq < port->ntxqs; txq++) { in mvpp2_txp_max_tx_size_set()
2691 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
2699 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
2707 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port, in mvpp2_set_rxq_free_tresh() argument
2712 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_set_rxq_free_tresh()
2714 val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG); in mvpp2_set_rxq_free_tresh()
2717 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); in mvpp2_set_rxq_free_tresh()
2723 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, in mvpp2_rx_pkts_coal_set() argument
2726 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_rx_pkts_coal_set()
2731 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rx_pkts_coal_set()
2732 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, in mvpp2_rx_pkts_coal_set()
2739 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, in mvpp2_tx_pkts_coal_set() argument
2751 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_tx_pkts_coal_set()
2752 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); in mvpp2_tx_pkts_coal_set()
2775 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, in mvpp2_rx_time_coal_set() argument
2778 unsigned long freq = port->priv->tclk; in mvpp2_rx_time_coal_set()
2789 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); in mvpp2_rx_time_coal_set()
2792 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) in mvpp2_tx_time_coal_set() argument
2794 unsigned long freq = port->priv->tclk; in mvpp2_tx_time_coal_set()
2795 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); in mvpp2_tx_time_coal_set()
2798 port->tx_time_coal = in mvpp2_tx_time_coal_set()
2802 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); in mvpp2_tx_time_coal_set()
2805 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); in mvpp2_tx_time_coal_set()
2809 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, in mvpp2_txq_bufs_free() argument
2826 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, in mvpp2_txq_bufs_free()
2841 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, in mvpp2_get_rx_queue() argument
2846 return port->rxqs[queue]; in mvpp2_get_rx_queue()
2849 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, in mvpp2_get_tx_queue() argument
2854 return port->txqs[queue]; in mvpp2_get_tx_queue()
2858 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, in mvpp2_txq_done() argument
2861 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); in mvpp2_txq_done()
2864 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) in mvpp2_txq_done()
2865 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); in mvpp2_txq_done()
2867 tx_done = mvpp2_txq_sent_desc_proc(port, txq); in mvpp2_txq_done()
2870 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); in mvpp2_txq_done()
2879 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, in mvpp2_tx_done() argument
2887 txq = mvpp2_get_tx_queue(port, cause); in mvpp2_tx_done()
2894 mvpp2_txq_done(port, txq, txq_pcpu); in mvpp2_tx_done()
2942 static int mvpp2_rxq_init(struct mvpp2_port *port, in mvpp2_rxq_init() argument
2945 struct mvpp2 *priv = port->priv; in mvpp2_rxq_init()
2950 rxq->size = port->rx_ring_size; in mvpp2_rxq_init()
2953 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_rxq_init()
2962 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
2965 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_rxq_init()
2966 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
2967 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_init()
2971 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); in mvpp2_rxq_init()
2972 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
2973 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
2977 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM); in mvpp2_rxq_init()
2980 mvpp2_rx_pkts_coal_set(port, rxq); in mvpp2_rxq_init()
2981 mvpp2_rx_time_coal_set(port, rxq); in mvpp2_rxq_init()
2984 mvpp2_set_rxq_free_tresh(port, rxq); in mvpp2_rxq_init()
2987 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); in mvpp2_rxq_init()
2990 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->logic_rxq, 0); in mvpp2_rxq_init()
2994 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->logic_rxq, 0); in mvpp2_rxq_init()
3008 port->nrxqs]); in mvpp2_rxq_init()
3022 dma_free_coherent(port->dev->dev.parent, in mvpp2_rxq_init()
3029 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, in mvpp2_rxq_drop_pkts() argument
3034 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rxq_drop_pkts()
3040 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rxq_drop_pkts()
3046 mvpp2_bm_pool_put(port, pool, in mvpp2_rxq_drop_pkts()
3047 mvpp2_rxdesc_dma_addr_get(port, rx_desc), in mvpp2_rxq_drop_pkts()
3048 mvpp2_rxdesc_cookie_get(port, rx_desc)); in mvpp2_rxq_drop_pkts()
3050 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); in mvpp2_rxq_drop_pkts()
3054 static void mvpp2_rxq_deinit(struct mvpp2_port *port, in mvpp2_rxq_deinit() argument
3065 mvpp2_rxq_drop_pkts(port, rxq); in mvpp2_rxq_deinit()
3068 dma_free_coherent(port->dev->dev.parent, in mvpp2_rxq_deinit()
3081 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
3082 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_rxq_deinit()
3083 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
3084 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
3085 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
3090 static int mvpp2_txq_init(struct mvpp2_port *port, in mvpp2_txq_init() argument
3098 txq->size = port->tx_ring_size; in mvpp2_txq_init()
3101 txq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_txq_init()
3110 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_txq_init()
3111 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
3112 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, in mvpp2_txq_init()
3114 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, in mvpp2_txq_init()
3116 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
3117 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
3119 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_init()
3121 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
3125 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT in mvpp2_txq_init()
3129 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + in mvpp2_txq_init()
3132 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
3138 tx_port_num = mvpp2_egress_port(port); in mvpp2_txq_init()
3139 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
3141 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
3145 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
3148 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
3151 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_init()
3170 dma_alloc_coherent(port->dev->dev.parent, in mvpp2_txq_init()
3182 static void mvpp2_txq_deinit(struct mvpp2_port *port, in mvpp2_txq_deinit() argument
3188 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_deinit()
3193 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_deinit()
3202 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_deinit()
3212 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); in mvpp2_txq_deinit()
3215 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_txq_deinit()
3216 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
3217 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
3218 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
3223 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) in mvpp2_txq_clean() argument
3227 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_txq_clean()
3230 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
3231 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); in mvpp2_txq_clean()
3233 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
3241 netdev_warn(port->dev, in mvpp2_txq_clean()
3242 "port %d: cleaning queue %d timed out\n", in mvpp2_txq_clean()
3243 port->id, txq->log_id); in mvpp2_txq_clean()
3249 pending = mvpp2_thread_read(port->priv, thread, in mvpp2_txq_clean()
3255 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
3258 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_clean()
3262 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); in mvpp2_txq_clean()
3272 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) in mvpp2_cleanup_txqs() argument
3278 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()
3281 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
3282 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
3284 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_cleanup_txqs()
3285 txq = port->txqs[queue]; in mvpp2_cleanup_txqs()
3286 mvpp2_txq_clean(port, txq); in mvpp2_cleanup_txqs()
3287 mvpp2_txq_deinit(port, txq); in mvpp2_cleanup_txqs()
3290 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); in mvpp2_cleanup_txqs()
3292 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
3293 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
3297 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) in mvpp2_cleanup_rxqs() argument
3301 for (queue = 0; queue < port->nrxqs; queue++) in mvpp2_cleanup_rxqs()
3302 mvpp2_rxq_deinit(port, port->rxqs[queue]); in mvpp2_cleanup_rxqs()
3304 if (port->tx_fc) in mvpp2_cleanup_rxqs()
3305 mvpp2_rxq_disable_fc(port); in mvpp2_cleanup_rxqs()
3308 /* Init all Rx queues for port */
3309 static int mvpp2_setup_rxqs(struct mvpp2_port *port) in mvpp2_setup_rxqs() argument
3313 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_setup_rxqs()
3314 err = mvpp2_rxq_init(port, port->rxqs[queue]); in mvpp2_setup_rxqs()
3319 if (port->tx_fc) in mvpp2_setup_rxqs()
3320 mvpp2_rxq_enable_fc(port); in mvpp2_setup_rxqs()
3325 mvpp2_cleanup_rxqs(port); in mvpp2_setup_rxqs()
3329 /* Init all tx queues for port */
3330 static int mvpp2_setup_txqs(struct mvpp2_port *port) in mvpp2_setup_txqs() argument
3335 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_setup_txqs()
3336 txq = port->txqs[queue]; in mvpp2_setup_txqs()
3337 err = mvpp2_txq_init(port, txq); in mvpp2_setup_txqs()
3343 netif_set_xps_queue(port->dev, cpumask_of(queue), queue); in mvpp2_setup_txqs()
3346 if (port->has_tx_irqs) { in mvpp2_setup_txqs()
3347 mvpp2_tx_time_coal_set(port); in mvpp2_setup_txqs()
3348 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_setup_txqs()
3349 txq = port->txqs[queue]; in mvpp2_setup_txqs()
3350 mvpp2_tx_pkts_coal_set(port, txq); in mvpp2_setup_txqs()
3354 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); in mvpp2_setup_txqs()
3358 mvpp2_cleanup_txqs(port); in mvpp2_setup_txqs()
3362 /* The callback for per-port interrupt */
3374 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq) in mvpp2_isr_handle_ptp_queue() argument
3383 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); in mvpp2_isr_handle_ptp_queue()
3387 queue = &port->tx_hwtstamp_queue[nq]; in mvpp2_isr_handle_ptp_queue()
3404 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps); in mvpp2_isr_handle_ptp_queue()
3411 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port) in mvpp2_isr_handle_ptp() argument
3416 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); in mvpp2_isr_handle_ptp()
3419 mvpp2_isr_handle_ptp_queue(port, 0); in mvpp2_isr_handle_ptp()
3421 mvpp2_isr_handle_ptp_queue(port, 1); in mvpp2_isr_handle_ptp()
3424 static void mvpp2_isr_handle_link(struct mvpp2_port *port, in mvpp2_isr_handle_link() argument
3427 struct net_device *dev = port->dev; in mvpp2_isr_handle_link()
3429 if (port->phylink) { in mvpp2_isr_handle_link()
3438 mvpp2_interrupts_enable(port); in mvpp2_isr_handle_link()
3440 mvpp2_egress_enable(port); in mvpp2_isr_handle_link()
3441 mvpp2_ingress_enable(port); in mvpp2_isr_handle_link()
3447 mvpp2_ingress_disable(port); in mvpp2_isr_handle_link()
3448 mvpp2_egress_disable(port); in mvpp2_isr_handle_link()
3450 mvpp2_interrupts_disable(port); in mvpp2_isr_handle_link()
3454 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port) in mvpp2_isr_handle_xlg() argument
3459 val = readl(port->base + MVPP22_XLG_INT_STAT); in mvpp2_isr_handle_xlg()
3461 val = readl(port->base + MVPP22_XLG_STATUS); in mvpp2_isr_handle_xlg()
3463 mvpp2_isr_handle_link(port, &port->pcs_xlg, link); in mvpp2_isr_handle_xlg()
3467 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port) in mvpp2_isr_handle_gmac_internal() argument
3472 if (phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp2_isr_handle_gmac_internal()
3473 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp2_isr_handle_gmac_internal()
3474 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp2_isr_handle_gmac_internal()
3475 val = readl(port->base + MVPP22_GMAC_INT_STAT); in mvpp2_isr_handle_gmac_internal()
3477 val = readl(port->base + MVPP2_GMAC_STATUS0); in mvpp2_isr_handle_gmac_internal()
3479 mvpp2_isr_handle_link(port, &port->pcs_gmac, link); in mvpp2_isr_handle_gmac_internal()
3484 /* Per-port interrupt for link status changes */
3487 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; in mvpp2_port_isr() local
3490 mvpp22_gop_mask_irq(port); in mvpp2_port_isr()
3492 if (mvpp2_port_supports_xlg(port) && in mvpp2_port_isr()
3493 mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_isr()
3495 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT); in mvpp2_port_isr()
3497 mvpp2_isr_handle_xlg(port); in mvpp2_port_isr()
3499 mvpp2_isr_handle_ptp(port); in mvpp2_port_isr()
3504 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT); in mvpp2_port_isr()
3506 mvpp2_isr_handle_gmac_internal(port); in mvpp2_port_isr()
3508 mvpp2_isr_handle_ptp(port); in mvpp2_port_isr()
3511 mvpp22_gop_unmask_irq(port); in mvpp2_port_isr()
3518 struct mvpp2_port *port; in mvpp2_hr_timer_cb() local
3529 port = netdev_priv(dev); in mvpp2_hr_timer_cb()
3532 cause = (1 << port->ntxqs) - 1; in mvpp2_hr_timer_cb()
3533 tx_todo = mvpp2_tx_done(port, cause, in mvpp2_hr_timer_cb()
3534 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); in mvpp2_hr_timer_cb()
3550 static void mvpp2_rx_error(struct mvpp2_port *port, in mvpp2_rx_error() argument
3553 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rx_error()
3554 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_rx_error()
3569 netdev_err(port->dev, in mvpp2_rx_error()
3575 static int mvpp2_rx_csum(struct mvpp2_port *port, u32 status) in mvpp2_rx_csum() argument
3589 static int mvpp2_rx_refill(struct mvpp2_port *port, in mvpp2_rx_refill() argument
3597 buf = mvpp2_buf_alloc(port, bm_pool, page_pool, in mvpp2_rx_refill()
3602 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_rx_refill()
3608 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) in mvpp2_skb_tx_csum() argument
3639 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte) in mvpp2_xdp_finish_tx() argument
3641 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_xdp_finish_tx()
3647 txq = port->txqs[txq_id]; in mvpp2_xdp_finish_tx()
3649 nq = netdev_get_tx_queue(port->dev, txq_id); in mvpp2_xdp_finish_tx()
3650 aggr_txq = &port->priv->aggr_txqs[thread]; in mvpp2_xdp_finish_tx()
3658 mvpp2_aggr_txq_pend_desc_add(port, nxmit); in mvpp2_xdp_finish_tx()
3664 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) in mvpp2_xdp_finish_tx()
3665 mvpp2_txq_done(port, txq, txq_pcpu); in mvpp2_xdp_finish_tx()
3669 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id, in mvpp2_xdp_submit_frame() argument
3672 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_xdp_submit_frame()
3683 txq = port->txqs[txq_id]; in mvpp2_xdp_submit_frame()
3685 aggr_txq = &port->priv->aggr_txqs[thread]; in mvpp2_xdp_submit_frame()
3688 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) || in mvpp2_xdp_submit_frame()
3689 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) { in mvpp2_xdp_submit_frame()
3696 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_xdp_submit_frame()
3697 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len); in mvpp2_xdp_submit_frame()
3701 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data, in mvpp2_xdp_submit_frame()
3704 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { in mvpp2_xdp_submit_frame()
3717 dma_sync_single_for_device(port->dev->dev.parent, dma_addr, in mvpp2_xdp_submit_frame()
3723 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr); in mvpp2_xdp_submit_frame()
3725 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); in mvpp2_xdp_submit_frame()
3726 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type); in mvpp2_xdp_submit_frame()
3733 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp) in mvpp2_xdp_xmit_back() argument
3735 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_xdp_xmit_back()
3747 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); in mvpp2_xdp_xmit_back()
3749 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false); in mvpp2_xdp_xmit_back()
3757 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len); in mvpp2_xdp_xmit_back()
3771 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_xdp_xmit() local
3777 if (unlikely(test_bit(0, &port->state))) in mvpp2_xdp_xmit()
3786 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); in mvpp2_xdp_xmit()
3789 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true); in mvpp2_xdp_xmit()
3798 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte); in mvpp2_xdp_xmit()
3800 stats = this_cpu_ptr(port->stats); in mvpp2_xdp_xmit()
3812 mvpp2_run_xdp(struct mvpp2_port *port, struct bpf_prog *prog, in mvpp2_run_xdp() argument
3833 err = xdp_do_redirect(port->dev, xdp, prog); in mvpp2_run_xdp()
3844 ret = mvpp2_xdp_xmit_back(port, xdp); in mvpp2_run_xdp()
3851 bpf_warn_invalid_xdp_action(port->dev, prog, act); in mvpp2_run_xdp()
3854 trace_xdp_exception(port->dev, prog, act); in mvpp2_run_xdp()
3867 static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc, in mvpp2_buff_hdr_pool_put() argument
3874 phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); in mvpp2_buff_hdr_pool_put()
3875 dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); in mvpp2_buff_hdr_pool_put()
3883 if (port->priv->hw_version >= MVPP22) { in mvpp2_buff_hdr_pool_put()
3888 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_buff_hdr_pool_put()
3897 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, in mvpp2_rx() argument
3900 struct net_device *dev = port->dev; in mvpp2_rx()
3909 xdp_prog = READ_ONCE(port->xdp_prog); in mvpp2_rx()
3912 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rx()
3929 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); in mvpp2_rx()
3935 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rx()
3936 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_rx()
3938 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); in mvpp2_rx()
3942 bm_pool = &port->priv->bm_pools[pool]; in mvpp2_rx()
3944 if (port->priv->percpu_pools) { in mvpp2_rx()
3945 pp = port->priv->page_pool[pool]; in mvpp2_rx()
3988 ret = mvpp2_run_xdp(port, xdp_prog, &xdp, pp, &ps); in mvpp2_rx()
3992 err = mvpp2_rx_refill(port, bm_pool, pp, pool); in mvpp2_rx()
3994 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_rx()
4009 netdev_warn(port->dev, "skb build failed\n"); in mvpp2_rx()
4016 if (mvpp22_rx_hwtstamping(port)) { in mvpp2_rx()
4018 mvpp22_tai_tstamp(port->priv->tai, timestamp, in mvpp2_rx()
4022 err = mvpp2_rx_refill(port, bm_pool, pp, pool); in mvpp2_rx()
4024 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_rx()
4041 skb->ip_summed = mvpp2_rx_csum(port, rx_status); in mvpp2_rx()
4049 mvpp2_rx_error(port, rx_desc); in mvpp2_rx()
4052 mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status); in mvpp2_rx()
4054 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_rx()
4061 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_rx()
4075 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); in mvpp2_rx()
4081 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, in tx_desc_unmap_put() argument
4084 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in tx_desc_unmap_put()
4088 mvpp2_txdesc_dma_addr_get(port, desc); in tx_desc_unmap_put()
4090 mvpp2_txdesc_size_get(port, desc); in tx_desc_unmap_put()
4092 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, in tx_desc_unmap_put()
4097 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port, in mvpp2_txdesc_clear_ptp() argument
4101 if (port->priv->hw_version >= MVPP22) in mvpp2_txdesc_clear_ptp()
4106 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port, in mvpp2_tx_hw_tstamp() argument
4115 if (port->priv->hw_version == MVPP21 || in mvpp2_tx_hw_tstamp()
4116 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF) in mvpp2_tx_hw_tstamp()
4131 queue = &port->tx_hwtstamp_queue[0]; in mvpp2_tx_hw_tstamp()
4144 queue = &port->tx_hwtstamp_queue[1]; in mvpp2_tx_hw_tstamp()
4186 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, in mvpp2_tx_frag_process() argument
4190 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_tx_frag_process()
4201 mvpp2_txdesc_clear_ptp(port, tx_desc); in mvpp2_tx_frag_process()
4202 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tx_frag_process()
4203 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag)); in mvpp2_tx_frag_process()
4205 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, in mvpp2_tx_frag_process()
4208 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { in mvpp2_tx_frag_process()
4213 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); in mvpp2_tx_frag_process()
4217 mvpp2_txdesc_cmd_set(port, tx_desc, in mvpp2_tx_frag_process()
4219 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tx_frag_process()
4222 mvpp2_txdesc_cmd_set(port, tx_desc, 0); in mvpp2_tx_frag_process()
4223 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tx_frag_process()
4234 tx_desc_unmap_put(port, txq, tx_desc); in mvpp2_tx_frag_process()
4247 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tso_put_hdr() local
4251 mvpp2_txdesc_clear_ptp(port, tx_desc); in mvpp2_tso_put_hdr()
4252 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tso_put_hdr()
4253 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); in mvpp2_tso_put_hdr()
4257 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); in mvpp2_tso_put_hdr()
4259 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | in mvpp2_tso_put_hdr()
4262 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tso_put_hdr()
4272 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tso_put_data() local
4276 mvpp2_txdesc_clear_ptp(port, tx_desc); in mvpp2_tso_put_data()
4277 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tso_put_data()
4278 mvpp2_txdesc_size_set(port, tx_desc, sz); in mvpp2_tso_put_data()
4287 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); in mvpp2_tso_put_data()
4290 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); in mvpp2_tso_put_data()
4292 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tso_put_data()
4296 mvpp2_txdesc_cmd_set(port, tx_desc, 0); in mvpp2_tso_put_data()
4299 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tso_put_data()
4308 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tx_tso() local
4313 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || in mvpp2_tx_tso()
4314 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, in mvpp2_tx_tso()
4349 tx_desc_unmap_put(port, txq, tx_desc); in mvpp2_tx_tso()
4357 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tx() local
4368 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_tx()
4371 txq = port->txqs[txq_id]; in mvpp2_tx()
4373 aggr_txq = &port->priv->aggr_txqs[thread]; in mvpp2_tx()
4375 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_tx()
4376 spin_lock_irqsave(&port->tx_lock[thread], flags); in mvpp2_tx()
4385 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || in mvpp2_tx()
4386 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { in mvpp2_tx()
4394 !mvpp2_tx_hw_tstamp(port, tx_desc, skb)) in mvpp2_tx()
4395 mvpp2_txdesc_clear_ptp(port, tx_desc); in mvpp2_tx()
4396 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tx()
4397 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); in mvpp2_tx()
4407 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); in mvpp2_tx()
4409 tx_cmd = mvpp2_skb_tx_csum(port, skb); in mvpp2_tx()
4414 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); in mvpp2_tx()
4415 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tx()
4419 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); in mvpp2_tx()
4420 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tx()
4423 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { in mvpp2_tx()
4424 tx_desc_unmap_put(port, txq, tx_desc); in mvpp2_tx()
4431 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); in mvpp2_tx()
4440 mvpp2_aggr_txq_pend_desc_add(port, frags); in mvpp2_tx()
4455 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) in mvpp2_tx()
4456 mvpp2_txq_done(port, txq, txq_pcpu); in mvpp2_tx()
4459 if (!port->has_tx_irqs && txq_pcpu->count <= frags && in mvpp2_tx()
4461 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); in mvpp2_tx()
4471 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_tx()
4472 spin_unlock_irqrestore(&port->tx_lock[thread], flags); in mvpp2_tx()
4491 struct mvpp2_port *port = netdev_priv(napi->dev); in mvpp2_poll() local
4493 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_poll()
4507 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, in mvpp2_poll()
4508 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); in mvpp2_poll()
4512 mvpp2_cause_error(port->dev, cause_misc); in mvpp2_poll()
4515 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); in mvpp2_poll()
4516 mvpp2_thread_write(port->priv, thread, in mvpp2_poll()
4517 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), in mvpp2_poll()
4521 if (port->has_tx_irqs) { in mvpp2_poll()
4525 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); in mvpp2_poll()
4531 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); in mvpp2_poll()
4538 rxq = mvpp2_get_rx_queue(port, cause_rx); in mvpp2_poll()
4542 count = mvpp2_rx(port, napi, budget, rxq); in mvpp2_poll()
4564 static void mvpp22_mode_reconfigure(struct mvpp2_port *port, in mvpp22_mode_reconfigure() argument
4570 mvpp2_mac_reset_assert(port); in mvpp22_mode_reconfigure()
4573 mvpp22_pcs_reset_assert(port); in mvpp22_mode_reconfigure()
4576 mvpp22_comphy_init(port, interface); in mvpp22_mode_reconfigure()
4579 mvpp22_gop_init(port, interface); in mvpp22_mode_reconfigure()
4581 mvpp22_pcs_reset_deassert(port, interface); in mvpp22_mode_reconfigure()
4583 if (mvpp2_port_supports_xlg(port)) { in mvpp22_mode_reconfigure()
4584 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure()
4592 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure()
4595 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(interface)) in mvpp22_mode_reconfigure()
4596 mvpp2_xlg_max_rx_size_set(port); in mvpp22_mode_reconfigure()
4598 mvpp2_gmac_max_rx_size_set(port); in mvpp22_mode_reconfigure()
4601 /* Set hw internals when starting port */
4602 static void mvpp2_start_dev(struct mvpp2_port *port) in mvpp2_start_dev() argument
4606 mvpp2_txp_max_tx_size_set(port); in mvpp2_start_dev()
4608 for (i = 0; i < port->nqvecs; i++) in mvpp2_start_dev()
4609 napi_enable(&port->qvecs[i].napi); in mvpp2_start_dev()
4612 mvpp2_interrupts_enable(port); in mvpp2_start_dev()
4614 if (port->priv->hw_version >= MVPP22) in mvpp2_start_dev()
4615 mvpp22_mode_reconfigure(port, port->phy_interface); in mvpp2_start_dev()
4617 if (port->phylink) { in mvpp2_start_dev()
4618 phylink_start(port->phylink); in mvpp2_start_dev()
4620 mvpp2_acpi_start(port); in mvpp2_start_dev()
4623 netif_tx_start_all_queues(port->dev); in mvpp2_start_dev()
4625 clear_bit(0, &port->state); in mvpp2_start_dev()
4628 /* Set hw internals when stopping port */
4629 static void mvpp2_stop_dev(struct mvpp2_port *port) in mvpp2_stop_dev() argument
4633 set_bit(0, &port->state); in mvpp2_stop_dev()
4636 mvpp2_interrupts_disable(port); in mvpp2_stop_dev()
4638 for (i = 0; i < port->nqvecs; i++) in mvpp2_stop_dev()
4639 napi_disable(&port->qvecs[i].napi); in mvpp2_stop_dev()
4641 if (port->phylink) in mvpp2_stop_dev()
4642 phylink_stop(port->phylink); in mvpp2_stop_dev()
4643 phy_power_off(port->comphy); in mvpp2_stop_dev()
4688 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) in mvpp21_get_mac_address() argument
4692 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp21_get_mac_address()
4693 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); in mvpp21_get_mac_address()
4694 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); in mvpp21_get_mac_address()
4703 static int mvpp2_irqs_init(struct mvpp2_port *port) in mvpp2_irqs_init() argument
4707 for (i = 0; i < port->nqvecs; i++) { in mvpp2_irqs_init()
4708 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_irqs_init()
4720 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); in mvpp2_irqs_init()
4728 if (mvpp2_cpu_to_thread(port->priv, cpu) == in mvpp2_irqs_init()
4739 for (i = 0; i < port->nqvecs; i++) { in mvpp2_irqs_init()
4740 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_irqs_init()
4751 static void mvpp2_irqs_deinit(struct mvpp2_port *port) in mvpp2_irqs_deinit() argument
4755 for (i = 0; i < port->nqvecs; i++) { in mvpp2_irqs_deinit()
4756 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_irqs_deinit()
4766 static bool mvpp22_rss_is_supported(struct mvpp2_port *port) in mvpp22_rss_is_supported() argument
4769 !(port->flags & MVPP2_F_LOOPBACK); in mvpp22_rss_is_supported()
4774 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_open() local
4775 struct mvpp2 *priv = port->priv; in mvpp2_open()
4781 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); in mvpp2_open()
4786 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); in mvpp2_open()
4791 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); in mvpp2_open()
4796 err = mvpp2_prs_def_flow(port); in mvpp2_open()
4803 err = mvpp2_setup_rxqs(port); in mvpp2_open()
4805 netdev_err(port->dev, "cannot allocate Rx queues\n"); in mvpp2_open()
4809 err = mvpp2_setup_txqs(port); in mvpp2_open()
4811 netdev_err(port->dev, "cannot allocate Tx queues\n"); in mvpp2_open()
4815 err = mvpp2_irqs_init(port); in mvpp2_open()
4817 netdev_err(port->dev, "cannot init IRQs\n"); in mvpp2_open()
4821 if (port->phylink) { in mvpp2_open()
4822 err = phylink_fwnode_phy_connect(port->phylink, port->fwnode, 0); in mvpp2_open()
4824 netdev_err(port->dev, "could not attach PHY (%d)\n", in mvpp2_open()
4832 if (priv->hw_version >= MVPP22 && port->port_irq) { in mvpp2_open()
4833 err = request_irq(port->port_irq, mvpp2_port_isr, 0, in mvpp2_open()
4834 dev->name, port); in mvpp2_open()
4836 netdev_err(port->dev, in mvpp2_open()
4837 "cannot request port link/ptp IRQ %d\n", in mvpp2_open()
4838 port->port_irq); in mvpp2_open()
4842 mvpp22_gop_setup_irq(port); in mvpp2_open()
4845 netif_carrier_off(port->dev); in mvpp2_open()
4849 port->port_irq = 0; in mvpp2_open()
4853 netdev_err(port->dev, in mvpp2_open()
4860 on_each_cpu(mvpp2_interrupts_unmask, port, 1); in mvpp2_open()
4861 mvpp2_shared_interrupt_mask_unmask(port, false); in mvpp2_open()
4863 mvpp2_start_dev(port); in mvpp2_open()
4866 queue_delayed_work(priv->stats_queue, &port->stats_work, in mvpp2_open()
4872 mvpp2_irqs_deinit(port); in mvpp2_open()
4874 mvpp2_cleanup_txqs(port); in mvpp2_open()
4876 mvpp2_cleanup_rxqs(port); in mvpp2_open()
4882 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_stop() local
4886 mvpp2_stop_dev(port); in mvpp2_stop()
4889 on_each_cpu(mvpp2_interrupts_mask, port, 1); in mvpp2_stop()
4890 mvpp2_shared_interrupt_mask_unmask(port, true); in mvpp2_stop()
4892 if (port->phylink) in mvpp2_stop()
4893 phylink_disconnect_phy(port->phylink); in mvpp2_stop()
4894 if (port->port_irq) in mvpp2_stop()
4895 free_irq(port->port_irq, port); in mvpp2_stop()
4897 mvpp2_irqs_deinit(port); in mvpp2_stop()
4898 if (!port->has_tx_irqs) { in mvpp2_stop()
4899 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_stop()
4900 port_pcpu = per_cpu_ptr(port->pcpu, thread); in mvpp2_stop()
4906 mvpp2_cleanup_rxqs(port); in mvpp2_stop()
4907 mvpp2_cleanup_txqs(port); in mvpp2_stop()
4909 cancel_delayed_work_sync(&port->stats_work); in mvpp2_stop()
4911 mvpp2_mac_reset_assert(port); in mvpp2_stop()
4912 mvpp22_pcs_reset_assert(port); in mvpp2_stop()
4917 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, in mvpp2_prs_mac_da_accept_list() argument
4924 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); in mvpp2_prs_mac_da_accept_list()
4932 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) in mvpp2_set_rx_promisc() argument
4934 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) in mvpp2_set_rx_promisc()
4935 mvpp2_prs_vid_enable_filtering(port); in mvpp2_set_rx_promisc()
4937 mvpp2_prs_vid_disable_filtering(port); in mvpp2_set_rx_promisc()
4939 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_promisc()
4942 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_promisc()
4948 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_set_rx_mode() local
4951 mvpp2_prs_mac_del_all(port); in mvpp2_set_rx_mode()
4954 mvpp2_set_rx_promisc(port, true); in mvpp2_set_rx_mode()
4958 mvpp2_set_rx_promisc(port, false); in mvpp2_set_rx_mode()
4961 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) in mvpp2_set_rx_mode()
4962 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_mode()
4966 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_mode()
4972 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) in mvpp2_set_rx_mode()
4973 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_mode()
5001 struct mvpp2_port *port = NULL; in mvpp2_bm_switch_buffers() local
5005 port = priv->port_list[i]; in mvpp2_bm_switch_buffers()
5006 status[i] = netif_running(port->dev); in mvpp2_bm_switch_buffers()
5008 mvpp2_stop(port->dev); in mvpp2_bm_switch_buffers()
5013 numbufs = port->nrxqs * 2; in mvpp2_bm_switch_buffers()
5019 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]); in mvpp2_bm_switch_buffers()
5021 devm_kfree(port->dev->dev.parent, priv->bm_pools); in mvpp2_bm_switch_buffers()
5023 mvpp2_bm_init(port->dev->dev.parent, priv); in mvpp2_bm_switch_buffers()
5026 port = priv->port_list[i]; in mvpp2_bm_switch_buffers()
5027 if (percpu && port->ntxqs >= num_possible_cpus() * 2) in mvpp2_bm_switch_buffers()
5028 xdp_set_features_flag(port->dev, in mvpp2_bm_switch_buffers()
5033 xdp_clear_features_flag(port->dev); in mvpp2_bm_switch_buffers()
5035 mvpp2_swf_bm_pool_init(port); in mvpp2_bm_switch_buffers()
5037 mvpp2_open(port->dev); in mvpp2_bm_switch_buffers()
5048 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_change_mtu() local
5050 struct mvpp2 *priv = port->priv; in mvpp2_change_mtu()
5059 if (port->xdp_prog && mtu > MVPP2_MAX_RX_BUF_SIZE) { in mvpp2_change_mtu()
5075 if (priv->port_list[i] != port && in mvpp2_change_mtu()
5082 /* No port is using jumbo frames */ in mvpp2_change_mtu()
5084 dev_info(port->dev->dev.parent, in mvpp2_change_mtu()
5091 mvpp2_stop_dev(port); in mvpp2_change_mtu()
5099 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); in mvpp2_change_mtu()
5103 mvpp2_start_dev(port); in mvpp2_change_mtu()
5104 mvpp2_egress_enable(port); in mvpp2_change_mtu()
5105 mvpp2_ingress_enable(port); in mvpp2_change_mtu()
5111 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port) in mvpp2_check_pagepool_dma() argument
5114 struct mvpp2 *priv = port->priv; in mvpp2_check_pagepool_dma()
5124 port = priv->port_list[i]; in mvpp2_check_pagepool_dma()
5125 if (port->xdp_prog) { in mvpp2_check_pagepool_dma()
5141 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_get_stats64() local
5152 cpu_stats = per_cpu_ptr(port->stats, cpu); in mvpp2_get_stats64()
5172 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr) in mvpp2_set_ts_config() argument
5185 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); in mvpp2_set_ts_config()
5200 mvpp22_tai_start(port->priv->tai); in mvpp2_set_ts_config()
5208 port->rx_hwtstamp = true; in mvpp2_set_ts_config()
5210 port->rx_hwtstamp = false; in mvpp2_set_ts_config()
5222 mvpp22_tai_stop(port->priv->tai); in mvpp2_set_ts_config()
5224 port->tx_hwtstamp_type = config.tx_type; in mvpp2_set_ts_config()
5232 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr) in mvpp2_get_ts_config() argument
5238 config.tx_type = port->tx_hwtstamp_type; in mvpp2_get_ts_config()
5239 config.rx_filter = port->rx_hwtstamp ? in mvpp2_get_ts_config()
5251 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_ts_info() local
5253 if (!port->hwtstamp) in mvpp2_ethtool_get_ts_info()
5256 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai); in mvpp2_ethtool_get_ts_info()
5271 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ioctl() local
5275 if (port->hwtstamp) in mvpp2_ioctl()
5276 return mvpp2_set_ts_config(port, ifr); in mvpp2_ioctl()
5280 if (port->hwtstamp) in mvpp2_ioctl()
5281 return mvpp2_get_ts_config(port, ifr); in mvpp2_ioctl()
5285 if (!port->phylink) in mvpp2_ioctl()
5288 return phylink_mii_ioctl(port->phylink, ifr, cmd); in mvpp2_ioctl()
5293 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_vlan_rx_add_vid() local
5296 ret = mvpp2_prs_vid_entry_add(port, vid); in mvpp2_vlan_rx_add_vid()
5298 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", in mvpp2_vlan_rx_add_vid()
5305 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_vlan_rx_kill_vid() local
5307 mvpp2_prs_vid_entry_remove(port, vid); in mvpp2_vlan_rx_kill_vid()
5315 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_set_features() local
5319 mvpp2_prs_vid_enable_filtering(port); in mvpp2_set_features()
5322 * port in mvpp2_set_features()
5324 mvpp2_prs_vid_remove_all(port); in mvpp2_set_features()
5326 mvpp2_prs_vid_disable_filtering(port); in mvpp2_set_features()
5332 mvpp22_port_rss_enable(port); in mvpp2_set_features()
5334 mvpp22_port_rss_disable(port); in mvpp2_set_features()
5340 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf) in mvpp2_xdp_setup() argument
5343 bool running = netif_running(port->dev); in mvpp2_xdp_setup()
5344 bool reset = !prog != !port->xdp_prog; in mvpp2_xdp_setup()
5346 if (port->dev->mtu > MVPP2_MAX_RX_BUF_SIZE) { in mvpp2_xdp_setup()
5351 if (!port->priv->percpu_pools) { in mvpp2_xdp_setup()
5356 if (port->ntxqs < num_possible_cpus() * 2) { in mvpp2_xdp_setup()
5363 mvpp2_stop(port->dev); in mvpp2_xdp_setup()
5365 old_prog = xchg(&port->xdp_prog, prog); in mvpp2_xdp_setup()
5375 mvpp2_open(port->dev); in mvpp2_xdp_setup()
5378 mvpp2_check_pagepool_dma(port); in mvpp2_xdp_setup()
5385 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_xdp() local
5389 return mvpp2_xdp_setup(port, xdp); in mvpp2_xdp()
5399 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_nway_reset() local
5401 if (!port->phylink) in mvpp2_ethtool_nway_reset()
5404 return phylink_ethtool_nway_reset(port->phylink); in mvpp2_ethtool_nway_reset()
5414 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_coalesce() local
5417 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_ethtool_set_coalesce()
5418 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_ethtool_set_coalesce()
5422 mvpp2_rx_pkts_coal_set(port, rxq); in mvpp2_ethtool_set_coalesce()
5423 mvpp2_rx_time_coal_set(port, rxq); in mvpp2_ethtool_set_coalesce()
5426 if (port->has_tx_irqs) { in mvpp2_ethtool_set_coalesce()
5427 port->tx_time_coal = c->tx_coalesce_usecs; in mvpp2_ethtool_set_coalesce()
5428 mvpp2_tx_time_coal_set(port); in mvpp2_ethtool_set_coalesce()
5431 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_ethtool_set_coalesce()
5432 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_ethtool_set_coalesce()
5436 if (port->has_tx_irqs) in mvpp2_ethtool_set_coalesce()
5437 mvpp2_tx_pkts_coal_set(port, txq); in mvpp2_ethtool_set_coalesce()
5450 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_coalesce() local
5452 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; in mvpp2_ethtool_get_coalesce()
5453 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; in mvpp2_ethtool_get_coalesce()
5454 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; in mvpp2_ethtool_get_coalesce()
5455 c->tx_coalesce_usecs = port->tx_time_coal; in mvpp2_ethtool_get_coalesce()
5476 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_ringparam() local
5480 ring->rx_pending = port->rx_ring_size; in mvpp2_ethtool_get_ringparam()
5481 ring->tx_pending = port->tx_ring_size; in mvpp2_ethtool_get_ringparam()
5490 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_ringparam() local
5491 u16 prev_rx_ring_size = port->rx_ring_size; in mvpp2_ethtool_set_ringparam()
5492 u16 prev_tx_ring_size = port->tx_ring_size; in mvpp2_ethtool_set_ringparam()
5500 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5501 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5508 mvpp2_stop_dev(port); in mvpp2_ethtool_set_ringparam()
5509 mvpp2_cleanup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5510 mvpp2_cleanup_txqs(port); in mvpp2_ethtool_set_ringparam()
5512 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5513 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5515 err = mvpp2_setup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5518 port->rx_ring_size = prev_rx_ring_size; in mvpp2_ethtool_set_ringparam()
5520 err = mvpp2_setup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5524 err = mvpp2_setup_txqs(port); in mvpp2_ethtool_set_ringparam()
5527 port->tx_ring_size = prev_tx_ring_size; in mvpp2_ethtool_set_ringparam()
5529 err = mvpp2_setup_txqs(port); in mvpp2_ethtool_set_ringparam()
5534 mvpp2_start_dev(port); in mvpp2_ethtool_set_ringparam()
5535 mvpp2_egress_enable(port); in mvpp2_ethtool_set_ringparam()
5536 mvpp2_ingress_enable(port); in mvpp2_ethtool_set_ringparam()
5541 mvpp2_cleanup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5550 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_pause_param() local
5552 if (!port->phylink) in mvpp2_ethtool_get_pause_param()
5555 phylink_ethtool_get_pauseparam(port->phylink, pause); in mvpp2_ethtool_get_pause_param()
5561 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_pause_param() local
5563 if (!port->phylink) in mvpp2_ethtool_set_pause_param()
5566 return phylink_ethtool_set_pauseparam(port->phylink, pause); in mvpp2_ethtool_set_pause_param()
5572 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_link_ksettings() local
5574 if (!port->phylink) in mvpp2_ethtool_get_link_ksettings()
5577 return phylink_ethtool_ksettings_get(port->phylink, cmd); in mvpp2_ethtool_get_link_ksettings()
5583 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_link_ksettings() local
5585 if (!port->phylink) in mvpp2_ethtool_set_link_ksettings()
5588 return phylink_ethtool_ksettings_set(port->phylink, cmd); in mvpp2_ethtool_set_link_ksettings()
5594 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_rxnfc() local
5597 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_get_rxnfc()
5602 ret = mvpp2_ethtool_rxfh_get(port, info); in mvpp2_ethtool_get_rxnfc()
5605 info->data = port->nrxqs; in mvpp2_ethtool_get_rxnfc()
5608 info->rule_cnt = port->n_rfs_rules; in mvpp2_ethtool_get_rxnfc()
5611 ret = mvpp2_ethtool_cls_rule_get(port, info); in mvpp2_ethtool_get_rxnfc()
5620 if (port->rfs_rules[i]) in mvpp2_ethtool_get_rxnfc()
5634 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_rxnfc() local
5637 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_set_rxnfc()
5642 ret = mvpp2_ethtool_rxfh_set(port, info); in mvpp2_ethtool_set_rxnfc()
5645 ret = mvpp2_ethtool_cls_rule_ins(port, info); in mvpp2_ethtool_set_rxnfc()
5648 ret = mvpp2_ethtool_cls_rule_del(port, info); in mvpp2_ethtool_set_rxnfc()
5658 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_rxfh_indir_size() local
5660 return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0; in mvpp2_ethtool_get_rxfh_indir_size()
5666 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_rxfh() local
5670 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_get_rxfh()
5678 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, in mvpp2_ethtool_get_rxfh()
5684 static bool mvpp2_ethtool_rxfh_okay(struct mvpp2_port *port, in mvpp2_ethtool_rxfh_okay() argument
5687 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_rxfh_okay()
5705 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_create_rxfh_context() local
5708 if (!mvpp2_ethtool_rxfh_okay(port, rxfh)) in mvpp2_create_rxfh_context()
5713 ret = mvpp22_port_rss_ctx_create(port, rxfh->rss_context); in mvpp2_create_rxfh_context()
5718 ret = mvpp22_port_rss_ctx_indir_get(port, rxfh->rss_context, in mvpp2_create_rxfh_context()
5721 ret = mvpp22_port_rss_ctx_indir_set(port, rxfh->rss_context, in mvpp2_create_rxfh_context()
5731 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_modify_rxfh_context() local
5734 if (!mvpp2_ethtool_rxfh_okay(port, rxfh)) in mvpp2_modify_rxfh_context()
5738 ret = mvpp22_port_rss_ctx_indir_set(port, rxfh->rss_context, in mvpp2_modify_rxfh_context()
5748 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_remove_rxfh_context() local
5750 return mvpp22_port_rss_ctx_delete(port, rss_context); in mvpp2_remove_rxfh_context()
5763 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_eee() local
5765 if (!port->phylink) in mvpp2_ethtool_get_eee()
5768 return phylink_ethtool_get_eee(port->phylink, eee); in mvpp2_ethtool_get_eee()
5774 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_eee() local
5776 if (!port->phylink) in mvpp2_ethtool_set_eee()
5779 return phylink_ethtool_set_eee(port->phylink, eee); in mvpp2_ethtool_set_eee()
5832 * had a single IRQ defined per-port.
5834 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, in mvpp2_simple_queue_vectors_init() argument
5837 struct mvpp2_queue_vector *v = &port->qvecs[0]; in mvpp2_simple_queue_vectors_init()
5840 v->nrxqs = port->nrxqs; in mvpp2_simple_queue_vectors_init()
5844 v->port = port; in mvpp2_simple_queue_vectors_init()
5848 netif_napi_add(port->dev, &v->napi, mvpp2_poll); in mvpp2_simple_queue_vectors_init()
5850 port->nqvecs = 1; in mvpp2_simple_queue_vectors_init()
5855 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, in mvpp2_multi_queue_vectors_init() argument
5858 struct mvpp2 *priv = port->priv; in mvpp2_multi_queue_vectors_init()
5864 port->nqvecs = priv->nthreads + 1; in mvpp2_multi_queue_vectors_init()
5867 port->nqvecs = priv->nthreads; in mvpp2_multi_queue_vectors_init()
5871 for (i = 0; i < port->nqvecs; i++) { in mvpp2_multi_queue_vectors_init()
5874 v = port->qvecs + i; in mvpp2_multi_queue_vectors_init()
5876 v->port = port; in mvpp2_multi_queue_vectors_init()
5881 if (port->flags & MVPP2_F_DT_COMPAT) in mvpp2_multi_queue_vectors_init()
5890 i == (port->nqvecs - 1)) { in mvpp2_multi_queue_vectors_init()
5892 v->nrxqs = port->nrxqs; in mvpp2_multi_queue_vectors_init()
5895 if (port->flags & MVPP2_F_DT_COMPAT) in mvpp2_multi_queue_vectors_init()
5902 v->irq = fwnode_irq_get(port->fwnode, i); in mvpp2_multi_queue_vectors_init()
5908 netif_napi_add(port->dev, &v->napi, mvpp2_poll); in mvpp2_multi_queue_vectors_init()
5914 for (i = 0; i < port->nqvecs; i++) in mvpp2_multi_queue_vectors_init()
5915 irq_dispose_mapping(port->qvecs[i].irq); in mvpp2_multi_queue_vectors_init()
5919 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, in mvpp2_queue_vectors_init() argument
5922 if (port->has_tx_irqs) in mvpp2_queue_vectors_init()
5923 return mvpp2_multi_queue_vectors_init(port, port_node); in mvpp2_queue_vectors_init()
5925 return mvpp2_simple_queue_vectors_init(port, port_node); in mvpp2_queue_vectors_init()
5928 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) in mvpp2_queue_vectors_deinit() argument
5932 for (i = 0; i < port->nqvecs; i++) in mvpp2_queue_vectors_deinit()
5933 irq_dispose_mapping(port->qvecs[i].irq); in mvpp2_queue_vectors_deinit()
5936 /* Configure Rx queue group interrupt for this port */
5937 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) in mvpp2_rx_irqs_setup() argument
5939 struct mvpp2 *priv = port->priv; in mvpp2_rx_irqs_setup()
5944 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), in mvpp2_rx_irqs_setup()
5945 port->nrxqs); in mvpp2_rx_irqs_setup()
5950 for (i = 0; i < port->nqvecs; i++) { in mvpp2_rx_irqs_setup()
5951 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_rx_irqs_setup()
5957 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; in mvpp2_rx_irqs_setup()
5966 /* Initialize port HW */
5967 static int mvpp2_port_init(struct mvpp2_port *port) in mvpp2_port_init() argument
5969 struct device *dev = port->dev->dev.parent; in mvpp2_port_init()
5970 struct mvpp2 *priv = port->priv; in mvpp2_port_init()
5976 if (port->first_rxq + port->nrxqs > in mvpp2_port_init()
5980 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) in mvpp2_port_init()
5983 /* Disable port */ in mvpp2_port_init()
5984 mvpp2_egress_disable(port); in mvpp2_port_init()
5985 mvpp2_port_disable(port); in mvpp2_port_init()
5987 if (mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_init()
5988 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()
5991 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()
5993 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_init()
5996 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_init()
5999 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; in mvpp2_port_init()
6001 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), in mvpp2_port_init()
6003 if (!port->txqs) in mvpp2_port_init()
6006 /* Associate physical Tx queues to this port and initialize. in mvpp2_port_init()
6009 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_port_init()
6010 int queue_phy_id = mvpp2_txq_phys(port->id, queue); in mvpp2_port_init()
6033 port->txqs[queue] = txq; in mvpp2_port_init()
6036 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), in mvpp2_port_init()
6038 if (!port->rxqs) { in mvpp2_port_init()
6043 /* Allocate and initialize Rx queue for this port */ in mvpp2_port_init()
6044 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_port_init()
6047 /* Map physical Rx queue to port's logical Rx queue */ in mvpp2_port_init()
6054 rxq->id = port->first_rxq + queue; in mvpp2_port_init()
6055 rxq->port = port->id; in mvpp2_port_init()
6058 port->rxqs[queue] = rxq; in mvpp2_port_init()
6061 mvpp2_rx_irqs_setup(port); in mvpp2_port_init()
6064 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_port_init()
6065 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_port_init()
6067 rxq->size = port->rx_ring_size; in mvpp2_port_init()
6072 mvpp2_ingress_disable(port); in mvpp2_port_init()
6074 /* Port default configuration */ in mvpp2_port_init()
6075 mvpp2_defaults_set(port); in mvpp2_port_init()
6077 /* Port's classifier configuration */ in mvpp2_port_init()
6078 mvpp2_cls_oversize_rxq_set(port); in mvpp2_port_init()
6079 mvpp2_cls_port_config(port); in mvpp2_port_init()
6081 if (mvpp22_rss_is_supported(port)) in mvpp2_port_init()
6082 mvpp22_port_rss_init(port); in mvpp2_port_init()
6085 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); in mvpp2_port_init()
6088 err = mvpp2_swf_bm_pool_init(port); in mvpp2_port_init()
6092 /* Clear all port stats */ in mvpp2_port_init()
6093 mvpp2_read_stats(port); in mvpp2_port_init()
6094 memset(port->ethtool_stats, 0, in mvpp2_port_init()
6095 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); in mvpp2_port_init()
6100 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_port_init()
6101 if (!port->txqs[queue]) in mvpp2_port_init()
6103 free_percpu(port->txqs[queue]->pcpu); in mvpp2_port_init()
6124 /* Checks if the port dt description has the required Tx interrupts:
6163 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_port_copy_mac_addr() local
6175 mvpp21_get_mac_address(port, hw_mac_addr); in mvpp2_port_copy_mac_addr()
6218 struct mvpp2_port *port = mvpp2_pcs_xlg_to_port(pcs); in mvpp2_xlg_pcs_get_state() local
6221 if (port->phy_interface == PHY_INTERFACE_MODE_5GBASER) in mvpp2_xlg_pcs_get_state()
6228 val = readl(port->base + MVPP22_XLG_STATUS); in mvpp2_xlg_pcs_get_state()
6232 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_pcs_get_state()
6278 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs); in mvpp2_gmac_pcs_get_state() local
6281 val = readl(port->base + MVPP2_GMAC_STATUS0); in mvpp2_gmac_pcs_get_state()
6287 switch (port->phy_interface) { in mvpp2_gmac_pcs_get_state()
6315 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs); in mvpp2_gmac_pcs_config() local
6357 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_config()
6361 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_config()
6369 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs); in mvpp2_gmac_pcs_an_restart() local
6370 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_an_restart()
6373 port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_an_restart()
6375 port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_an_restart()
6385 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, in mvpp2_xlg_config() argument
6390 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_xlg_config()
6393 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG, in mvpp2_xlg_config()
6401 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()
6405 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, in mvpp2_gmac_config() argument
6412 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_config()
6413 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_gmac_config()
6414 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); in mvpp2_gmac_config()
6419 /* Configure port type */ in mvpp2_gmac_config()
6457 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_config()
6459 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_gmac_config()
6461 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); in mvpp2_gmac_config()
6467 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_select_pcs() local
6474 return &port->pcs_xlg; in mvpp2_select_pcs()
6476 return &port->pcs_gmac; in mvpp2_select_pcs()
6482 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_prepare() local
6485 if (mvpp2_is_xlg(interface) && port->gop_id != 0) { in mvpp2_mac_prepare()
6486 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name); in mvpp2_mac_prepare()
6490 if (port->phy_interface != interface || in mvpp2_mac_prepare()
6498 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, in mvpp2_mac_prepare()
6503 if (mvpp2_port_supports_xlg(port)) in mvpp2_mac_prepare()
6504 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_mac_prepare()
6510 /* Make sure the port is disabled when reconfiguring the mode */ in mvpp2_mac_prepare()
6511 mvpp2_port_disable(port); in mvpp2_mac_prepare()
6513 if (port->phy_interface != interface) { in mvpp2_mac_prepare()
6515 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, in mvpp2_mac_prepare()
6519 if (port->priv->hw_version >= MVPP22) { in mvpp2_mac_prepare()
6520 mvpp22_gop_mask_irq(port); in mvpp2_mac_prepare()
6522 phy_power_off(port->comphy); in mvpp2_mac_prepare()
6525 mvpp22_mode_reconfigure(port, interface); in mvpp2_mac_prepare()
6535 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_config() local
6539 mvpp2_xlg_config(port, mode, state); in mvpp2_mac_config()
6543 mvpp2_gmac_config(port, mode, state); in mvpp2_mac_config()
6545 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) in mvpp2_mac_config()
6546 mvpp2_port_loopback_set(port, state); in mvpp2_mac_config()
6552 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_finish() local
6554 if (port->priv->hw_version >= MVPP22 && in mvpp2_mac_finish()
6555 port->phy_interface != interface) { in mvpp2_mac_finish()
6556 port->phy_interface = interface; in mvpp2_mac_finish()
6559 mvpp22_gop_unmask_irq(port); in mvpp2_mac_finish()
6564 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, in mvpp2_mac_finish()
6567 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_mac_finish()
6572 mvpp2_port_enable(port); in mvpp2_mac_finish()
6579 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_mac_finish()
6583 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, in mvpp2_mac_finish()
6597 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_link_up() local
6609 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_mac_link_up()
6627 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, in mvpp2_mac_link_up()
6645 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG, in mvpp2_mac_link_up()
6650 if (port->priv->global_tx_fc) { in mvpp2_mac_link_up()
6651 port->tx_fc = tx_pause; in mvpp2_mac_link_up()
6653 mvpp2_rxq_enable_fc(port); in mvpp2_mac_link_up()
6655 mvpp2_rxq_disable_fc(port); in mvpp2_mac_link_up()
6656 if (port->priv->percpu_pools) { in mvpp2_mac_link_up()
6657 for (i = 0; i < port->nrxqs; i++) in mvpp2_mac_link_up()
6658 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause); in mvpp2_mac_link_up()
6660 mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause); in mvpp2_mac_link_up()
6661 mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause); in mvpp2_mac_link_up()
6663 if (port->priv->hw_version == MVPP23) in mvpp2_mac_link_up()
6664 mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause); in mvpp2_mac_link_up()
6667 mvpp2_port_enable(port); in mvpp2_mac_link_up()
6669 mvpp2_egress_enable(port); in mvpp2_mac_link_up()
6670 mvpp2_ingress_enable(port); in mvpp2_mac_link_up()
6671 netif_tx_wake_all_queues(port->dev); in mvpp2_mac_link_up()
6677 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_link_down() local
6682 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_link_down()
6685 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_link_down()
6687 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_mac_link_down()
6690 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_mac_link_down()
6694 netif_tx_stop_all_queues(port->dev); in mvpp2_mac_link_down()
6695 mvpp2_egress_disable(port); in mvpp2_mac_link_down()
6696 mvpp2_ingress_disable(port); in mvpp2_mac_link_down()
6698 mvpp2_port_disable(port); in mvpp2_mac_link_down()
6703 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_disable_tx_lpi() local
6705 mvpp2_modify(port->base + MVPP2_GMAC_LPI_CTRL1, in mvpp2_mac_disable_tx_lpi()
6712 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_enable_tx_lpi() local
6715 status = readl(port->base + MVPP2_GMAC_STATUS0); in mvpp2_mac_enable_tx_lpi()
6734 mvpp2_modify(port->base + MVPP2_GMAC_LPI_CTRL0, in mvpp2_mac_enable_tx_lpi()
6738 lpi1 = readl(port->base + MVPP2_GMAC_LPI_CTRL1); in mvpp2_mac_enable_tx_lpi()
6745 port->base + MVPP2_GMAC_LPI_CTRL1); in mvpp2_mac_enable_tx_lpi()
6762 static void mvpp2_acpi_start(struct mvpp2_port *port) in mvpp2_acpi_start() argument
6769 .interface = port->phy_interface, in mvpp2_acpi_start()
6773 pcs = mvpp2_select_pcs(&port->phylink_config, port->phy_interface); in mvpp2_acpi_start()
6775 mvpp2_mac_prepare(&port->phylink_config, MLO_AN_INBAND, in mvpp2_acpi_start()
6776 port->phy_interface); in mvpp2_acpi_start()
6777 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); in mvpp2_acpi_start()
6779 port->phy_interface, state.advertising, in mvpp2_acpi_start()
6781 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND, in mvpp2_acpi_start()
6782 port->phy_interface); in mvpp2_acpi_start()
6783 mvpp2_mac_link_up(&port->phylink_config, NULL, in mvpp2_acpi_start()
6784 MLO_AN_INBAND, port->phy_interface, in mvpp2_acpi_start()
6788 /* In order to ensure backward compatibility for ACPI, check if the port
6807 struct mvpp2_port *port; in mvpp2_port_probe() local
6831 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); in mvpp2_port_probe()
6862 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { in mvpp2_port_probe()
6864 dev_err(&pdev->dev, "missing port-id value\n"); in mvpp2_port_probe()
6873 port = netdev_priv(dev); in mvpp2_port_probe()
6874 port->dev = dev; in mvpp2_port_probe()
6875 port->fwnode = port_fwnode; in mvpp2_port_probe()
6876 port->ntxqs = ntxqs; in mvpp2_port_probe()
6877 port->nrxqs = nrxqs; in mvpp2_port_probe()
6878 port->priv = priv; in mvpp2_port_probe()
6879 port->has_tx_irqs = has_tx_irqs; in mvpp2_port_probe()
6880 port->flags = flags; in mvpp2_port_probe()
6882 err = mvpp2_queue_vectors_init(port, port_node); in mvpp2_port_probe()
6887 port->port_irq = of_irq_get_byname(port_node, "link"); in mvpp2_port_probe()
6889 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); in mvpp2_port_probe()
6890 if (port->port_irq == -EPROBE_DEFER) { in mvpp2_port_probe()
6894 if (port->port_irq <= 0) in mvpp2_port_probe()
6896 port->port_irq = 0; in mvpp2_port_probe()
6899 port->flags |= MVPP2_F_LOOPBACK; in mvpp2_port_probe()
6901 port->id = id; in mvpp2_port_probe()
6903 port->first_rxq = port->id * port->nrxqs; in mvpp2_port_probe()
6905 port->first_rxq = port->id * priv->max_port_rxqs; in mvpp2_port_probe()
6907 port->of_node = port_node; in mvpp2_port_probe()
6908 port->phy_interface = phy_mode; in mvpp2_port_probe()
6909 port->comphy = comphy; in mvpp2_port_probe()
6912 port->base = devm_platform_ioremap_resource(pdev, 2 + id); in mvpp2_port_probe()
6913 if (IS_ERR(port->base)) { in mvpp2_port_probe()
6914 err = PTR_ERR(port->base); in mvpp2_port_probe()
6918 port->stats_base = port->priv->lms_base + in mvpp2_port_probe()
6920 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; in mvpp2_port_probe()
6922 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", in mvpp2_port_probe()
6923 &port->gop_id)) { in mvpp2_port_probe()
6925 dev_err(&pdev->dev, "missing gop-port-id value\n"); in mvpp2_port_probe()
6929 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); in mvpp2_port_probe()
6930 port->stats_base = port->priv->iface_base + in mvpp2_port_probe()
6932 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; in mvpp2_port_probe()
6938 port->hwtstamp = true; in mvpp2_port_probe()
6942 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); in mvpp2_port_probe()
6943 if (!port->stats) { in mvpp2_port_probe()
6948 port->ethtool_stats = devm_kcalloc(&pdev->dev, in mvpp2_port_probe()
6951 if (!port->ethtool_stats) { in mvpp2_port_probe()
6956 mutex_init(&port->gather_stats_lock); in mvpp2_port_probe()
6957 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); in mvpp2_port_probe()
6963 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; in mvpp2_port_probe()
6964 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; in mvpp2_port_probe()
6967 err = mvpp2_port_init(port); in mvpp2_port_probe()
6969 dev_err(&pdev->dev, "failed to init port %d\n", id); in mvpp2_port_probe()
6973 mvpp2_port_periodic_xon_disable(port); in mvpp2_port_probe()
6975 mvpp2_mac_reset_assert(port); in mvpp2_port_probe()
6976 mvpp22_pcs_reset_assert(port); in mvpp2_port_probe()
6978 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); in mvpp2_port_probe()
6979 if (!port->pcpu) { in mvpp2_port_probe()
6984 if (!port->has_tx_irqs) { in mvpp2_port_probe()
6986 port_pcpu = per_cpu_ptr(port->pcpu, thread); in mvpp2_port_probe()
7002 if (mvpp22_rss_is_supported(port)) { in mvpp2_port_probe()
7007 if (!port->priv->percpu_pools) in mvpp2_port_probe()
7008 mvpp2_set_hw_csum(port, port->pool_long->id); in mvpp2_port_probe()
7009 else if (port->ntxqs >= num_possible_cpus() * 2) in mvpp2_port_probe()
7024 dev->dev_port = port->id; in mvpp2_port_probe()
7026 port->pcs_gmac.ops = &mvpp2_phylink_gmac_pcs_ops; in mvpp2_port_probe()
7027 port->pcs_gmac.neg_mode = true; in mvpp2_port_probe()
7028 port->pcs_xlg.ops = &mvpp2_phylink_xlg_pcs_ops; in mvpp2_port_probe()
7029 port->pcs_xlg.neg_mode = true; in mvpp2_port_probe()
7032 port->phylink_config.dev = &dev->dev; in mvpp2_port_probe()
7033 port->phylink_config.type = PHYLINK_NETDEV; in mvpp2_port_probe()
7034 port->phylink_config.mac_capabilities = in mvpp2_port_probe()
7038 port->phylink_config.lpi_interfaces); in mvpp2_port_probe()
7040 port->phylink_config.lpi_capabilities = MAC_1000FD | MAC_100FD; in mvpp2_port_probe()
7043 port->phylink_config.lpi_timer_default = 250; in mvpp2_port_probe()
7044 port->phylink_config.eee_enabled_default = true; in mvpp2_port_probe()
7046 if (port->priv->global_tx_fc) in mvpp2_port_probe()
7047 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
7050 if (mvpp2_port_supports_xlg(port)) { in mvpp2_port_probe()
7056 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7058 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7060 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7063 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7066 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7069 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7073 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
7076 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
7079 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
7083 if (mvpp2_port_supports_rgmii(port)) { in mvpp2_port_probe()
7084 phy_interface_set_rgmii(port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7086 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7094 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7096 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7098 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7102 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7108 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7110 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
7113 phylink = phylink_create(&port->phylink_config, port_fwnode, in mvpp2_port_probe()
7119 port->phylink = phylink; in mvpp2_port_probe()
7121 mvpp2_mac_disable_tx_lpi(&port->phylink_config); in mvpp2_port_probe()
7123 dev_warn(&pdev->dev, "Use link irqs for port#%d. FW update required\n", port->id); in mvpp2_port_probe()
7124 port->phylink = NULL; in mvpp2_port_probe()
7127 /* Cycle the comphy to power it down, saving 270mW per port - in mvpp2_port_probe()
7131 if (port->comphy) { in mvpp2_port_probe()
7132 err = mvpp22_comphy_init(port, port->phy_interface); in mvpp2_port_probe()
7134 phy_power_off(port->comphy); in mvpp2_port_probe()
7144 priv->port_list[priv->port_count++] = port; in mvpp2_port_probe()
7149 if (port->phylink) in mvpp2_port_probe()
7150 phylink_destroy(port->phylink); in mvpp2_port_probe()
7152 free_percpu(port->pcpu); in mvpp2_port_probe()
7154 for (i = 0; i < port->ntxqs; i++) in mvpp2_port_probe()
7155 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_probe()
7157 free_percpu(port->stats); in mvpp2_port_probe()
7159 if (port->port_irq) in mvpp2_port_probe()
7160 irq_dispose_mapping(port->port_irq); in mvpp2_port_probe()
7162 mvpp2_queue_vectors_deinit(port); in mvpp2_port_probe()
7169 static void mvpp2_port_remove(struct mvpp2_port *port) in mvpp2_port_remove() argument
7173 unregister_netdev(port->dev); in mvpp2_port_remove()
7174 if (port->phylink) in mvpp2_port_remove()
7175 phylink_destroy(port->phylink); in mvpp2_port_remove()
7176 free_percpu(port->pcpu); in mvpp2_port_remove()
7177 free_percpu(port->stats); in mvpp2_port_remove()
7178 for (i = 0; i < port->ntxqs; i++) in mvpp2_port_remove()
7179 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_remove()
7180 mvpp2_queue_vectors_deinit(port); in mvpp2_port_remove()
7181 if (port->port_irq) in mvpp2_port_remove()
7182 irq_dispose_mapping(port->port_irq); in mvpp2_port_remove()
7183 free_netdev(port->dev); in mvpp2_port_remove()
7222 int port; in mvpp2_rx_fifo_init() local
7224 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_rx_fifo_init()
7225 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
7227 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
7236 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size) in mvpp22_rx_fifo_set_hw() argument
7240 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size); in mvpp22_rx_fifo_set_hw()
7241 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size); in mvpp22_rx_fifo_set_hw()
7245 * 4kB fixed space must be assigned for the loopback port.
7247 * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
7255 int port, size; in mvpp22_rx_fifo_init() local
7263 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) in mvpp22_rx_fifo_init()
7264 mvpp22_rx_fifo_set_hw(priv, port, 0); in mvpp22_rx_fifo_init()
7270 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { in mvpp22_rx_fifo_init()
7273 else if (port == 0) in mvpp22_rx_fifo_init()
7276 else if (port == 1) in mvpp22_rx_fifo_init()
7285 mvpp22_rx_fifo_set_hw(priv, port, size); in mvpp22_rx_fifo_init()
7296 int port, val; in mvpp23_rx_fifo_fc_set_tresh() local
7298 /* Port 0: maximum speed -10Gb/s port in mvpp23_rx_fifo_fc_set_tresh()
7300 * Port 1: maximum speed -5Gb/s port in mvpp23_rx_fifo_fc_set_tresh()
7302 * Port 2: maximum speed -1Gb/s port in mvpp23_rx_fifo_fc_set_tresh()
7306 /* Without loopback port */ in mvpp23_rx_fifo_fc_set_tresh()
7307 for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) { in mvpp23_rx_fifo_fc_set_tresh()
7308 if (port == 0) { in mvpp23_rx_fifo_fc_set_tresh()
7312 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); in mvpp23_rx_fifo_fc_set_tresh()
7313 } else if (port == 1) { in mvpp23_rx_fifo_fc_set_tresh()
7317 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); in mvpp23_rx_fifo_fc_set_tresh()
7322 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); in mvpp23_rx_fifo_fc_set_tresh()
7328 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en) in mvpp23_rx_fifo_fc_en() argument
7332 val = mvpp2_read(priv, MVPP2_RX_FC_REG(port)); in mvpp23_rx_fifo_fc_en()
7339 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); in mvpp23_rx_fifo_fc_en()
7342 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size) in mvpp22_tx_fifo_set_hw() argument
7346 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); in mvpp22_tx_fifo_set_hw()
7347 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold); in mvpp22_tx_fifo_set_hw()
7351 * 1kB fixed space must be assigned for the loopback port.
7354 * per single port).
7361 int port, size; in mvpp22_tx_fifo_init() local
7369 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) in mvpp22_tx_fifo_init()
7370 mvpp22_tx_fifo_set_hw(priv, port, 0); in mvpp22_tx_fifo_init()
7376 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { in mvpp22_tx_fifo_init()
7380 else if (port == 0) in mvpp22_tx_fifo_init()
7388 mvpp22_tx_fifo_set_hw(priv, port, size); in mvpp22_tx_fifo_init()
7718 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i)) in mvpp2_probe()