Lines Matching full:c2
487 /* The default RxQ for this port is set in the C2 lookup */ in mvpp2_cls_flow_lkp_init()
491 * the C2 lookup. in mvpp2_cls_flow_lkp_init()
495 /* CLS is always enabled, RSS is enabled/disabled in C2 lookup */ in mvpp2_cls_flow_lkp_init()
502 struct mvpp2_cls_c2_entry *c2) in mvpp2_cls_c2_write() argument
505 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_IDX, c2->index); in mvpp2_cls_c2_write()
508 if (c2->valid) in mvpp2_cls_c2_write()
514 mvpp2_write(priv, MVPP22_CLS_C2_ACT, c2->act); in mvpp2_cls_c2_write()
516 mvpp2_write(priv, MVPP22_CLS_C2_ATTR0, c2->attr[0]); in mvpp2_cls_c2_write()
517 mvpp2_write(priv, MVPP22_CLS_C2_ATTR1, c2->attr[1]); in mvpp2_cls_c2_write()
518 mvpp2_write(priv, MVPP22_CLS_C2_ATTR2, c2->attr[2]); in mvpp2_cls_c2_write()
519 mvpp2_write(priv, MVPP22_CLS_C2_ATTR3, c2->attr[3]); in mvpp2_cls_c2_write()
521 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA0, c2->tcam[0]); in mvpp2_cls_c2_write()
522 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA1, c2->tcam[1]); in mvpp2_cls_c2_write()
523 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA2, c2->tcam[2]); in mvpp2_cls_c2_write()
524 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA3, c2->tcam[3]); in mvpp2_cls_c2_write()
526 mvpp2_write(priv, MVPP22_CLS_C2_TCAM_DATA4, c2->tcam[4]); in mvpp2_cls_c2_write()
530 struct mvpp2_cls_c2_entry *c2) in mvpp2_cls_c2_read() argument
535 c2->index = index; in mvpp2_cls_c2_read()
537 c2->tcam[0] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA0); in mvpp2_cls_c2_read()
538 c2->tcam[1] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA1); in mvpp2_cls_c2_read()
539 c2->tcam[2] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA2); in mvpp2_cls_c2_read()
540 c2->tcam[3] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA3); in mvpp2_cls_c2_read()
541 c2->tcam[4] = mvpp2_read(priv, MVPP22_CLS_C2_TCAM_DATA4); in mvpp2_cls_c2_read()
543 c2->act = mvpp2_read(priv, MVPP22_CLS_C2_ACT); in mvpp2_cls_c2_read()
545 c2->attr[0] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR0); in mvpp2_cls_c2_read()
546 c2->attr[1] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR1); in mvpp2_cls_c2_read()
547 c2->attr[2] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR2); in mvpp2_cls_c2_read()
548 c2->attr[3] = mvpp2_read(priv, MVPP22_CLS_C2_ATTR3); in mvpp2_cls_c2_read()
551 c2->valid = !(val & MVPP22_CLS_C2_TCAM_INV_BIT); in mvpp2_cls_c2_read()
601 /* RSS config C2 lookup */ in mvpp2_cls_flow_init()
869 struct mvpp2_cls_c2_entry c2; in mvpp2_port_c2_cls_init() local
872 memset(&c2, 0, sizeof(c2)); in mvpp2_port_c2_cls_init()
874 c2.index = MVPP22_CLS_C2_RSS_ENTRY(port->id); in mvpp2_port_c2_cls_init()
877 c2.tcam[4] = MVPP22_CLS_C2_PORT_ID(pmap); in mvpp2_port_c2_cls_init()
878 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_PORT_ID(pmap)); in mvpp2_port_c2_cls_init()
881 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_LU_TYPE(MVPP2_CLS_LU_TYPE_MASK)); in mvpp2_port_c2_cls_init()
882 c2.tcam[4] |= MVPP22_CLS_C2_LU_TYPE(MVPP22_CLS_LU_TYPE_ALL); in mvpp2_port_c2_cls_init()
885 c2.act = MVPP22_CLS_C2_ACT_RSS_EN(MVPP22_C2_UPD_LOCK); in mvpp2_port_c2_cls_init()
888 c2.act |= MVPP22_CLS_C2_ACT_FWD(MVPP22_C2_FWD_SW_LOCK); in mvpp2_port_c2_cls_init()
893 c2.act |= MVPP22_CLS_C2_ACT_QHIGH(MVPP22_C2_UPD) | in mvpp2_port_c2_cls_init()
899 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) | in mvpp2_port_c2_cls_init()
902 c2.valid = true; in mvpp2_port_c2_cls_init()
904 mvpp2_cls_c2_write(port->priv, &c2); in mvpp2_port_c2_cls_init()
912 struct mvpp2_cls_c2_entry c2; in mvpp2_cls_init() local
936 /* Clear C2 TCAM engine table */ in mvpp2_cls_init()
937 memset(&c2, 0, sizeof(c2)); in mvpp2_cls_init()
938 c2.valid = false; in mvpp2_cls_init()
940 c2.index = index; in mvpp2_cls_init()
941 mvpp2_cls_c2_write(priv, &c2); in mvpp2_cls_init()
944 /* Disable the FIFO stages in C2 engine, which are only used in BIST in mvpp2_cls_init()
992 struct mvpp2_cls_c2_entry c2; in mvpp2_rss_port_c2_enable() local
995 mvpp2_cls_c2_read(port->priv, MVPP22_CLS_C2_RSS_ENTRY(port->id), &c2); in mvpp2_rss_port_c2_enable()
1003 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) | in mvpp2_rss_port_c2_enable()
1006 c2.attr[2] |= MVPP22_CLS_C2_ATTR2_RSS_EN; in mvpp2_rss_port_c2_enable()
1008 mvpp2_cls_c2_write(port->priv, &c2); in mvpp2_rss_port_c2_enable()
1013 struct mvpp2_cls_c2_entry c2; in mvpp2_rss_port_c2_disable() local
1016 mvpp2_cls_c2_read(port->priv, MVPP22_CLS_C2_RSS_ENTRY(port->id), &c2); in mvpp2_rss_port_c2_disable()
1022 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) | in mvpp2_rss_port_c2_disable()
1025 c2.attr[2] &= ~MVPP22_CLS_C2_ATTR2_RSS_EN; in mvpp2_rss_port_c2_disable()
1027 mvpp2_cls_c2_write(port->priv, &c2); in mvpp2_rss_port_c2_disable()
1057 struct mvpp2_cls_c2_entry c2; in mvpp22_port_c2_lookup_disable() local
1059 mvpp2_cls_c2_read(port->priv, entry, &c2); in mvpp22_port_c2_lookup_disable()
1062 c2.tcam[4] &= ~(MVPP22_CLS_C2_PORT_ID(BIT(port->id))); in mvpp22_port_c2_lookup_disable()
1064 mvpp2_cls_c2_write(port->priv, &c2); in mvpp22_port_c2_lookup_disable()
1087 struct mvpp2_cls_c2_entry c2; in mvpp2_port_c2_tcam_rule_add() local
1094 memset(&c2, 0, sizeof(c2)); in mvpp2_port_c2_tcam_rule_add()
1099 c2.index = index; in mvpp2_port_c2_tcam_rule_add()
1103 rule->c2_index = c2.index; in mvpp2_port_c2_tcam_rule_add()
1105 c2.tcam[3] = (rule->c2_tcam & 0xffff) | in mvpp2_port_c2_tcam_rule_add()
1107 c2.tcam[2] = ((rule->c2_tcam >> 16) & 0xffff) | in mvpp2_port_c2_tcam_rule_add()
1109 c2.tcam[1] = ((rule->c2_tcam >> 32) & 0xffff) | in mvpp2_port_c2_tcam_rule_add()
1111 c2.tcam[0] = ((rule->c2_tcam >> 48) & 0xffff) | in mvpp2_port_c2_tcam_rule_add()
1115 c2.tcam[4] = MVPP22_CLS_C2_PORT_ID(pmap); in mvpp2_port_c2_tcam_rule_add()
1116 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_PORT_ID(pmap)); in mvpp2_port_c2_tcam_rule_add()
1119 c2.tcam[4] |= MVPP22_CLS_C2_TCAM_EN(MVPP22_CLS_C2_LU_TYPE(MVPP2_CLS_LU_TYPE_MASK)); in mvpp2_port_c2_tcam_rule_add()
1120 c2.tcam[4] |= MVPP22_CLS_C2_LU_TYPE(rule->loc); in mvpp2_port_c2_tcam_rule_add()
1123 c2.act = MVPP22_CLS_C2_ACT_COLOR(MVPP22_C2_COL_RED_LOCK); in mvpp2_port_c2_tcam_rule_add()
1130 c2.act = MVPP22_CLS_C2_ACT_COLOR(MVPP22_C2_COL_NO_UPD_LOCK); in mvpp2_port_c2_tcam_rule_add()
1134 c2.attr[2] |= MVPP22_CLS_C2_ATTR2_RSS_EN; in mvpp2_port_c2_tcam_rule_add()
1140 c2.act = MVPP22_CLS_C2_ACT_RSS_EN(MVPP22_C2_UPD_LOCK); in mvpp2_port_c2_tcam_rule_add()
1143 c2.act |= MVPP22_CLS_C2_ACT_FWD(MVPP22_C2_FWD_SW_LOCK); in mvpp2_port_c2_tcam_rule_add()
1145 c2.act |= MVPP22_CLS_C2_ACT_QHIGH(MVPP22_C2_UPD_LOCK) | in mvpp2_port_c2_tcam_rule_add()
1163 c2.attr[0] = MVPP22_CLS_C2_ATTR0_QHIGH(qh) | in mvpp2_port_c2_tcam_rule_add()
1167 c2.valid = true; in mvpp2_port_c2_tcam_rule_add()
1169 mvpp2_cls_c2_write(port->priv, &c2); in mvpp2_port_c2_tcam_rule_add()
1248 /* The order of insertion in C2 tcam must match the order in which in mvpp2_cls_c2_build_match()
1331 /* For now, only use the C2 engine which has a HEK size limited to 64 in mvpp2_cls_rfs_parse_rule()