Lines Matching full:ppv2

3  * Definitions for Marvell PPv2 network controller for Armada 375 SoC.
490 /* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
527 /* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
531 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
603 /* XPCS registers.PPv2.2 and PPv2.3 */
614 /* FCA registers. PPv2.2 and PPv2.3 */
623 /* XPCS registers. PPv2.2 and PPv2.3 */
630 /* PTP registers. PPv2.2 only */
1039 	/* On PPv2.2 and PPv2.3, each "software thread" can access the base
1046 	/* On PPv2.2 and PPv2.3, some port control registers are located into
1197 	 * of view. This is specific to PPv2.2.
1316 /* HW TX descriptor for PPv2.1 */
1328 /* HW RX descriptor for PPv2.1 */
1344 /* HW TX descriptor for PPv2.2 and PPv2.3 */
1356 /* HW RX descriptor for PPv2.2 and PPv2.3 */