Lines Matching +full:tcs +full:- +full:wait
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
9 * ixgbe_cache_ring_dcb_sriov - Descriptor ring to register mapping for SR-IOV
12 * Cache the descriptor ring offsets for SR-IOV to the assigned rings. It
20 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_cache_ring_dcb_sriov()
22 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; in ixgbe_cache_ring_dcb_sriov()
25 u8 tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb_sriov() local
28 if (tcs <= 1) in ixgbe_cache_ring_dcb_sriov()
32 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_cache_ring_dcb_sriov()
35 /* start at VMDq register offset for SR-IOV enabled setups */ in ixgbe_cache_ring_dcb_sriov()
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
37 for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
41 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
43 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
44 adapter->rx_ring[i]->netdev = pool ? NULL : adapter->netdev; in ixgbe_cache_ring_dcb_sriov()
47 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
48 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
51 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
52 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
57 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) in ixgbe_cache_ring_dcb_sriov()
61 if (fcoe->offset < tcs) in ixgbe_cache_ring_dcb_sriov()
65 if (fcoe->indices) { in ixgbe_cache_ring_dcb_sriov()
66 u16 queues_per_pool = __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
69 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; in ixgbe_cache_ring_dcb_sriov()
70 for (i = fcoe->offset; i < adapter->num_rx_queues; i++) { in ixgbe_cache_ring_dcb_sriov()
71 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; in ixgbe_cache_ring_dcb_sriov()
72 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
73 adapter->rx_ring[i]->netdev = adapter->netdev; in ixgbe_cache_ring_dcb_sriov()
77 reg_idx = (vmdq->offset + vmdq->indices) * queues_per_pool; in ixgbe_cache_ring_dcb_sriov()
78 for (i = fcoe->offset; i < adapter->num_tx_queues; i++) { in ixgbe_cache_ring_dcb_sriov()
79 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask) + fcoe_tc; in ixgbe_cache_ring_dcb_sriov()
80 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
89 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
93 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_get_first_reg_idx()
94 u8 num_tcs = adapter->hw_tcs; in ixgbe_get_first_reg_idx()
99 switch (hw->mac.type) { in ixgbe_get_first_reg_idx()
113 * TCs : TC0/1 TC2/3 TC4-7 in ixgbe_get_first_reg_idx()
126 * TCs : TC0 TC1 TC2/3 in ixgbe_get_first_reg_idx()
143 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
151 u8 num_tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb()
159 rss_i = adapter->ring_feature[RING_F_RSS].indices; in ixgbe_cache_ring_dcb()
164 adapter->tx_ring[offset + i]->reg_idx = tx_idx; in ixgbe_cache_ring_dcb()
165 adapter->rx_ring[offset + i]->reg_idx = rx_idx; in ixgbe_cache_ring_dcb()
166 adapter->rx_ring[offset + i]->netdev = adapter->netdev; in ixgbe_cache_ring_dcb()
167 adapter->tx_ring[offset + i]->dcb_tc = tc; in ixgbe_cache_ring_dcb()
168 adapter->rx_ring[offset + i]->dcb_tc = tc; in ixgbe_cache_ring_dcb()
177 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
180 * SR-IOV doesn't use any descriptor rings but changes the default if
187 struct ixgbe_ring_feature *fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_cache_ring_sriov()
189 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; in ixgbe_cache_ring_sriov()
190 struct ixgbe_ring_feature *rss = &adapter->ring_feature[RING_F_RSS]; in ixgbe_cache_ring_sriov()
195 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)) in ixgbe_cache_ring_sriov()
198 /* start at VMDq register offset for SR-IOV enabled setups */ in ixgbe_cache_ring_sriov()
200 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_sriov()
201 for (i = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_sriov()
204 if (fcoe->offset && (i > fcoe->offset)) in ixgbe_cache_ring_sriov()
208 if ((reg_idx & ~vmdq->mask) >= rss->indices) { in ixgbe_cache_ring_sriov()
210 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_sriov()
212 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
213 adapter->rx_ring[i]->netdev = pool ? NULL : adapter->netdev; in ixgbe_cache_ring_sriov()
218 for (; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_sriov()
219 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
220 adapter->rx_ring[i]->netdev = adapter->netdev; in ixgbe_cache_ring_sriov()
224 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_sriov()
225 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_sriov()
228 if (fcoe->offset && (i > fcoe->offset)) in ixgbe_cache_ring_sriov()
232 if ((reg_idx & rss->mask) >= rss->indices) in ixgbe_cache_ring_sriov()
233 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_sriov()
234 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
239 for (; i < adapter->num_tx_queues; i++, reg_idx++) in ixgbe_cache_ring_sriov()
240 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_sriov()
248 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
258 for (i = 0; i < adapter->num_rx_queues; i++) { in ixgbe_cache_ring_rss()
259 adapter->rx_ring[i]->reg_idx = i; in ixgbe_cache_ring_rss()
260 adapter->rx_ring[i]->netdev = adapter->netdev; in ixgbe_cache_ring_rss()
262 for (i = 0, reg_idx = 0; i < adapter->num_tx_queues; i++, reg_idx++) in ixgbe_cache_ring_rss()
263 adapter->tx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_rss()
264 for (i = 0; i < adapter->num_xdp_queues; i++, reg_idx++) in ixgbe_cache_ring_rss()
265 adapter->xdp_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_rss()
271 * ixgbe_cache_ring_register - Descriptor ring to register mapping
274 * Once we know the feature-set enabled for the device, we'll cache
284 adapter->rx_ring[0]->reg_idx = 0; in ixgbe_cache_ring_register()
285 adapter->tx_ring[0]->reg_idx = 0; in ixgbe_cache_ring_register()
306 return adapter->xdp_prog ? queues : 0; in ixgbe_xdp_queues()
318 * ixgbe_set_dcb_sriov_queues: Allocate queues for SR-IOV devices w/ DCB
321 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
329 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; in ixgbe_set_dcb_sriov_queues()
334 u8 tcs = adapter->hw_tcs; in ixgbe_set_dcb_sriov_queues() local
337 if (tcs <= 1) in ixgbe_set_dcb_sriov_queues()
341 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_set_dcb_sriov_queues()
345 vmdq_i = min_t(u16, vmdq_i, MAX_TX_QUEUES / tcs); in ixgbe_set_dcb_sriov_queues()
348 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_dcb_sriov_queues()
351 if (tcs > 4) { in ixgbe_set_dcb_sriov_queues()
362 fcoe_i = (128 / __ALIGN_MASK(1, ~vmdq_m)) - vmdq_i; in ixgbe_set_dcb_sriov_queues()
366 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_dcb_sriov_queues()
369 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; in ixgbe_set_dcb_sriov_queues()
370 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; in ixgbe_set_dcb_sriov_queues()
376 adapter->ring_feature[RING_F_RSS].indices = 1; in ixgbe_set_dcb_sriov_queues()
377 adapter->ring_feature[RING_F_RSS].mask = IXGBE_RSS_DISABLED_MASK; in ixgbe_set_dcb_sriov_queues()
380 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_dcb_sriov_queues()
382 adapter->num_rx_pools = vmdq_i; in ixgbe_set_dcb_sriov_queues()
383 adapter->num_rx_queues_per_pool = tcs; in ixgbe_set_dcb_sriov_queues()
385 adapter->num_tx_queues = vmdq_i * tcs; in ixgbe_set_dcb_sriov_queues()
386 adapter->num_xdp_queues = 0; in ixgbe_set_dcb_sriov_queues()
387 adapter->num_rx_queues = vmdq_i * tcs; in ixgbe_set_dcb_sriov_queues()
390 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_dcb_sriov_queues()
393 fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_dcb_sriov_queues()
396 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); in ixgbe_set_dcb_sriov_queues()
400 fcoe->indices = fcoe_i; in ixgbe_set_dcb_sriov_queues()
401 fcoe->offset = vmdq_i * tcs; in ixgbe_set_dcb_sriov_queues()
404 adapter->num_tx_queues += fcoe_i; in ixgbe_set_dcb_sriov_queues()
405 adapter->num_rx_queues += fcoe_i; in ixgbe_set_dcb_sriov_queues()
406 } else if (tcs > 1) { in ixgbe_set_dcb_sriov_queues()
408 fcoe->indices = 1; in ixgbe_set_dcb_sriov_queues()
409 fcoe->offset = ixgbe_fcoe_get_tc(adapter); in ixgbe_set_dcb_sriov_queues()
411 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; in ixgbe_set_dcb_sriov_queues()
413 fcoe->indices = 0; in ixgbe_set_dcb_sriov_queues()
414 fcoe->offset = 0; in ixgbe_set_dcb_sriov_queues()
420 for (i = 0; i < tcs; i++) in ixgbe_set_dcb_sriov_queues()
421 netdev_set_tc_queue(adapter->netdev, i, 1, i); in ixgbe_set_dcb_sriov_queues()
428 struct net_device *dev = adapter->netdev; in ixgbe_set_dcb_queues()
431 int tcs; in ixgbe_set_dcb_queues() local
434 tcs = adapter->hw_tcs; in ixgbe_set_dcb_queues()
437 if (tcs <= 1) in ixgbe_set_dcb_queues()
441 rss_i = dev->num_tx_queues / tcs; in ixgbe_set_dcb_queues()
442 if (adapter->hw.mac.type == ixgbe_mac_82598EB) { in ixgbe_set_dcb_queues()
446 } else if (tcs > 4) { in ixgbe_set_dcb_queues()
457 f = &adapter->ring_feature[RING_F_RSS]; in ixgbe_set_dcb_queues()
458 rss_i = min_t(int, rss_i, f->limit); in ixgbe_set_dcb_queues()
459 f->indices = rss_i; in ixgbe_set_dcb_queues()
460 f->mask = rss_m; in ixgbe_set_dcb_queues()
462 /* disable ATR as it is not supported when multiple TCs are enabled */ in ixgbe_set_dcb_queues()
463 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_dcb_queues()
471 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_dcb_queues()
474 f = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_dcb_queues()
475 f->indices = min_t(u16, rss_i, f->limit); in ixgbe_set_dcb_queues()
476 f->offset = rss_i * tc; in ixgbe_set_dcb_queues()
480 for (i = 0; i < tcs; i++) in ixgbe_set_dcb_queues()
483 adapter->num_tx_queues = rss_i * tcs; in ixgbe_set_dcb_queues()
484 adapter->num_xdp_queues = 0; in ixgbe_set_dcb_queues()
485 adapter->num_rx_queues = rss_i * tcs; in ixgbe_set_dcb_queues()
492 * ixgbe_set_sriov_queues - Allocate queues for SR-IOV devices
495 * When SR-IOV (Single Root IO Virtualiztion) is enabled, allocate queues
502 u16 vmdq_i = adapter->ring_feature[RING_F_VMDQ].limit; in ixgbe_set_sriov_queues()
504 u16 rss_i = adapter->ring_feature[RING_F_RSS].limit; in ixgbe_set_sriov_queues()
510 /* only proceed if SR-IOV is enabled */ in ixgbe_set_sriov_queues()
511 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) in ixgbe_set_sriov_queues()
518 vmdq_i += adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_sriov_queues()
538 fcoe_i = 128 - (vmdq_i * __ALIGN_MASK(1, ~vmdq_m)); in ixgbe_set_sriov_queues()
542 vmdq_i -= adapter->ring_feature[RING_F_VMDQ].offset; in ixgbe_set_sriov_queues()
545 adapter->ring_feature[RING_F_VMDQ].indices = vmdq_i; in ixgbe_set_sriov_queues()
546 adapter->ring_feature[RING_F_VMDQ].mask = vmdq_m; in ixgbe_set_sriov_queues()
549 adapter->ring_feature[RING_F_RSS].indices = rss_i; in ixgbe_set_sriov_queues()
550 adapter->ring_feature[RING_F_RSS].mask = rss_m; in ixgbe_set_sriov_queues()
552 adapter->num_rx_pools = vmdq_i; in ixgbe_set_sriov_queues()
553 adapter->num_rx_queues_per_pool = rss_i; in ixgbe_set_sriov_queues()
555 adapter->num_rx_queues = vmdq_i * rss_i; in ixgbe_set_sriov_queues()
556 adapter->num_tx_queues = vmdq_i * rss_i; in ixgbe_set_sriov_queues()
557 adapter->num_xdp_queues = 0; in ixgbe_set_sriov_queues()
560 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_sriov_queues()
568 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_sriov_queues()
571 fcoe = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_sriov_queues()
574 fcoe_i = min_t(u16, fcoe_i, fcoe->limit); in ixgbe_set_sriov_queues()
578 fcoe->indices = fcoe_i; in ixgbe_set_sriov_queues()
579 fcoe->offset = vmdq_i * rss_i; in ixgbe_set_sriov_queues()
584 /* limit indices to rss_i if MSI-X is disabled */ in ixgbe_set_sriov_queues()
585 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) in ixgbe_set_sriov_queues()
589 fcoe->indices = min_t(u16, fcoe_i, fcoe->limit); in ixgbe_set_sriov_queues()
590 fcoe->offset = fcoe_i - fcoe->indices; in ixgbe_set_sriov_queues()
592 fcoe_i -= rss_i; in ixgbe_set_sriov_queues()
596 adapter->num_tx_queues += fcoe_i; in ixgbe_set_sriov_queues()
597 adapter->num_rx_queues += fcoe_i; in ixgbe_set_sriov_queues()
607 netdev_set_num_tc(adapter->netdev, 1); in ixgbe_set_sriov_queues()
610 netdev_set_tc_queue(adapter->netdev, 0, in ixgbe_set_sriov_queues()
611 adapter->num_rx_queues_per_pool, 0); in ixgbe_set_sriov_queues()
617 * ixgbe_set_rss_queues - Allocate queues for RSS
626 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_set_rss_queues()
631 f = &adapter->ring_feature[RING_F_RSS]; in ixgbe_set_rss_queues()
632 rss_i = f->limit; in ixgbe_set_rss_queues()
634 f->indices = rss_i; in ixgbe_set_rss_queues()
636 if (hw->mac.type < ixgbe_mac_X550) in ixgbe_set_rss_queues()
637 f->mask = IXGBE_RSS_16Q_MASK; in ixgbe_set_rss_queues()
639 f->mask = IXGBE_RSS_64Q_MASK; in ixgbe_set_rss_queues()
642 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_rss_queues()
649 if (rss_i > 1 && adapter->atr_sample_rate) { in ixgbe_set_rss_queues()
650 f = &adapter->ring_feature[RING_F_FDIR]; in ixgbe_set_rss_queues()
652 rss_i = f->indices = f->limit; in ixgbe_set_rss_queues()
654 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) in ixgbe_set_rss_queues()
655 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; in ixgbe_set_rss_queues()
667 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { in ixgbe_set_rss_queues()
668 struct net_device *dev = adapter->netdev; in ixgbe_set_rss_queues()
671 f = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_set_rss_queues()
674 fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus()); in ixgbe_set_rss_queues()
675 fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues); in ixgbe_set_rss_queues()
677 /* limit indices to rss_i if MSI-X is disabled */ in ixgbe_set_rss_queues()
678 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) in ixgbe_set_rss_queues()
682 f->indices = min_t(u16, fcoe_i, f->limit); in ixgbe_set_rss_queues()
683 f->offset = fcoe_i - f->indices; in ixgbe_set_rss_queues()
688 adapter->num_rx_queues = rss_i; in ixgbe_set_rss_queues()
689 adapter->num_tx_queues = rss_i; in ixgbe_set_rss_queues()
690 adapter->num_xdp_queues = ixgbe_xdp_queues(adapter); in ixgbe_set_rss_queues()
696 * ixgbe_set_num_queues - Allocate queues for device, feature dependent
709 adapter->num_rx_queues = 1; in ixgbe_set_num_queues()
710 adapter->num_tx_queues = 1; in ixgbe_set_num_queues()
711 adapter->num_xdp_queues = 0; in ixgbe_set_num_queues()
712 adapter->num_rx_pools = 1; in ixgbe_set_num_queues()
713 adapter->num_rx_queues_per_pool = 1; in ixgbe_set_num_queues()
730 * ixgbe_acquire_msix_vectors - acquire MSI-X vectors
733 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
734 * return a negative error code if unable to acquire MSI-X vectors for any
739 struct ixgbe_hw *hw = &adapter->hw; in ixgbe_acquire_msix_vectors()
745 vectors = max(adapter->num_rx_queues, adapter->num_tx_queues); in ixgbe_acquire_msix_vectors()
746 vectors = max(vectors, adapter->num_xdp_queues); in ixgbe_acquire_msix_vectors()
748 /* It is easy to be greedy for MSI-X vectors. However, it really in ixgbe_acquire_msix_vectors()
755 /* Some vectors are necessary for non-queue interrupts */ in ixgbe_acquire_msix_vectors()
758 /* Hardware can only support a maximum of hw.mac->max_msix_vectors. in ixgbe_acquire_msix_vectors()
764 vectors = min_t(int, vectors, hw->mac.max_msix_vectors); in ixgbe_acquire_msix_vectors()
766 /* We want a minimum of two MSI-X vectors for (1) a TxQ[0] + RxQ[0] in ixgbe_acquire_msix_vectors()
771 adapter->msix_entries = kcalloc(vectors, in ixgbe_acquire_msix_vectors()
774 if (!adapter->msix_entries) in ixgbe_acquire_msix_vectors()
775 return -ENOMEM; in ixgbe_acquire_msix_vectors()
778 adapter->msix_entries[i].entry = i; in ixgbe_acquire_msix_vectors()
780 vectors = pci_enable_msix_range(adapter->pdev, adapter->msix_entries, in ixgbe_acquire_msix_vectors()
785 * acquiring within the specified range of MSI-X vectors in ixgbe_acquire_msix_vectors()
787 e_dev_warn("Failed to allocate MSI-X interrupts. Err: %d\n", in ixgbe_acquire_msix_vectors()
790 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; in ixgbe_acquire_msix_vectors()
791 kfree(adapter->msix_entries); in ixgbe_acquire_msix_vectors()
792 adapter->msix_entries = NULL; in ixgbe_acquire_msix_vectors()
800 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; in ixgbe_acquire_msix_vectors()
805 vectors -= NON_Q_VECTORS; in ixgbe_acquire_msix_vectors()
806 adapter->num_q_vectors = min_t(int, vectors, adapter->max_q_vectors); in ixgbe_acquire_msix_vectors()
814 ring->next = head->ring; in ixgbe_add_ring()
815 head->ring = ring; in ixgbe_add_ring()
816 head->count++; in ixgbe_add_ring()
817 head->next_update = jiffies + 1; in ixgbe_add_ring()
821 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
832 * We allocate one q_vector. If allocation fails we return -ENOMEM.
840 int node = dev_to_node(&adapter->pdev->dev); in ixgbe_alloc_q_vector()
843 int cpu = -1; in ixgbe_alloc_q_vector()
845 u8 tcs = adapter->hw_tcs; in ixgbe_alloc_q_vector() local
850 if ((tcs <= 1) && !(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { in ixgbe_alloc_q_vector()
851 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; in ixgbe_alloc_q_vector()
852 if (rss_i > 1 && adapter->atr_sample_rate) { in ixgbe_alloc_q_vector()
865 return -ENOMEM; in ixgbe_alloc_q_vector()
868 if (cpu != -1) in ixgbe_alloc_q_vector()
869 cpumask_set_cpu(cpu, &q_vector->affinity_mask); in ixgbe_alloc_q_vector()
870 q_vector->numa_node = node; in ixgbe_alloc_q_vector()
874 q_vector->cpu = -1; in ixgbe_alloc_q_vector()
878 netif_napi_add(adapter->netdev, &q_vector->napi, ixgbe_poll); in ixgbe_alloc_q_vector()
881 adapter->q_vector[v_idx] = q_vector; in ixgbe_alloc_q_vector()
882 q_vector->adapter = adapter; in ixgbe_alloc_q_vector()
883 q_vector->v_idx = v_idx; in ixgbe_alloc_q_vector()
886 q_vector->tx.work_limit = adapter->tx_work_limit; in ixgbe_alloc_q_vector()
889 q_vector->tx.itr = IXGBE_ITR_ADAPTIVE_MAX_USECS | in ixgbe_alloc_q_vector()
891 q_vector->rx.itr = IXGBE_ITR_ADAPTIVE_MAX_USECS | in ixgbe_alloc_q_vector()
897 if (adapter->tx_itr_setting == 1) in ixgbe_alloc_q_vector()
898 q_vector->itr = IXGBE_12K_ITR; in ixgbe_alloc_q_vector()
900 q_vector->itr = adapter->tx_itr_setting; in ixgbe_alloc_q_vector()
903 if (adapter->rx_itr_setting == 1) in ixgbe_alloc_q_vector()
904 q_vector->itr = IXGBE_20K_ITR; in ixgbe_alloc_q_vector()
906 q_vector->itr = adapter->rx_itr_setting; in ixgbe_alloc_q_vector()
910 ring = q_vector->ring; in ixgbe_alloc_q_vector()
914 ring->dev = &adapter->pdev->dev; in ixgbe_alloc_q_vector()
915 ring->netdev = adapter->netdev; in ixgbe_alloc_q_vector()
918 ring->q_vector = q_vector; in ixgbe_alloc_q_vector()
921 ixgbe_add_ring(ring, &q_vector->tx); in ixgbe_alloc_q_vector()
924 ring->count = adapter->tx_ring_count; in ixgbe_alloc_q_vector()
925 ring->queue_index = txr_idx; in ixgbe_alloc_q_vector()
928 WRITE_ONCE(adapter->tx_ring[txr_idx], ring); in ixgbe_alloc_q_vector()
931 txr_count--; in ixgbe_alloc_q_vector()
940 ring->dev = &adapter->pdev->dev; in ixgbe_alloc_q_vector()
941 ring->netdev = adapter->netdev; in ixgbe_alloc_q_vector()
944 ring->q_vector = q_vector; in ixgbe_alloc_q_vector()
947 ixgbe_add_ring(ring, &q_vector->tx); in ixgbe_alloc_q_vector()
950 ring->count = adapter->tx_ring_count; in ixgbe_alloc_q_vector()
951 ring->queue_index = xdp_idx; in ixgbe_alloc_q_vector()
953 spin_lock_init(&ring->tx_lock); in ixgbe_alloc_q_vector()
956 WRITE_ONCE(adapter->xdp_ring[xdp_idx], ring); in ixgbe_alloc_q_vector()
959 xdp_count--; in ixgbe_alloc_q_vector()
968 ring->dev = &adapter->pdev->dev; in ixgbe_alloc_q_vector()
969 ring->netdev = adapter->netdev; in ixgbe_alloc_q_vector()
972 ring->q_vector = q_vector; in ixgbe_alloc_q_vector()
975 ixgbe_add_ring(ring, &q_vector->rx); in ixgbe_alloc_q_vector()
981 if (adapter->hw.mac.type == ixgbe_mac_82599EB) in ixgbe_alloc_q_vector()
982 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); in ixgbe_alloc_q_vector()
985 if (adapter->netdev->fcoe_mtu) { in ixgbe_alloc_q_vector()
987 f = &adapter->ring_feature[RING_F_FCOE]; in ixgbe_alloc_q_vector()
988 if ((rxr_idx >= f->offset) && in ixgbe_alloc_q_vector()
989 (rxr_idx < f->offset + f->indices)) in ixgbe_alloc_q_vector()
990 set_bit(__IXGBE_RX_FCOE, &ring->state); in ixgbe_alloc_q_vector()
995 ring->count = adapter->rx_ring_count; in ixgbe_alloc_q_vector()
996 ring->queue_index = rxr_idx; in ixgbe_alloc_q_vector()
999 WRITE_ONCE(adapter->rx_ring[rxr_idx], ring); in ixgbe_alloc_q_vector()
1002 rxr_count--; in ixgbe_alloc_q_vector()
1013 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
1023 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; in ixgbe_free_q_vector()
1026 ixgbe_for_each_ring(ring, q_vector->tx) { in ixgbe_free_q_vector()
1028 WRITE_ONCE(adapter->xdp_ring[ring->queue_index], NULL); in ixgbe_free_q_vector()
1030 WRITE_ONCE(adapter->tx_ring[ring->queue_index], NULL); in ixgbe_free_q_vector()
1033 ixgbe_for_each_ring(ring, q_vector->rx) in ixgbe_free_q_vector()
1034 WRITE_ONCE(adapter->rx_ring[ring->queue_index], NULL); in ixgbe_free_q_vector()
1036 adapter->q_vector[v_idx] = NULL; in ixgbe_free_q_vector()
1037 __netif_napi_del(&q_vector->napi); in ixgbe_free_q_vector()
1042 * we must wait a grace period before freeing it. in ixgbe_free_q_vector()
1048 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
1052 * return -ENOMEM.
1056 int q_vectors = adapter->num_q_vectors; in ixgbe_alloc_q_vectors()
1057 int rxr_remaining = adapter->num_rx_queues; in ixgbe_alloc_q_vectors()
1058 int txr_remaining = adapter->num_tx_queues; in ixgbe_alloc_q_vectors()
1059 int xdp_remaining = adapter->num_xdp_queues; in ixgbe_alloc_q_vectors()
1063 /* only one q_vector if MSI-X is disabled. */ in ixgbe_alloc_q_vectors()
1064 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) in ixgbe_alloc_q_vectors()
1076 rxr_remaining--; in ixgbe_alloc_q_vectors()
1082 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); in ixgbe_alloc_q_vectors()
1083 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); in ixgbe_alloc_q_vectors()
1084 int xqpv = DIV_ROUND_UP(xdp_remaining, q_vectors - v_idx); in ixgbe_alloc_q_vectors()
1095 rxr_remaining -= rqpv; in ixgbe_alloc_q_vectors()
1096 txr_remaining -= tqpv; in ixgbe_alloc_q_vectors()
1097 xdp_remaining -= xqpv; in ixgbe_alloc_q_vectors()
1103 for (i = 0; i < adapter->num_rx_queues; i++) { in ixgbe_alloc_q_vectors()
1104 if (adapter->rx_ring[i]) in ixgbe_alloc_q_vectors()
1105 adapter->rx_ring[i]->ring_idx = i; in ixgbe_alloc_q_vectors()
1108 for (i = 0; i < adapter->num_tx_queues; i++) { in ixgbe_alloc_q_vectors()
1109 if (adapter->tx_ring[i]) in ixgbe_alloc_q_vectors()
1110 adapter->tx_ring[i]->ring_idx = i; in ixgbe_alloc_q_vectors()
1113 for (i = 0; i < adapter->num_xdp_queues; i++) { in ixgbe_alloc_q_vectors()
1114 if (adapter->xdp_ring[i]) in ixgbe_alloc_q_vectors()
1115 adapter->xdp_ring[i]->ring_idx = i; in ixgbe_alloc_q_vectors()
1121 adapter->num_tx_queues = 0; in ixgbe_alloc_q_vectors()
1122 adapter->num_xdp_queues = 0; in ixgbe_alloc_q_vectors()
1123 adapter->num_rx_queues = 0; in ixgbe_alloc_q_vectors()
1124 adapter->num_q_vectors = 0; in ixgbe_alloc_q_vectors()
1126 while (v_idx--) in ixgbe_alloc_q_vectors()
1129 return -ENOMEM; in ixgbe_alloc_q_vectors()
1133 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
1142 int v_idx = adapter->num_q_vectors; in ixgbe_free_q_vectors()
1144 adapter->num_tx_queues = 0; in ixgbe_free_q_vectors()
1145 adapter->num_xdp_queues = 0; in ixgbe_free_q_vectors()
1146 adapter->num_rx_queues = 0; in ixgbe_free_q_vectors()
1147 adapter->num_q_vectors = 0; in ixgbe_free_q_vectors()
1149 while (v_idx--) in ixgbe_free_q_vectors()
1155 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { in ixgbe_reset_interrupt_capability()
1156 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; in ixgbe_reset_interrupt_capability()
1157 pci_disable_msix(adapter->pdev); in ixgbe_reset_interrupt_capability()
1158 kfree(adapter->msix_entries); in ixgbe_reset_interrupt_capability()
1159 adapter->msix_entries = NULL; in ixgbe_reset_interrupt_capability()
1160 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { in ixgbe_reset_interrupt_capability()
1161 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; in ixgbe_reset_interrupt_capability()
1162 pci_disable_msi(adapter->pdev); in ixgbe_reset_interrupt_capability()
1167 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
1177 /* We will try to get MSI-X interrupts first */ in ixgbe_set_interrupt_capability()
1181 /* At this point, we do not have MSI-X capabilities. We need to in ixgbe_set_interrupt_capability()
1182 * reconfigure or disable various features which require MSI-X in ixgbe_set_interrupt_capability()
1187 if (adapter->hw_tcs > 1) { in ixgbe_set_interrupt_capability()
1188 e_dev_warn("Number of DCB TCs exceeds number of available queues. Disabling DCB support.\n"); in ixgbe_set_interrupt_capability()
1189 netdev_reset_tc(adapter->netdev); in ixgbe_set_interrupt_capability()
1191 if (adapter->hw.mac.type == ixgbe_mac_82598EB) in ixgbe_set_interrupt_capability()
1192 adapter->hw.fc.requested_mode = adapter->last_lfc_mode; in ixgbe_set_interrupt_capability()
1194 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; in ixgbe_set_interrupt_capability()
1195 adapter->temp_dcb_cfg.pfc_mode_enable = false; in ixgbe_set_interrupt_capability()
1196 adapter->dcb_cfg.pfc_mode_enable = false; in ixgbe_set_interrupt_capability()
1199 adapter->hw_tcs = 0; in ixgbe_set_interrupt_capability()
1200 adapter->dcb_cfg.num_tcs.pg_tcs = 1; in ixgbe_set_interrupt_capability()
1201 adapter->dcb_cfg.num_tcs.pfc_tcs = 1; in ixgbe_set_interrupt_capability()
1203 /* Disable SR-IOV support */ in ixgbe_set_interrupt_capability()
1204 e_dev_warn("Disabling SR-IOV support\n"); in ixgbe_set_interrupt_capability()
1209 adapter->ring_feature[RING_F_RSS].limit = 1; in ixgbe_set_interrupt_capability()
1215 adapter->num_q_vectors = 1; in ixgbe_set_interrupt_capability()
1217 err = pci_enable_msi(adapter->pdev); in ixgbe_set_interrupt_capability()
1222 adapter->flags |= IXGBE_FLAG_MSI_ENABLED; in ixgbe_set_interrupt_capability()
1226 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
1230 * - Kernel support (MSI, MSI-X)
1231 * - which can be user-defined (via MODULE_PARAM)
1232 * - Hardware queue count (num_*_queues)
1233 * - defined by miscellaneous hardware support/features (RSS, etc.)
1254 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", in ixgbe_init_interrupt_scheme()
1255 adapter->num_rx_queues, adapter->num_tx_queues, in ixgbe_init_interrupt_scheme()
1256 adapter->num_xdp_queues); in ixgbe_init_interrupt_scheme()
1258 set_bit(__IXGBE_DOWN, &adapter->state); in ixgbe_init_interrupt_scheme()
1268 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
1272 * to pre-load conditions
1276 adapter->num_tx_queues = 0; in ixgbe_clear_interrupt_scheme()
1277 adapter->num_xdp_queues = 0; in ixgbe_clear_interrupt_scheme()
1278 adapter->num_rx_queues = 0; in ixgbe_clear_interrupt_scheme()
1288 u16 i = tx_ring->next_to_use; in ixgbe_tx_ctxtdesc()
1293 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; in ixgbe_tx_ctxtdesc()
1298 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); in ixgbe_tx_ctxtdesc()
1299 context_desc->fceof_saidx = cpu_to_le32(fceof_saidx); in ixgbe_tx_ctxtdesc()
1300 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); in ixgbe_tx_ctxtdesc()
1301 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); in ixgbe_tx_ctxtdesc()