25 	u8 tcs = adapter->hw_tcs;  in ixgbe_cache_ring_dcb_sriov()  local
28 	if (tcs <= 1)  in ixgbe_cache_ring_dcb_sriov()
39 		if ((reg_idx & ~vmdq->mask) >= tcs) {  in ixgbe_cache_ring_dcb_sriov()
50 		if ((reg_idx & ~vmdq->mask) >= tcs)  in ixgbe_cache_ring_dcb_sriov()
61 	if (fcoe->offset < tcs)  in ixgbe_cache_ring_dcb_sriov()
113 			 * TCs    : TC0/1 TC2/3 TC4-7  in ixgbe_get_first_reg_idx()
126 			 * TCs    : TC0 TC1 TC2/3  in ixgbe_get_first_reg_idx()
334 	u8 tcs = adapter->hw_tcs;  in ixgbe_set_dcb_sriov_queues()  local
337 	if (tcs <= 1)  in ixgbe_set_dcb_sriov_queues()
345 	vmdq_i = min_t(u16, vmdq_i, MAX_TX_QUEUES / tcs);  in ixgbe_set_dcb_sriov_queues()
351 	if (tcs > 4) {  in ixgbe_set_dcb_sriov_queues()
383 	adapter->num_rx_queues_per_pool = tcs;  in ixgbe_set_dcb_sriov_queues()
385 	adapter->num_tx_queues = vmdq_i * tcs;  in ixgbe_set_dcb_sriov_queues()
387 	adapter->num_rx_queues = vmdq_i * tcs;  in ixgbe_set_dcb_sriov_queues()
401 			fcoe->offset = vmdq_i * tcs;  in ixgbe_set_dcb_sriov_queues()
406 		} else if (tcs > 1) {  in ixgbe_set_dcb_sriov_queues()
420 	for (i = 0; i < tcs; i++)  in ixgbe_set_dcb_sriov_queues()
431 	int tcs;  in ixgbe_set_dcb_queues()  local
434 	tcs = adapter->hw_tcs;  in ixgbe_set_dcb_queues()
437 	if (tcs <= 1)  in ixgbe_set_dcb_queues()
441 	rss_i = dev->num_tx_queues / tcs;  in ixgbe_set_dcb_queues()
446 	} else if (tcs > 4) {  in ixgbe_set_dcb_queues()
462 	/* disable ATR as it is not supported when multiple TCs are enabled */  in ixgbe_set_dcb_queues()
480 	for (i = 0; i < tcs; i++)  in ixgbe_set_dcb_queues()
483 	adapter->num_tx_queues = rss_i * tcs;  in ixgbe_set_dcb_queues()
485 	adapter->num_rx_queues = rss_i * tcs;  in ixgbe_set_dcb_queues()
845 	u8 tcs = adapter->hw_tcs;  in ixgbe_alloc_q_vector()  local
850 	if ((tcs <= 1) && !(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {  in ixgbe_alloc_q_vector()
1188 		e_dev_warn("Number of DCB TCs exceeds number of available queues. Disabling DCB support.\n");  in ixgbe_set_interrupt_capability()