Lines Matching +full:gphy +full:- +full:fw
1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define IGC_CTRL 0x00000 /* Device Control - RW */
9 #define IGC_STATUS 0x00008 /* Device Status - RO */
10 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
11 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define IGC_MDIC 0x00020 /* MDI Control - RW */
13 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
14 #define IGC_VET 0x00038 /* VLAN Ether Type - RW */
15 #define IGC_LEDCTL 0x00E00 /* LED Control - RW */
17 #define IGC_GPHY_VERSION 0x0001E /* I225 gPHY Firmware Version */
20 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
21 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
24 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
25 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
28 #define IGC_FCAL 0x00028 /* FC Address Low - RW */
29 #define IGC_FCAH 0x0002C /* FC Address High - RW */
30 #define IGC_FCT 0x00030 /* FC Type - RW */
31 #define IGC_FCTTV 0x00170 /* FC Transmit Timer - RW */
32 #define IGC_FCRTL 0x02160 /* FC Receive Threshold Low - RW */
33 #define IGC_FCRTH 0x02168 /* FC Receive Threshold High - RW */
34 #define IGC_FCRTV 0x02460 /* FC Refresh Timer Value - RW */
37 #define IGC_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
39 #define IGC_FWSM 0x05B54 /* FW Semaphore */
45 #define IGC_EICR 0x01580 /* Ext. Interrupt Cause read - W0 */
46 #define IGC_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
47 #define IGC_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
48 #define IGC_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
49 #define IGC_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
50 #define IGC_EIAM 0x01530 /* Ext. Interrupt Auto Mask - RW */
51 #define IGC_ICR 0x01500 /* Intr Cause Read - RC/W1C */
52 #define IGC_ICS 0x01504 /* Intr Cause Set - WO */
53 #define IGC_IMS 0x01508 /* Intr Mask Set/Read - RW */
54 #define IGC_IMC 0x0150C /* Intr Mask Clear - WO */
55 #define IGC_IAM 0x01510 /* Intr Ack Auto Mask- RW */
56 /* Intr Throttle - RW */
58 /* Interrupt Vector Allocation - RW */
60 #define IGC_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
61 #define IGC_GPIE 0x01514 /* General Purpose Intr Enable - RW */
64 #define IGC_MRQC 0x05818 /* Multiple Receive Control - RW */
92 /* Redirection Table - RW Array */
94 /* RSS Random Key - RW Array */
98 #define IGC_RCTL 0x00100 /* Rx Control - RW */
108 #define IGC_RXCSUM 0x05000 /* Rx Checksum Control - RW */
111 #define IGC_MTA 0x05200 /* Multicast Table Array - RW Array */
112 #define IGC_RA 0x05400 /* Receive Address - RW Array */
113 #define IGC_UTA 0x0A000 /* Unicast Table Array - RW */
116 #define IGC_VLANPQF 0x055B0 /* VLAN Priority Queue Filter - RW */
119 #define IGC_TCTL 0x00400 /* Tx Control - RW */
120 #define IGC_TIPG 0x00410 /* Tx Inter-packet gap - RW */
133 #define IGC_CRCERRS 0x04000 /* CRC Error Count - R/clr */
134 #define IGC_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
135 #define IGC_RXERRC 0x0400C /* Receive Error Count - R/clr */
136 #define IGC_MPC 0x04010 /* Missed Packet Count - R/clr */
137 #define IGC_SCC 0x04014 /* Single Collision Count - R/clr */
138 #define IGC_ECOL 0x04018 /* Excessive Collision Count - R/clr */
139 #define IGC_MCC 0x0401C /* Multiple Collision Count - R/clr */
140 #define IGC_LATECOL 0x04020 /* Late Collision Count - R/clr */
141 #define IGC_COLC 0x04028 /* Collision Count - R/clr */
142 #define IGC_RERC 0x0402C /* Receive Error Count - R/clr */
143 #define IGC_DC 0x04030 /* Defer Count - R/clr */
144 #define IGC_TNCRS 0x04034 /* Tx-No CRS - R/clr */
145 #define IGC_HTDPMC 0x0403C /* Host Transmit Discarded by MAC - R/clr */
146 #define IGC_RLEC 0x04040 /* Receive Length Error Count - R/clr */
147 #define IGC_XONRXC 0x04048 /* XON Rx Count - R/clr */
148 #define IGC_XONTXC 0x0404C /* XON Tx Count - R/clr */
149 #define IGC_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
150 #define IGC_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
151 #define IGC_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
152 #define IGC_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
153 #define IGC_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
154 #define IGC_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
155 #define IGC_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
156 #define IGC_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
157 #define IGC_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
158 #define IGC_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
159 #define IGC_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
160 #define IGC_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
161 #define IGC_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
162 #define IGC_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
163 #define IGC_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
164 #define IGC_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
165 #define IGC_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
166 #define IGC_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
167 #define IGC_RUC 0x040A4 /* Rx Undersize Count - R/clr */
168 #define IGC_RFC 0x040A8 /* Rx Fragment Count - R/clr */
169 #define IGC_ROC 0x040AC /* Rx Oversize Count - R/clr */
170 #define IGC_RJC 0x040B0 /* Rx Jabber Count - R/clr */
171 #define IGC_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
172 #define IGC_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
173 #define IGC_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
174 #define IGC_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
175 #define IGC_TORH 0x040C4 /* Total Octets Rx High - R/clr */
176 #define IGC_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
177 #define IGC_TOTH 0x040CC /* Total Octets Tx High - R/clr */
178 #define IGC_TPR 0x040D0 /* Total Packets Rx - R/clr */
179 #define IGC_TPT 0x040D4 /* Total Packets Tx - R/clr */
180 #define IGC_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
181 #define IGC_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
182 #define IGC_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
183 #define IGC_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
184 #define IGC_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
185 #define IGC_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
186 #define IGC_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
187 #define IGC_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
188 #define IGC_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
205 #define IGC_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
206 #define IGC_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
207 #define IGC_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
208 #define IGC_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */
209 #define IGC_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */
210 #define IGC_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */
211 #define IGC_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */
212 #define IGC_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */
213 #define IGC_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */
214 #define IGC_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */
215 #define IGC_AUXSTMPL0 0x0B65C /* Auxiliary Time Stamp 0 Register Low - RO */
216 #define IGC_AUXSTMPH0 0x0B660 /* Auxiliary Time Stamp 0 Register High - RO */
217 #define IGC_AUXSTMPL1 0x0B664 /* Auxiliary Time Stamp 1 Register Low - RO */
218 #define IGC_AUXSTMPH1 0x0B668 /* Auxiliary Time Stamp 1 Register High - RO */
223 #define IGC_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
241 #define IGC_TXARB 0x3354 /* Tx Arbitration Control TxARB - RW */
244 #define IGC_SYSTIML 0x0B600 /* System time register Low - RO */
245 #define IGC_SYSTIMH 0x0B604 /* System time register High - RO */
247 #define IGC_TIMINCA 0x0B608 /* Increment attributes register - RW */
249 #define IGC_SYSTIML_1 0x0B688 /* System time register Low - RO (timer 1) */
250 #define IGC_SYSTIMH_1 0x0B68C /* System time register High - RO (timer 1) */
252 #define IGC_TIMINCA_1 0x0B690 /* Increment attributes register - RW (timer 1) */
266 #define IGC_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */
267 #define IGC_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */
293 #define IGC_MANC 0x05820 /* Management Control - RW */
295 /* Shadow Ram Write Register - RW */
299 #define IGC_WUC 0x05800 /* Wakeup Control - RW */
300 #define IGC_WUFC 0x05808 /* Wakeup Filter Control - RW */
301 #define IGC_WUS 0x05810 /* Wakeup Status - R/W1C */
302 #define IGC_WUPL 0x05900 /* Wakeup Packet Length - RW */
303 #define IGC_WUFC_EXT 0x0580C /* Wakeup Filter Control Register Extended - RW */
313 /* MULTI GBT AN Control Register - reg. 7.32 */
316 /* EEE ANeg Advertisement Register - reg 7.60 and reg 7.62 */
319 /* EEE ANeg Link-Partner Advertisement Register - reg 7.61 and reg 7.63 */
335 u8 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \