1 // SPDX-License-Identifier: GPL-2.0
11  * igc_disable_pcie_master - Disables PCI-express master access
14  * Returns 0 (0) if successful, else returns -10
15  * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18  * Disables PCI-Express master access and verifies there are no pending
36 		timeout--;  in igc_disable_pcie_master()
41 		ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING;  in igc_disable_pcie_master()
50  * igc_init_rx_addrs - Initialize receive addresses
66 	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);  in igc_init_rx_addrs()
68 	/* Zero out the other (rar_entry_count - 1) receive addresses */  in igc_init_rx_addrs()
69 	hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1);  in igc_init_rx_addrs()
71 		hw->mac.ops.rar_set(hw, mac_addr, i);  in igc_init_rx_addrs()
75  * igc_set_fc_watermarks - Set flow control high/low watermarks
78  * Sets the flow control high/low threshold (watermark) registers.  If
79  * flow control XON frame transmission is enabled, then set XON frame
86 	/* Set the flow control receive threshold registers.  Normally,  in igc_set_fc_watermarks()
92 	if (hw->fc.current_mode & igc_fc_tx_pause) {  in igc_set_fc_watermarks()
97 		fcrtl = hw->fc.low_water;  in igc_set_fc_watermarks()
98 		if (hw->fc.send_xon)  in igc_set_fc_watermarks()
101 		fcrth = hw->fc.high_water;  in igc_set_fc_watermarks()
110  * igc_setup_link - Setup flow control and link settings
113  * Determines which flow control settings to use, then configures flow
114  * control.  Calls the appropriate media-specific link configuration
129 	/* If requested flow control is set to default, set flow control  in igc_setup_link()
132 	if (hw->fc.requested_mode == igc_fc_default)  in igc_setup_link()
133 		hw->fc.requested_mode = igc_fc_full;  in igc_setup_link()
135 	/* We want to save off the original Flow Control configuration just  in igc_setup_link()
137 	 * hub or switch with different Flow Control capabilities.  in igc_setup_link()
139 	hw->fc.current_mode = hw->fc.requested_mode;  in igc_setup_link()
141 	hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);  in igc_setup_link()
144 	ret_val = hw->mac.ops.setup_physical_interface(hw);  in igc_setup_link()
148 	/* Initialize the flow control address, type, and PAUSE timer  in igc_setup_link()
149 	 * registers to their default values.  This is done even if flow  in igc_setup_link()
150 	 * control is disabled, because it does not hurt anything to  in igc_setup_link()
153 	hw_dbg("Initializing the Flow Control address, type and timer regs\n");  in igc_setup_link()
158 	wr32(IGC_FCTTV, hw->fc.pause_time);  in igc_setup_link()
167  * igc_force_mac_fc - Force the MAC's flow control settings
170  * Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
171  * device control register to reflect the adapter settings.  TFCE and RFCE
183 	/* Because we didn't get link via the internal auto-negotiation  in igc_force_mac_fc()
185 	 * auto-neg), we have to manually enable/disable transmit an  in igc_force_mac_fc()
186 	 * receive flow control.  in igc_force_mac_fc()
188 	 * The "Case" statement below enables/disable flow control  in igc_force_mac_fc()
189 	 * according to the "hw->fc.current_mode" parameter.  in igc_force_mac_fc()
192 	 *      0:  Flow control is completely disabled  in igc_force_mac_fc()
193 	 *      1:  Rx flow control is enabled (we can receive pause  in igc_force_mac_fc()
195 	 *      2:  Tx flow control is enabled (we can send pause frames  in igc_force_mac_fc()
197 	 *      3:  Both Rx and TX flow control (symmetric) is enabled.  in igc_force_mac_fc()
200 	hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);  in igc_force_mac_fc()
202 	switch (hw->fc.current_mode) {  in igc_force_mac_fc()
218 		hw_dbg("Flow control param set incorrectly\n");  in igc_force_mac_fc()
219 		ret_val = -IGC_ERR_CONFIG;  in igc_force_mac_fc()
230  * igc_clear_hw_cntrs_base - Clear base hardware counters
312  * igc_rar_set - Set receive address register
337 	/* Some bridges will combine consecutive 32-bit writes into  in igc_rar_set()
348  * igc_check_for_copper_link - Check for link (Copper)
357 	struct igc_mac_info *mac = &hw->mac;  in igc_check_for_copper_link()
361 	/* We only want to go out to the PHY registers to see if Auto-Neg  in igc_check_for_copper_link()
366 	if (!mac->get_link_status) {  in igc_check_for_copper_link()
382 	mac->get_link_status = false;  in igc_check_for_copper_link()
385 	 * immediately after link-up  in igc_check_for_copper_link()
389 	/* Auto-Neg is enabled.  Auto Speed Detection takes care  in igc_check_for_copper_link()
395 	/* Configure Flow Control now that Auto-Neg has completed.  in igc_check_for_copper_link()
396 	 * First, we need to restore the desired flow control  in igc_check_for_copper_link()
397 	 * settings because we may have had to re-autoneg with a  in igc_check_for_copper_link()
402 		hw_dbg("Error configuring flow control\n");  in igc_check_for_copper_link()
414  * igc_config_collision_dist - Configure collision distance
435  * igc_config_fc_after_link_up - Configures flow control after link
438  * Checks the status of auto-negotiation after link up to ensure that the
440  * flow control needs to be forced also.  If auto-negotiation is enabled
441  * and did not fail, then we configure flow control based on our link
447 	struct igc_mac_info *mac = &hw->mac;  in igc_config_fc_after_link_up()
451 	/* Check for the case where we have fiber media and auto-neg failed  in igc_config_fc_after_link_up()
455 	if (mac->autoneg_failed)  in igc_config_fc_after_link_up()
459 		hw_dbg("Error forcing flow control settings\n");  in igc_config_fc_after_link_up()
463 	/* In auto-neg, we need to check and see if Auto-Neg has completed,  in igc_config_fc_after_link_up()
464 	 * and if so, how the PHY and link partner has flow control  in igc_config_fc_after_link_up()
472 	ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,  in igc_config_fc_after_link_up()
476 	ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,  in igc_config_fc_after_link_up()
490 	 * flow control was negotiated.  in igc_config_fc_after_link_up()
492 	ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,  in igc_config_fc_after_link_up()
496 	ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,  in igc_config_fc_after_link_up()
502 	 * Page Ability Register (Address 5) determine flow control  in igc_config_fc_after_link_up()
505 	 * 1999, describes these PAUSE resolution bits and how flow  in igc_config_fc_after_link_up()
506 	 * control is determined based upon these settings.  in igc_config_fc_after_link_up()
511 	 *-------|---------|-------|---------|--------------------  in igc_config_fc_after_link_up()
522 	 * Symmetric Flow Control is enabled at both ends.  The  in igc_config_fc_after_link_up()
525 	 * For Symmetric Flow Control:  in igc_config_fc_after_link_up()
529 	 *-------|---------|-------|---------|--------------------  in igc_config_fc_after_link_up()
537 		 * FULL flow control because we could not advertise RX  in igc_config_fc_after_link_up()
541 		if (hw->fc.requested_mode == igc_fc_full) {  in igc_config_fc_after_link_up()
542 			hw->fc.current_mode = igc_fc_full;  in igc_config_fc_after_link_up()
543 			hw_dbg("Flow Control = FULL.\n");  in igc_config_fc_after_link_up()
545 			hw->fc.current_mode = igc_fc_rx_pause;  in igc_config_fc_after_link_up()
546 			hw_dbg("Flow Control = RX PAUSE frames only.\n");  in igc_config_fc_after_link_up()
554 	 *-------|---------|-------|---------|--------------------  in igc_config_fc_after_link_up()
561 		hw->fc.current_mode = igc_fc_tx_pause;  in igc_config_fc_after_link_up()
562 		hw_dbg("Flow Control = TX PAUSE frames only.\n");  in igc_config_fc_after_link_up()
568 	 *-------|---------|-------|---------|--------------------  in igc_config_fc_after_link_up()
575 		hw->fc.current_mode = igc_fc_rx_pause;  in igc_config_fc_after_link_up()
576 		hw_dbg("Flow Control = RX PAUSE frames only.\n");  in igc_config_fc_after_link_up()
578 	/* Per the IEEE spec, at this point flow control should be  in igc_config_fc_after_link_up()
581 	 * desired flow control, but can be forced on the link  in igc_config_fc_after_link_up()
582 	 * partner.  So if we advertised no flow control, that is  in igc_config_fc_after_link_up()
584 	 * receive capability (Rx Pause Only or Full Flow Control)  in igc_config_fc_after_link_up()
586 	 * ourselves to enable Rx Flow Control only.  We can do  in igc_config_fc_after_link_up()
588 	 * didn't want flow control enabled, and we enable Rx, no  in igc_config_fc_after_link_up()
591 	 * flow control enabled, then by us enabling RX only, we  in igc_config_fc_after_link_up()
598 	else if ((hw->fc.requested_mode == igc_fc_none) ||  in igc_config_fc_after_link_up()
599 		 (hw->fc.requested_mode == igc_fc_tx_pause) ||  in igc_config_fc_after_link_up()
600 		 (hw->fc.strict_ieee)) {  in igc_config_fc_after_link_up()
601 		hw->fc.current_mode = igc_fc_none;  in igc_config_fc_after_link_up()
602 		hw_dbg("Flow Control = NONE.\n");  in igc_config_fc_after_link_up()
604 		hw->fc.current_mode = igc_fc_rx_pause;  in igc_config_fc_after_link_up()
605 		hw_dbg("Flow Control = RX PAUSE frames only.\n");  in igc_config_fc_after_link_up()
608 	/* Now we need to do one last check...  If we auto-  in igc_config_fc_after_link_up()
609 	 * negotiated to HALF DUPLEX, flow control should not be  in igc_config_fc_after_link_up()
612 	ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);  in igc_config_fc_after_link_up()
619 		hw->fc.current_mode = igc_fc_none;  in igc_config_fc_after_link_up()
622 	 * controller to use the correct flow control settings.  in igc_config_fc_after_link_up()
626 		hw_dbg("Error forcing flow control settings\n");  in igc_config_fc_after_link_up()
635  * igc_get_auto_rd_done - Check for auto read completion
654 		ret_val = -IGC_ERR_RESET;  in igc_get_auto_rd_done()
663  * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex
682 		if (hw->mac.type == igc_i225 &&  in igc_get_speed_and_duplex_copper()
710  * igc_put_hw_semaphore - Release hardware semaphore
727  * igc_enable_mng_pass_thru - Enable processing of ARP's
739 	if (!hw->mac.asf_firmware_present)  in igc_enable_mng_pass_thru()
747 	if (hw->mac.arc_subsystem_valid) {  in igc_enable_mng_pass_thru()
770  *  igc_hash_mc_addr - Generate a multicast hash value
784 	hash_mask = (hw->mac.mta_reg_count * 32) - 1;  in igc_hash_mc_addr()
786 	/* For a mc_filter_type of 0, bit_shift is the number of left-shifts  in igc_hash_mc_addr()
796 	 * left-shifts where the MSB of mc_addr[5] would still fall within  in igc_hash_mc_addr()
799 	 * remaining number of bits. Thus 8 - bit_shift.  The rest of the  in igc_hash_mc_addr()
802 	 * 8-bit shifting total.  in igc_hash_mc_addr()
805 	 * MTA register count of 128 (thus a 4096-bit vector and 0xFFF mask),  in igc_hash_mc_addr()
817 	switch (hw->mac.mc_filter_type) {  in igc_hash_mc_addr()
832 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |  in igc_hash_mc_addr()
839  *  igc_update_mc_addr_list - Update Multicast addresses
854 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));  in igc_update_mc_addr_list()
860 		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);  in igc_update_mc_addr_list()
863 		hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);  in igc_update_mc_addr_list()
868 	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)  in igc_update_mc_addr_list()
869 		array_wr32(IGC_MTA, i, hw->mac.mta_shadow[i]);  in igc_update_mc_addr_list()