Lines Matching +full:256 +full:k

11 #define I40E_DEFAULT_IRQ_WORK      256
100 #define I40E_RXBUFFER_256   256
109  * we could have is 1K.
121  * use a 2K buffer for receives and need 1536/1534 to store the data for
126  * Note: For cache line sizes 256 or larger this value is going to end
148 	/* If a 2K buffer cannot handle a standard Ethernet frame then  in i40e_skb_pad()
149 	 * optimize padding for a 3K buffer instead of a 1.5K buffer.  in i40e_skb_pad()
151 	 * For a 3K buffer we need to add enough padding to allow for  in i40e_skb_pad()
204 /* The size limit for a transmit buffer in a descriptor is (16K - 1).
206  * the nearest 4K which represents our maximum read request size.
217  * Due to hardware alignment restrictions (4K alignment), we need to
218  * assume that we can have no more than 12K of data per descriptor, even
219  * though each descriptor can take up to 16K - 1 bytes of aligned memory.
220  * Thus, we need to divide by 12K. But division is slow! Instead,
224  * To divide by 12K, we first divide by 4K, then divide by 3:
225  *     To divide by 4K, shift right by 12 bits
226  *     To divide by 3, multiply by 85, then divide by 256
227  *     (Divide by 256 is done by shifting right by 8 bits)
228  * Finally, we add one to round up. Because 256 isn't an exact multiple of
229  * 3, we'll underestimate near each multiple of 12K. This is actually more
230  * accurate as we have 4K - 1 of wiggle room that we can fit into the last