Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) in __er16flash() argument
143 return readw(hw->flash_address + reg); in __er16flash()
146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) in __er32flash() argument
148 return readl(hw->flash_address + reg); in __er32flash()
151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) in __ew16flash() argument
153 writew(val, hw->flash_address + reg); in __ew16flash()
156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) in __ew32flash() argument
158 writel(val, hw->flash_address + reg); in __ew32flash()
161 #define er16flash(reg) __er16flash(hw, (reg))
162 #define er32flash(reg) __er32flash(hw, (reg))
163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
174 * Assumes the sw/fw/hw semaphore is already acquired.
176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) in e1000_phy_is_accessible_pchlan() argument
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); in e1000_phy_is_accessible_pchlan()
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); in e1000_phy_is_accessible_pchlan()
199 if (hw->phy.id) { in e1000_phy_is_accessible_pchlan()
200 if (hw->phy.id == phy_id) in e1000_phy_is_accessible_pchlan()
203 hw->phy.id = phy_id; in e1000_phy_is_accessible_pchlan()
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
211 if (hw->mac.type < e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
212 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
213 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_phy_is_accessible_pchlan()
215 ret_val = e1000e_get_phy_id(hw); in e1000_phy_is_accessible_pchlan()
216 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
222 if (hw->mac.type >= e1000_pch_lpt) { in e1000_phy_is_accessible_pchlan()
228 e1000e_disable_phy_retry(hw); in e1000_phy_is_accessible_pchlan()
231 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_phy_is_accessible_pchlan()
233 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_phy_is_accessible_pchlan()
235 e1000e_enable_phy_retry(hw); in e1000_phy_is_accessible_pchlan()
248 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
249 * @hw: pointer to the HW structure
251 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
254 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) in e1000_toggle_lanphypc_pch_lpt() argument
265 mac_reg = er32(CTRL); in e1000_toggle_lanphypc_pch_lpt()
268 ew32(CTRL, mac_reg); in e1000_toggle_lanphypc_pch_lpt()
272 ew32(CTRL, mac_reg); in e1000_toggle_lanphypc_pch_lpt()
275 if (hw->mac.type < e1000_pch_lpt) { in e1000_toggle_lanphypc_pch_lpt()
282 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); in e1000_toggle_lanphypc_pch_lpt()
289 * e1000_reconfigure_k1_exit_timeout - reconfigure K1 exit timeout to
291 * @hw: pointer to the HW structure
296 static s32 e1000_reconfigure_k1_exit_timeout(struct e1000_hw *hw) in e1000_reconfigure_k1_exit_timeout() argument
302 if (hw->mac.type < e1000_pch_mtp) in e1000_reconfigure_k1_exit_timeout()
315 ret_val = e1e_rphy_locked(hw, I217_PHY_TIMEOUTS_REG, in e1000_reconfigure_k1_exit_timeout()
323 return e1e_wphy_locked(hw, I217_PHY_TIMEOUTS_REG, in e1000_reconfigure_k1_exit_timeout()
328 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
329 * @hw: pointer to the HW structure
331 * Workarounds/flow necessary for PHY initialization during driver load
334 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) in e1000_init_phy_workarounds_pchlan() argument
336 struct e1000_adapter *adapter = hw->adapter; in e1000_init_phy_workarounds_pchlan()
341 * non-managed 82579 and newer adapters. in e1000_init_phy_workarounds_pchlan()
343 e1000_gate_hw_phy_config_ich8lan(hw, true); in e1000_init_phy_workarounds_pchlan()
348 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; in e1000_init_phy_workarounds_pchlan()
349 ret_val = e1000_disable_ulp_lpt_lp(hw, true); in e1000_init_phy_workarounds_pchlan()
353 ret_val = hw->phy.ops.acquire(hw); in e1000_init_phy_workarounds_pchlan()
355 e_dbg("Failed to initialize PHY flow\n"); in e1000_init_phy_workarounds_pchlan()
362 e1000e_disable_phy_retry(hw); in e1000_init_phy_workarounds_pchlan()
364 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is in e1000_init_phy_workarounds_pchlan()
368 switch (hw->mac.type) { in e1000_init_phy_workarounds_pchlan()
376 if (e1000_reconfigure_k1_exit_timeout(hw)) in e1000_init_phy_workarounds_pchlan()
385 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
403 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
408 if ((hw->mac.type == e1000_pchlan) && in e1000_init_phy_workarounds_pchlan()
412 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
414 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
419 e1000_toggle_lanphypc_pch_lpt(hw); in e1000_init_phy_workarounds_pchlan()
420 if (hw->mac.type >= e1000_pch_lpt) { in e1000_init_phy_workarounds_pchlan()
421 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
431 if (e1000_phy_is_accessible_pchlan(hw)) in e1000_init_phy_workarounds_pchlan()
434 ret_val = -E1000_ERR_PHY; in e1000_init_phy_workarounds_pchlan()
441 e1000e_enable_phy_retry(hw); in e1000_init_phy_workarounds_pchlan()
443 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
447 if (hw->phy.ops.check_reset_block(hw)) { in e1000_init_phy_workarounds_pchlan()
457 ret_val = e1000e_phy_hw_reset_generic(hw); in e1000_init_phy_workarounds_pchlan()
467 ret_val = hw->phy.ops.check_reset_block(hw); in e1000_init_phy_workarounds_pchlan()
473 if (hw->mac.type >= e1000_pch_mtp) { in e1000_init_phy_workarounds_pchlan()
474 ret_val = hw->phy.ops.acquire(hw); in e1000_init_phy_workarounds_pchlan()
479 ret_val = e1000_reconfigure_k1_exit_timeout(hw); in e1000_init_phy_workarounds_pchlan()
480 hw->phy.ops.release(hw); in e1000_init_phy_workarounds_pchlan()
485 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_init_phy_workarounds_pchlan()
486 if ((hw->mac.type == e1000_pch2lan) && in e1000_init_phy_workarounds_pchlan()
489 e1000_gate_hw_phy_config_ich8lan(hw, false); in e1000_init_phy_workarounds_pchlan()
496 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
497 * @hw: pointer to the HW structure
499 * Initialize family-specific PHY parameters and function pointers.
501 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) in e1000_init_phy_params_pchlan() argument
503 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_pchlan()
506 phy->addr = 1; in e1000_init_phy_params_pchlan()
507 phy->reset_delay_us = 100; in e1000_init_phy_params_pchlan()
509 phy->ops.set_page = e1000_set_page_igp; in e1000_init_phy_params_pchlan()
510 phy->ops.read_reg = e1000_read_phy_reg_hv; in e1000_init_phy_params_pchlan()
511 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
512 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
513 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
514 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; in e1000_init_phy_params_pchlan()
515 phy->ops.write_reg = e1000_write_phy_reg_hv; in e1000_init_phy_params_pchlan()
516 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; in e1000_init_phy_params_pchlan()
517 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; in e1000_init_phy_params_pchlan()
518 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_pchlan()
519 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_pchlan()
520 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_pchlan()
522 phy->id = e1000_phy_unknown; in e1000_init_phy_params_pchlan()
524 if (hw->mac.type == e1000_pch_mtp) { in e1000_init_phy_params_pchlan()
525 phy->retry_count = 2; in e1000_init_phy_params_pchlan()
526 e1000e_enable_phy_retry(hw); in e1000_init_phy_params_pchlan()
529 ret_val = e1000_init_phy_workarounds_pchlan(hw); in e1000_init_phy_params_pchlan()
533 if (phy->id == e1000_phy_unknown) in e1000_init_phy_params_pchlan()
534 switch (hw->mac.type) { in e1000_init_phy_params_pchlan()
536 ret_val = e1000e_get_phy_id(hw); in e1000_init_phy_params_pchlan()
539 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) in e1000_init_phy_params_pchlan()
555 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_init_phy_params_pchlan()
558 ret_val = e1000e_get_phy_id(hw); in e1000_init_phy_params_pchlan()
563 phy->type = e1000e_get_phy_type_from_id(phy->id); in e1000_init_phy_params_pchlan()
565 switch (phy->type) { in e1000_init_phy_params_pchlan()
569 phy->ops.check_polarity = e1000_check_polarity_82577; in e1000_init_phy_params_pchlan()
570 phy->ops.force_speed_duplex = in e1000_init_phy_params_pchlan()
572 phy->ops.get_cable_length = e1000_get_cable_length_82577; in e1000_init_phy_params_pchlan()
573 phy->ops.get_info = e1000_get_phy_info_82577; in e1000_init_phy_params_pchlan()
574 phy->ops.commit = e1000e_phy_sw_reset; in e1000_init_phy_params_pchlan()
577 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_pchlan()
578 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; in e1000_init_phy_params_pchlan()
579 phy->ops.get_cable_length = e1000e_get_cable_length_m88; in e1000_init_phy_params_pchlan()
580 phy->ops.get_info = e1000e_get_phy_info_m88; in e1000_init_phy_params_pchlan()
583 ret_val = -E1000_ERR_PHY; in e1000_init_phy_params_pchlan()
591 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
592 * @hw: pointer to the HW structure
594 * Initialize family-specific PHY parameters and function pointers.
596 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) in e1000_init_phy_params_ich8lan() argument
598 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_ich8lan()
602 phy->addr = 1; in e1000_init_phy_params_ich8lan()
603 phy->reset_delay_us = 100; in e1000_init_phy_params_ich8lan()
605 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_ich8lan()
606 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; in e1000_init_phy_params_ich8lan()
608 /* We may need to do this twice - once for IGP and if that fails, in e1000_init_phy_params_ich8lan()
611 ret_val = e1000e_determine_phy_address(hw); in e1000_init_phy_params_ich8lan()
613 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
614 phy->ops.read_reg = e1000e_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
615 ret_val = e1000e_determine_phy_address(hw); in e1000_init_phy_params_ich8lan()
622 phy->id = 0; in e1000_init_phy_params_ich8lan()
623 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && in e1000_init_phy_params_ich8lan()
626 ret_val = e1000e_get_phy_id(hw); in e1000_init_phy_params_ich8lan()
632 switch (phy->id) { in e1000_init_phy_params_ich8lan()
634 phy->type = e1000_phy_igp_3; in e1000_init_phy_params_ich8lan()
635 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
636 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
637 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; in e1000_init_phy_params_ich8lan()
638 phy->ops.get_info = e1000e_get_phy_info_igp; in e1000_init_phy_params_ich8lan()
639 phy->ops.check_polarity = e1000_check_polarity_igp; in e1000_init_phy_params_ich8lan()
640 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; in e1000_init_phy_params_ich8lan()
645 phy->type = e1000_phy_ife; in e1000_init_phy_params_ich8lan()
646 phy->autoneg_mask = E1000_ALL_NOT_GIG; in e1000_init_phy_params_ich8lan()
647 phy->ops.get_info = e1000_get_phy_info_ife; in e1000_init_phy_params_ich8lan()
648 phy->ops.check_polarity = e1000_check_polarity_ife; in e1000_init_phy_params_ich8lan()
649 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; in e1000_init_phy_params_ich8lan()
652 phy->type = e1000_phy_bm; in e1000_init_phy_params_ich8lan()
653 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_ich8lan()
654 phy->ops.read_reg = e1000e_read_phy_reg_bm; in e1000_init_phy_params_ich8lan()
655 phy->ops.write_reg = e1000e_write_phy_reg_bm; in e1000_init_phy_params_ich8lan()
656 phy->ops.commit = e1000e_phy_sw_reset; in e1000_init_phy_params_ich8lan()
657 phy->ops.get_info = e1000e_get_phy_info_m88; in e1000_init_phy_params_ich8lan()
658 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_ich8lan()
659 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; in e1000_init_phy_params_ich8lan()
662 return -E1000_ERR_PHY; in e1000_init_phy_params_ich8lan()
669 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
670 * @hw: pointer to the HW structure
672 * Initialize family-specific NVM parameters and function
675 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) in e1000_init_nvm_params_ich8lan() argument
677 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_init_nvm_params_ich8lan()
678 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_init_nvm_params_ich8lan()
683 nvm->type = e1000_nvm_flash_sw; in e1000_init_nvm_params_ich8lan()
685 if (hw->mac.type >= e1000_pch_spt) { in e1000_init_nvm_params_ich8lan()
692 nvm->flash_base_addr = 0; in e1000_init_nvm_params_ich8lan()
695 nvm->flash_bank_size = nvm_size / 2; in e1000_init_nvm_params_ich8lan()
697 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
699 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; in e1000_init_nvm_params_ich8lan()
702 if (!hw->flash_address) { in e1000_init_nvm_params_ich8lan()
704 return -E1000_ERR_CONFIG; in e1000_init_nvm_params_ich8lan()
709 /* sector_X_addr is a "sector"-aligned address (4096 bytes) in e1000_init_nvm_params_ich8lan()
716 /* flash_base_addr is byte-aligned */ in e1000_init_nvm_params_ich8lan()
717 nvm->flash_base_addr = sector_base_addr in e1000_init_nvm_params_ich8lan()
723 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) in e1000_init_nvm_params_ich8lan()
725 nvm->flash_bank_size /= 2; in e1000_init_nvm_params_ich8lan()
727 nvm->flash_bank_size /= sizeof(u16); in e1000_init_nvm_params_ich8lan()
730 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; in e1000_init_nvm_params_ich8lan()
733 for (i = 0; i < nvm->word_size; i++) { in e1000_init_nvm_params_ich8lan()
734 dev_spec->shadow_ram[i].modified = false; in e1000_init_nvm_params_ich8lan()
735 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_init_nvm_params_ich8lan()
742 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
743 * @hw: pointer to the HW structure
745 * Initialize family-specific MAC parameters and function
748 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) in e1000_init_mac_params_ich8lan() argument
750 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_ich8lan()
753 hw->phy.media_type = e1000_media_type_copper; in e1000_init_mac_params_ich8lan()
756 mac->mta_reg_count = 32; in e1000_init_mac_params_ich8lan()
758 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
759 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
760 mac->rar_entry_count--; in e1000_init_mac_params_ich8lan()
762 mac->has_fwsm = true; in e1000_init_mac_params_ich8lan()
764 mac->arc_subsystem_valid = false; in e1000_init_mac_params_ich8lan()
766 mac->adaptive_ifs = true; in e1000_init_mac_params_ich8lan()
769 switch (mac->type) { in e1000_init_mac_params_ich8lan()
774 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; in e1000_init_mac_params_ich8lan()
776 mac->ops.id_led_init = e1000e_id_led_init_generic; in e1000_init_mac_params_ich8lan()
778 mac->ops.blink_led = e1000e_blink_led_generic; in e1000_init_mac_params_ich8lan()
780 mac->ops.setup_led = e1000e_setup_led_generic; in e1000_init_mac_params_ich8lan()
782 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; in e1000_init_mac_params_ich8lan()
784 mac->ops.led_on = e1000_led_on_ich8lan; in e1000_init_mac_params_ich8lan()
785 mac->ops.led_off = e1000_led_off_ich8lan; in e1000_init_mac_params_ich8lan()
788 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
789 mac->ops.rar_set = e1000_rar_set_pch2lan; in e1000_init_mac_params_ich8lan()
802 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; in e1000_init_mac_params_ich8lan()
804 mac->ops.id_led_init = e1000_id_led_init_pchlan; in e1000_init_mac_params_ich8lan()
806 mac->ops.setup_led = e1000_setup_led_pchlan; in e1000_init_mac_params_ich8lan()
808 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; in e1000_init_mac_params_ich8lan()
810 mac->ops.led_on = e1000_led_on_pchlan; in e1000_init_mac_params_ich8lan()
811 mac->ops.led_off = e1000_led_off_pchlan; in e1000_init_mac_params_ich8lan()
817 if (mac->type >= e1000_pch_lpt) { in e1000_init_mac_params_ich8lan()
818 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; in e1000_init_mac_params_ich8lan()
819 mac->ops.rar_set = e1000_rar_set_pch_lpt; in e1000_init_mac_params_ich8lan()
820 mac->ops.setup_physical_interface = in e1000_init_mac_params_ich8lan()
822 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; in e1000_init_mac_params_ich8lan()
825 /* Enable PCS Lock-loss workaround for ICH8 */ in e1000_init_mac_params_ich8lan()
826 if (mac->type == e1000_ich8lan) in e1000_init_mac_params_ich8lan()
827 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); in e1000_init_mac_params_ich8lan()
833 * __e1000_access_emi_reg_locked - Read/write EMI register
834 * @hw: pointer to the HW structure
839 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
841 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, in __e1000_access_emi_reg_locked() argument
846 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); in __e1000_access_emi_reg_locked()
851 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); in __e1000_access_emi_reg_locked()
853 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); in __e1000_access_emi_reg_locked()
859 * e1000_read_emi_reg_locked - Read Extended Management Interface register
860 * @hw: pointer to the HW structure
864 * Assumes the SW/FW/HW Semaphore is already acquired.
866 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) in e1000_read_emi_reg_locked() argument
868 return __e1000_access_emi_reg_locked(hw, addr, data, true); in e1000_read_emi_reg_locked()
872 * e1000_write_emi_reg_locked - Write Extended Management Interface register
873 * @hw: pointer to the HW structure
877 * Assumes the SW/FW/HW Semaphore is already acquired.
879 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) in e1000_write_emi_reg_locked() argument
881 return __e1000_access_emi_reg_locked(hw, addr, &data, false); in e1000_write_emi_reg_locked()
885 * e1000_set_eee_pchlan - Enable/disable EEE support
886 * @hw: pointer to the HW structure
898 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) in e1000_set_eee_pchlan() argument
900 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_set_eee_pchlan()
904 switch (hw->phy.type) { in e1000_set_eee_pchlan()
919 ret_val = hw->phy.ops.acquire(hw); in e1000_set_eee_pchlan()
923 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); in e1000_set_eee_pchlan()
931 if (!dev_spec->eee_disable) { in e1000_set_eee_pchlan()
933 ret_val = e1000_read_emi_reg_locked(hw, lpa, in e1000_set_eee_pchlan()
934 &dev_spec->eee_lp_ability); in e1000_set_eee_pchlan()
939 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); in e1000_set_eee_pchlan()
946 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) in e1000_set_eee_pchlan()
949 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { in e1000_set_eee_pchlan()
950 e1e_rphy_locked(hw, MII_LPA, &data); in e1000_set_eee_pchlan()
955 * partner's EEE in 100 ability if full-duplex in e1000_set_eee_pchlan()
958 dev_spec->eee_lp_ability &= in e1000_set_eee_pchlan()
963 if (hw->phy.type == e1000_phy_82579) { in e1000_set_eee_pchlan()
964 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, in e1000_set_eee_pchlan()
970 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, in e1000_set_eee_pchlan()
974 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ in e1000_set_eee_pchlan()
975 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); in e1000_set_eee_pchlan()
979 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); in e1000_set_eee_pchlan()
981 hw->phy.ops.release(hw); in e1000_set_eee_pchlan()
987 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
988 * @hw: pointer to the HW structure
993 * the de-assertion of the clock request when in 1Gpbs mode.
994 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
997 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) in e1000_k1_workaround_lpt_lp() argument
1005 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_workaround_lpt_lp()
1010 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, in e1000_k1_workaround_lpt_lp()
1016 e1000e_write_kmrn_reg_locked(hw, in e1000_k1_workaround_lpt_lp()
1028 e1000e_write_kmrn_reg_locked(hw, in e1000_k1_workaround_lpt_lp()
1032 hw->phy.ops.release(hw); in e1000_k1_workaround_lpt_lp()
1037 if ((hw->phy.revision > 5) || !link || in e1000_k1_workaround_lpt_lp()
1042 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); in e1000_k1_workaround_lpt_lp()
1064 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); in e1000_k1_workaround_lpt_lp()
1076 * e1000_platform_pm_pch_lpt - Set platform power management values
1077 * @hw: pointer to the HW structure
1080 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1084 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1087 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1088 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1091 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) in e1000_platform_pm_pch_lpt() argument
1106 if (!hw->adapter->max_frame_size) { in e1000_platform_pm_pch_lpt()
1108 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1111 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); in e1000_platform_pm_pch_lpt()
1114 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1123 * a 3-bit encoded scale (only 0-5 are valid) multiplied by in e1000_platform_pm_pch_lpt()
1124 * a 10-bit value (0-1023) to provide a range from 1 ns to in e1000_platform_pm_pch_lpt()
1125 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, in e1000_platform_pm_pch_lpt()
1129 value = (rxa > hw->adapter->max_frame_size) ? in e1000_platform_pm_pch_lpt()
1130 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : in e1000_platform_pm_pch_lpt()
1139 return -E1000_ERR_CONFIG; in e1000_platform_pm_pch_lpt()
1144 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, in e1000_platform_pm_pch_lpt()
1146 pci_read_config_word(hw->adapter->pdev, in e1000_platform_pm_pch_lpt()
1162 /* Set Snoop and No-Snoop latencies the same */ in e1000_platform_pm_pch_lpt()
1170 * e1000e_force_smbus - Force interfaces to transition to SMBUS mode.
1171 * @hw: pointer to the HW structure
1178 static s32 e1000e_force_smbus(struct e1000_hw *hw) in e1000e_force_smbus() argument
1187 e1000e_disable_phy_retry(hw); in e1000e_force_smbus()
1190 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &smb_ctrl); in e1000e_force_smbus()
1192 e1000e_enable_phy_retry(hw); in e1000e_force_smbus()
1197 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, smb_ctrl); in e1000e_force_smbus()
1199 e1000e_enable_phy_retry(hw); in e1000e_force_smbus()
1210 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1211 * @hw: pointer to the HW structure
1219 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) in e1000_enable_ulp_lpt_lp() argument
1226 if ((hw->mac.type < e1000_pch_lpt) || in e1000_enable_ulp_lpt_lp()
1227 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_enable_ulp_lpt_lp()
1228 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_enable_ulp_lpt_lp()
1229 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || in e1000_enable_ulp_lpt_lp()
1230 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || in e1000_enable_ulp_lpt_lp()
1231 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) in e1000_enable_ulp_lpt_lp()
1248 /* Bail if link is re-acquired */ in e1000_enable_ulp_lpt_lp()
1250 return -E1000_ERR_PHY; in e1000_enable_ulp_lpt_lp()
1262 ret_val = hw->phy.ops.acquire(hw); in e1000_enable_ulp_lpt_lp()
1266 ret_val = e1000e_force_smbus(hw); in e1000_enable_ulp_lpt_lp()
1272 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable in e1000_enable_ulp_lpt_lp()
1275 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { in e1000_enable_ulp_lpt_lp()
1276 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, in e1000_enable_ulp_lpt_lp()
1284 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, in e1000_enable_ulp_lpt_lp()
1294 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); in e1000_enable_ulp_lpt_lp()
1312 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_enable_ulp_lpt_lp()
1321 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_enable_ulp_lpt_lp()
1323 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && in e1000_enable_ulp_lpt_lp()
1325 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, in e1000_enable_ulp_lpt_lp()
1332 hw->phy.ops.release(hw); in e1000_enable_ulp_lpt_lp()
1335 e_dbg("Error in ULP enable flow: %d\n", ret_val); in e1000_enable_ulp_lpt_lp()
1337 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; in e1000_enable_ulp_lpt_lp()
1343 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1344 * @hw: pointer to the HW structure
1347 * Un-configure ULP mode when link is up, the system is transitioned from
1349 * system, poll for an indication from ME that ULP has been un-configured.
1350 * If not on an ME enabled system, un-configure the ULP mode by software.
1354 * the driver or during Sx->S0 transitions, this is called with force=true
1357 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) in e1000_disable_ulp_lpt_lp() argument
1364 if ((hw->mac.type < e1000_pch_lpt) || in e1000_disable_ulp_lpt_lp()
1365 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || in e1000_disable_ulp_lpt_lp()
1366 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || in e1000_disable_ulp_lpt_lp()
1367 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || in e1000_disable_ulp_lpt_lp()
1368 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || in e1000_disable_ulp_lpt_lp()
1369 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) in e1000_disable_ulp_lpt_lp()
1373 struct e1000_adapter *adapter = hw->adapter; in e1000_disable_ulp_lpt_lp()
1377 /* Request ME un-configure ULP mode in the PHY */ in e1000_disable_ulp_lpt_lp()
1390 ret_val = -E1000_ERR_PHY; in e1000_disable_ulp_lpt_lp()
1419 ret_val = hw->phy.ops.acquire(hw); in e1000_disable_ulp_lpt_lp()
1425 e1000_toggle_lanphypc_pch_lpt(hw); in e1000_disable_ulp_lpt_lp()
1430 e1000e_disable_phy_retry(hw); in e1000_disable_ulp_lpt_lp()
1433 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_disable_ulp_lpt_lp()
1444 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, in e1000_disable_ulp_lpt_lp()
1450 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_disable_ulp_lpt_lp()
1452 e1000e_enable_phy_retry(hw); in e1000_disable_ulp_lpt_lp()
1460 * hardware. Re-Enable K1 in the PHY when exiting ULP. in e1000_disable_ulp_lpt_lp()
1462 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); in e1000_disable_ulp_lpt_lp()
1466 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); in e1000_disable_ulp_lpt_lp()
1469 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); in e1000_disable_ulp_lpt_lp()
1480 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_disable_ulp_lpt_lp()
1484 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); in e1000_disable_ulp_lpt_lp()
1492 hw->phy.ops.release(hw); in e1000_disable_ulp_lpt_lp()
1494 e1000_phy_hw_reset(hw); in e1000_disable_ulp_lpt_lp()
1499 e_dbg("Error in ULP disable flow: %d\n", ret_val); in e1000_disable_ulp_lpt_lp()
1501 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; in e1000_disable_ulp_lpt_lp()
1507 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1508 * @hw: pointer to the HW structure
1514 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) in e1000_check_for_copper_link_ich8lan() argument
1516 struct e1000_mac_info *mac = &hw->mac; in e1000_check_for_copper_link_ich8lan()
1522 /* We only want to go out to the PHY registers to see if Auto-Neg in e1000_check_for_copper_link_ich8lan()
1527 if (!mac->get_link_status) in e1000_check_for_copper_link_ich8lan()
1529 mac->get_link_status = false; in e1000_check_for_copper_link_ich8lan()
1535 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); in e1000_check_for_copper_link_ich8lan()
1539 if (hw->mac.type == e1000_pchlan) { in e1000_check_for_copper_link_ich8lan()
1540 ret_val = e1000_k1_gig_workaround_hv(hw, link); in e1000_check_for_copper_link_ich8lan()
1545 /* When connected at 10Mbps half-duplex, some parts are excessively in e1000_check_for_copper_link_ich8lan()
1549 if ((hw->mac.type >= e1000_pch2lan) && link) { in e1000_check_for_copper_link_ich8lan()
1552 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); in e1000_check_for_copper_link_ich8lan()
1560 } else if (hw->mac.type >= e1000_pch_spt && in e1000_check_for_copper_link_ich8lan()
1573 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1577 if (hw->mac.type == e1000_pch2lan) in e1000_check_for_copper_link_ich8lan()
1581 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); in e1000_check_for_copper_link_ich8lan()
1583 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1586 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); in e1000_check_for_copper_link_ich8lan()
1592 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); in e1000_check_for_copper_link_ich8lan()
1595 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1600 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, in e1000_check_for_copper_link_ich8lan()
1604 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1609 if (hw->mac.type >= e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1614 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1618 ret_val = e1e_rphy_locked(hw, in e1000_check_for_copper_link_ich8lan()
1622 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1631 e1e_wphy_locked(hw, in e1000_check_for_copper_link_ich8lan()
1635 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1639 ret_val = hw->phy.ops.acquire(hw); in e1000_check_for_copper_link_ich8lan()
1643 ret_val = e1e_wphy_locked(hw, in e1000_check_for_copper_link_ich8lan()
1646 hw->phy.ops.release(hw); in e1000_check_for_copper_link_ich8lan()
1659 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1668 /* Work-around I218 hang issue */ in e1000_check_for_copper_link_ich8lan()
1669 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || in e1000_check_for_copper_link_ich8lan()
1670 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || in e1000_check_for_copper_link_ich8lan()
1671 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || in e1000_check_for_copper_link_ich8lan()
1672 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { in e1000_check_for_copper_link_ich8lan()
1673 ret_val = e1000_k1_workaround_lpt_lp(hw, link); in e1000_check_for_copper_link_ich8lan()
1677 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1681 ret_val = e1000_platform_pm_pch_lpt(hw, link); in e1000_check_for_copper_link_ich8lan()
1687 hw->dev_spec.ich8lan.eee_lp_ability = 0; in e1000_check_for_copper_link_ich8lan()
1689 if (hw->mac.type >= e1000_pch_lpt) { in e1000_check_for_copper_link_ich8lan()
1692 if (hw->mac.type == e1000_pch_spt) { in e1000_check_for_copper_link_ich8lan()
1693 /* FEXTNVM6 K1-off workaround - for SPT only */ in e1000_check_for_copper_link_ich8lan()
1708 switch (hw->mac.type) { in e1000_check_for_copper_link_ich8lan()
1710 ret_val = e1000_k1_workaround_lv(hw); in e1000_check_for_copper_link_ich8lan()
1715 if (hw->phy.type == e1000_phy_82578) { in e1000_check_for_copper_link_ich8lan()
1716 ret_val = e1000_link_stall_workaround_hv(hw); in e1000_check_for_copper_link_ich8lan()
1721 /* Workaround for PCHx parts in half-duplex: in e1000_check_for_copper_link_ich8lan()
1726 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); in e1000_check_for_copper_link_ich8lan()
1732 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); in e1000_check_for_copper_link_ich8lan()
1739 * immediately after link-up in e1000_check_for_copper_link_ich8lan()
1741 e1000e_check_downshift(hw); in e1000_check_for_copper_link_ich8lan()
1744 if (hw->phy.type > e1000_phy_82579) { in e1000_check_for_copper_link_ich8lan()
1745 ret_val = e1000_set_eee_pchlan(hw); in e1000_check_for_copper_link_ich8lan()
1753 if (!mac->autoneg) in e1000_check_for_copper_link_ich8lan()
1754 return -E1000_ERR_CONFIG; in e1000_check_for_copper_link_ich8lan()
1756 /* Auto-Neg is enabled. Auto Speed Detection takes care in e1000_check_for_copper_link_ich8lan()
1760 mac->ops.config_collision_dist(hw); in e1000_check_for_copper_link_ich8lan()
1762 /* Configure Flow Control now that Auto-Neg has completed. in e1000_check_for_copper_link_ich8lan()
1763 * First, we need to restore the desired flow control in e1000_check_for_copper_link_ich8lan()
1764 * settings because we may have had to re-autoneg with a in e1000_check_for_copper_link_ich8lan()
1767 ret_val = e1000e_config_fc_after_link_up(hw); in e1000_check_for_copper_link_ich8lan()
1769 e_dbg("Error configuring flow control\n"); in e1000_check_for_copper_link_ich8lan()
1774 mac->get_link_status = true; in e1000_check_for_copper_link_ich8lan()
1780 struct e1000_hw *hw = &adapter->hw; in e1000_get_variants_ich8lan() local
1783 rc = e1000_init_mac_params_ich8lan(hw); in e1000_get_variants_ich8lan()
1787 rc = e1000_init_nvm_params_ich8lan(hw); in e1000_get_variants_ich8lan()
1791 switch (hw->mac.type) { in e1000_get_variants_ich8lan()
1795 rc = e1000_init_phy_params_ich8lan(hw); in e1000_get_variants_ich8lan()
1808 rc = e1000_init_phy_params_pchlan(hw); in e1000_get_variants_ich8lan()
1819 if ((adapter->hw.phy.type == e1000_phy_ife) || in e1000_get_variants_ich8lan()
1820 ((adapter->hw.mac.type >= e1000_pch2lan) && in e1000_get_variants_ich8lan()
1822 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; in e1000_get_variants_ich8lan()
1823 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; in e1000_get_variants_ich8lan()
1825 hw->mac.ops.blink_led = NULL; in e1000_get_variants_ich8lan()
1828 if ((adapter->hw.mac.type == e1000_ich8lan) && in e1000_get_variants_ich8lan()
1829 (adapter->hw.phy.type != e1000_phy_ife)) in e1000_get_variants_ich8lan()
1830 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; in e1000_get_variants_ich8lan()
1833 if ((adapter->hw.mac.type == e1000_pch2lan) && in e1000_get_variants_ich8lan()
1835 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; in e1000_get_variants_ich8lan()
1843 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1844 * @hw: pointer to the HW structure
1848 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) in e1000_acquire_nvm_ich8lan() argument
1856 * e1000_release_nvm_ich8lan - Release NVM mutex
1857 * @hw: pointer to the HW structure
1861 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) in e1000_release_nvm_ich8lan() argument
1867 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1868 * @hw: pointer to the HW structure
1873 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) in e1000_acquire_swflag_ich8lan() argument
1879 &hw->adapter->state)) { in e1000_acquire_swflag_ich8lan()
1881 return -E1000_ERR_PHY; in e1000_acquire_swflag_ich8lan()
1890 timeout--; in e1000_acquire_swflag_ich8lan()
1895 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1910 timeout--; in e1000_acquire_swflag_ich8lan()
1914 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", in e1000_acquire_swflag_ich8lan()
1918 ret_val = -E1000_ERR_CONFIG; in e1000_acquire_swflag_ich8lan()
1924 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_acquire_swflag_ich8lan()
1930 * e1000_release_swflag_ich8lan - Release software control flag
1931 * @hw: pointer to the HW structure
1936 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) in e1000_release_swflag_ich8lan() argument
1946 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); in e1000_release_swflag_ich8lan()
1949 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_release_swflag_ich8lan()
1953 * e1000_check_mng_mode_ich8lan - Checks management mode
1954 * @hw: pointer to the HW structure
1960 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) in e1000_check_mng_mode_ich8lan() argument
1971 * e1000_check_mng_mode_pchlan - Checks management mode
1972 * @hw: pointer to the HW structure
1978 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) in e1000_check_mng_mode_pchlan() argument
1988 * e1000_rar_set_pch2lan - Set receive address register
1989 * @hw: pointer to the HW structure
1995 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1996 * Use SHRA[0-3] in place of those reserved for ME.
1998 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) in e1000_rar_set_pch2lan() argument
2002 /* HW expects these in little endian so we reverse the byte order in e1000_rar_set_pch2lan()
2023 /* RAR[1-6] are owned by manageability. Skip those and program the in e1000_rar_set_pch2lan()
2026 if (index < (u32)(hw->mac.rar_entry_count)) { in e1000_rar_set_pch2lan()
2029 ret_val = e1000_acquire_swflag_ich8lan(hw); in e1000_rar_set_pch2lan()
2033 ew32(SHRAL(index - 1), rar_low); in e1000_rar_set_pch2lan()
2035 ew32(SHRAH(index - 1), rar_high); in e1000_rar_set_pch2lan()
2038 e1000_release_swflag_ich8lan(hw); in e1000_rar_set_pch2lan()
2041 if ((er32(SHRAL(index - 1)) == rar_low) && in e1000_rar_set_pch2lan()
2042 (er32(SHRAH(index - 1)) == rar_high)) in e1000_rar_set_pch2lan()
2045 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", in e1000_rar_set_pch2lan()
2046 (index - 1), er32(FWSM)); in e1000_rar_set_pch2lan()
2051 return -E1000_ERR_CONFIG; in e1000_rar_set_pch2lan()
2055 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
2056 * @hw: pointer to the HW structure
2059 * program. SHRA[0-10] are the shared receive address registers
2064 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) in e1000_rar_get_count_pch_lpt() argument
2075 num_entries = hw->mac.rar_entry_count; in e1000_rar_get_count_pch_lpt()
2082 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ in e1000_rar_get_count_pch_lpt()
2091 * e1000_rar_set_pch_lpt - Set receive address registers
2092 * @hw: pointer to the HW structure
2098 * contain the MAC address. SHRA[0-10] are the shared receive address
2101 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) in e1000_rar_set_pch_lpt() argument
2106 /* HW expects these in little endian so we reverse the byte order in e1000_rar_set_pch_lpt()
2127 * it is using - those registers are unavailable for use. in e1000_rar_set_pch_lpt()
2129 if (index < hw->mac.rar_entry_count) { in e1000_rar_set_pch_lpt()
2140 ret_val = e1000_acquire_swflag_ich8lan(hw); in e1000_rar_set_pch_lpt()
2145 ew32(SHRAL_PCH_LPT(index - 1), rar_low); in e1000_rar_set_pch_lpt()
2147 ew32(SHRAH_PCH_LPT(index - 1), rar_high); in e1000_rar_set_pch_lpt()
2150 e1000_release_swflag_ich8lan(hw); in e1000_rar_set_pch_lpt()
2153 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && in e1000_rar_set_pch_lpt()
2154 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) in e1000_rar_set_pch_lpt()
2161 return -E1000_ERR_CONFIG; in e1000_rar_set_pch_lpt()
2165 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2166 * @hw: pointer to the HW structure
2172 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) in e1000_check_reset_block_ich8lan() argument
2184 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2185 * @hw: pointer to the HW structure
2190 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) in e1000_write_smbus_addr() argument
2199 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); in e1000_write_smbus_addr()
2207 if (hw->phy.type == e1000_phy_i217) { in e1000_write_smbus_addr()
2209 if (freq--) { in e1000_write_smbus_addr()
2214 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); in e1000_write_smbus_addr()
2220 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); in e1000_write_smbus_addr()
2224 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2225 * @hw: pointer to the HW structure
2230 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) in e1000_sw_lcd_config_ich8lan() argument
2232 struct e1000_phy_info *phy = &hw->phy; in e1000_sw_lcd_config_ich8lan()
2243 switch (hw->mac.type) { in e1000_sw_lcd_config_ich8lan()
2245 if (phy->type != e1000_phy_igp_3) in e1000_sw_lcd_config_ich8lan()
2248 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || in e1000_sw_lcd_config_ich8lan()
2249 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { in e1000_sw_lcd_config_ich8lan()
2271 ret_val = hw->phy.ops.acquire(hw); in e1000_sw_lcd_config_ich8lan()
2279 /* Make sure HW does not configure LCD from PHY in e1000_sw_lcd_config_ich8lan()
2283 if ((hw->mac.type < e1000_pch2lan) && in e1000_sw_lcd_config_ich8lan()
2296 if (((hw->mac.type == e1000_pchlan) && in e1000_sw_lcd_config_ich8lan()
2298 (hw->mac.type > e1000_pchlan)) { in e1000_sw_lcd_config_ich8lan()
2299 /* HW configures the SMBus address and LEDs when the in e1000_sw_lcd_config_ich8lan()
2304 ret_val = e1000_write_smbus_addr(hw); in e1000_sw_lcd_config_ich8lan()
2309 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, in e1000_sw_lcd_config_ich8lan()
2321 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); in e1000_sw_lcd_config_ich8lan()
2325 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), in e1000_sw_lcd_config_ich8lan()
2339 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); in e1000_sw_lcd_config_ich8lan()
2345 hw->phy.ops.release(hw); in e1000_sw_lcd_config_ich8lan()
2350 * e1000_k1_gig_workaround_hv - K1 Si workaround
2351 * @hw: pointer to the HW structure
2359 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) in e1000_k1_gig_workaround_hv() argument
2363 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; in e1000_k1_gig_workaround_hv()
2365 if (hw->mac.type != e1000_pchlan) in e1000_k1_gig_workaround_hv()
2368 /* Wrap the whole flow with the sw flag */ in e1000_k1_gig_workaround_hv()
2369 ret_val = hw->phy.ops.acquire(hw); in e1000_k1_gig_workaround_hv()
2375 if (hw->phy.type == e1000_phy_82578) { in e1000_k1_gig_workaround_hv()
2376 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, in e1000_k1_gig_workaround_hv()
2391 if (hw->phy.type == e1000_phy_82577) { in e1000_k1_gig_workaround_hv()
2392 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); in e1000_k1_gig_workaround_hv()
2407 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); in e1000_k1_gig_workaround_hv()
2413 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); in e1000_k1_gig_workaround_hv()
2418 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); in e1000_k1_gig_workaround_hv()
2421 hw->phy.ops.release(hw); in e1000_k1_gig_workaround_hv()
2427 * e1000_configure_k1_ich8lan - Configure K1 power state
2428 * @hw: pointer to the HW structure
2434 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2436 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) in e1000_configure_k1_ich8lan() argument
2444 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, in e1000_configure_k1_ich8lan()
2454 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, in e1000_configure_k1_ich8lan()
2461 ctrl_reg = er32(CTRL); in e1000_configure_k1_ich8lan()
2465 ew32(CTRL, reg); in e1000_configure_k1_ich8lan()
2470 ew32(CTRL, ctrl_reg); in e1000_configure_k1_ich8lan()
2479 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2480 * @hw: pointer to the HW structure
2485 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2487 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) in e1000_oem_bits_config_ich8lan() argument
2493 if (hw->mac.type < e1000_pchlan) in e1000_oem_bits_config_ich8lan()
2496 ret_val = hw->phy.ops.acquire(hw); in e1000_oem_bits_config_ich8lan()
2500 if (hw->mac.type == e1000_pchlan) { in e1000_oem_bits_config_ich8lan()
2512 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); in e1000_oem_bits_config_ich8lan()
2534 /* Set Restart auto-neg to activate the bits */ in e1000_oem_bits_config_ich8lan()
2535 if ((d0_state || (hw->mac.type != e1000_pchlan)) && in e1000_oem_bits_config_ich8lan()
2536 !hw->phy.ops.check_reset_block(hw)) in e1000_oem_bits_config_ich8lan()
2539 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); in e1000_oem_bits_config_ich8lan()
2542 hw->phy.ops.release(hw); in e1000_oem_bits_config_ich8lan()
2548 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2549 * @hw: pointer to the HW structure
2551 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) in e1000_set_mdio_slow_mode_hv() argument
2556 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); in e1000_set_mdio_slow_mode_hv()
2562 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); in e1000_set_mdio_slow_mode_hv()
2568 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2569 * @hw: pointer to the HW structure
2573 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) in e1000_hv_phy_workarounds_ich8lan() argument
2578 if (hw->mac.type != e1000_pchlan) in e1000_hv_phy_workarounds_ich8lan()
2582 if (hw->phy.type == e1000_phy_82577) { in e1000_hv_phy_workarounds_ich8lan()
2583 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_hv_phy_workarounds_ich8lan()
2588 if (((hw->phy.type == e1000_phy_82577) && in e1000_hv_phy_workarounds_ich8lan()
2589 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || in e1000_hv_phy_workarounds_ich8lan()
2590 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { in e1000_hv_phy_workarounds_ich8lan()
2592 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2597 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); in e1000_hv_phy_workarounds_ich8lan()
2602 if (hw->phy.type == e1000_phy_82578) { in e1000_hv_phy_workarounds_ich8lan()
2606 if (hw->phy.revision < 2) { in e1000_hv_phy_workarounds_ich8lan()
2607 e1000e_phy_sw_reset(hw); in e1000_hv_phy_workarounds_ich8lan()
2608 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); in e1000_hv_phy_workarounds_ich8lan()
2615 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2619 hw->phy.addr = 1; in e1000_hv_phy_workarounds_ich8lan()
2620 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); in e1000_hv_phy_workarounds_ich8lan()
2621 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2628 ret_val = e1000_k1_gig_workaround_hv(hw, true); in e1000_hv_phy_workarounds_ich8lan()
2633 ret_val = hw->phy.ops.acquire(hw); in e1000_hv_phy_workarounds_ich8lan()
2636 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); in e1000_hv_phy_workarounds_ich8lan()
2639 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); in e1000_hv_phy_workarounds_ich8lan()
2644 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); in e1000_hv_phy_workarounds_ich8lan()
2646 hw->phy.ops.release(hw); in e1000_hv_phy_workarounds_ich8lan()
2652 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2653 * @hw: pointer to the HW structure
2655 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) in e1000_copy_rx_addrs_to_phy_ich8lan() argument
2661 ret_val = hw->phy.ops.acquire(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2664 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_copy_rx_addrs_to_phy_ich8lan()
2669 for (i = 0; i < (hw->mac.rar_entry_count); i++) { in e1000_copy_rx_addrs_to_phy_ich8lan()
2671 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2673 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2677 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2679 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), in e1000_copy_rx_addrs_to_phy_ich8lan()
2683 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); in e1000_copy_rx_addrs_to_phy_ich8lan()
2686 hw->phy.ops.release(hw); in e1000_copy_rx_addrs_to_phy_ich8lan()
2690 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2692 * @hw: pointer to the HW structure
2695 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) in e1000_lv_jumbo_workaround_ich8lan() argument
2702 if (hw->mac.type < e1000_pch2lan) in e1000_lv_jumbo_workaround_ich8lan()
2706 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2707 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); in e1000_lv_jumbo_workaround_ich8lan()
2715 for (i = 0; i < hw->mac.rar_entry_count; i++) { in e1000_lv_jumbo_workaround_ich8lan()
2734 e1000_copy_rx_addrs_to_phy_ich8lan(hw); in e1000_lv_jumbo_workaround_ich8lan()
2746 ret_val = e1000e_read_kmrn_reg(hw, in e1000_lv_jumbo_workaround_ich8lan()
2751 ret_val = e1000e_write_kmrn_reg(hw, in e1000_lv_jumbo_workaround_ich8lan()
2756 ret_val = e1000e_read_kmrn_reg(hw, in e1000_lv_jumbo_workaround_ich8lan()
2763 ret_val = e1000e_write_kmrn_reg(hw, in e1000_lv_jumbo_workaround_ich8lan()
2770 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2773 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2776 e1e_rphy(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2778 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); in e1000_lv_jumbo_workaround_ich8lan()
2781 e1e_rphy(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2784 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); in e1000_lv_jumbo_workaround_ich8lan()
2787 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); in e1000_lv_jumbo_workaround_ich8lan()
2790 e1e_rphy(hw, HV_PM_CTRL, &data); in e1000_lv_jumbo_workaround_ich8lan()
2791 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); in e1000_lv_jumbo_workaround_ich8lan()
2804 ret_val = e1000e_read_kmrn_reg(hw, in e1000_lv_jumbo_workaround_ich8lan()
2809 ret_val = e1000e_write_kmrn_reg(hw, in e1000_lv_jumbo_workaround_ich8lan()
2814 ret_val = e1000e_read_kmrn_reg(hw, in e1000_lv_jumbo_workaround_ich8lan()
2821 ret_val = e1000e_write_kmrn_reg(hw, in e1000_lv_jumbo_workaround_ich8lan()
2828 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2830 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
2833 e1e_rphy(hw, PHY_REG(769, 16), &data); in e1000_lv_jumbo_workaround_ich8lan()
2835 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); in e1000_lv_jumbo_workaround_ich8lan()
2838 e1e_rphy(hw, PHY_REG(776, 20), &data); in e1000_lv_jumbo_workaround_ich8lan()
2841 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); in e1000_lv_jumbo_workaround_ich8lan()
2844 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); in e1000_lv_jumbo_workaround_ich8lan()
2847 e1e_rphy(hw, HV_PM_CTRL, &data); in e1000_lv_jumbo_workaround_ich8lan()
2848 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); in e1000_lv_jumbo_workaround_ich8lan()
2853 /* re-enable Rx path after enabling/disabling workaround */ in e1000_lv_jumbo_workaround_ich8lan()
2854 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); in e1000_lv_jumbo_workaround_ich8lan()
2858 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2859 * @hw: pointer to the HW structure
2863 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) in e1000_lv_phy_workarounds_ich8lan() argument
2867 if (hw->mac.type != e1000_pch2lan) in e1000_lv_phy_workarounds_ich8lan()
2871 ret_val = e1000_set_mdio_slow_mode_hv(hw); in e1000_lv_phy_workarounds_ich8lan()
2875 ret_val = hw->phy.ops.acquire(hw); in e1000_lv_phy_workarounds_ich8lan()
2879 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); in e1000_lv_phy_workarounds_ich8lan()
2883 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); in e1000_lv_phy_workarounds_ich8lan()
2885 hw->phy.ops.release(hw); in e1000_lv_phy_workarounds_ich8lan()
2891 * e1000_k1_workaround_lv - K1 Si workaround
2892 * @hw: pointer to the HW structure
2897 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) in e1000_k1_workaround_lv() argument
2902 if (hw->mac.type != e1000_pch2lan) in e1000_k1_workaround_lv()
2906 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); in e1000_k1_workaround_lv()
2917 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); in e1000_k1_workaround_lv()
2921 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); in e1000_k1_workaround_lv()
2938 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2939 * @hw: pointer to the HW structure
2945 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) in e1000_gate_hw_phy_config_ich8lan() argument
2949 if (hw->mac.type < e1000_pch2lan) in e1000_gate_hw_phy_config_ich8lan()
2963 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2964 * @hw: pointer to the HW structure
2969 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) in e1000_lan_init_done_ich8lan() argument
2978 } while ((!data) && --loop); in e1000_lan_init_done_ich8lan()
2994 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2995 * @hw: pointer to the HW structure
2997 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) in e1000_post_phy_reset_ich8lan() argument
3002 if (hw->phy.ops.check_reset_block(hw)) in e1000_post_phy_reset_ich8lan()
3008 /* Perform any necessary post-reset workarounds */ in e1000_post_phy_reset_ich8lan()
3009 switch (hw->mac.type) { in e1000_post_phy_reset_ich8lan()
3011 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); in e1000_post_phy_reset_ich8lan()
3016 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); in e1000_post_phy_reset_ich8lan()
3025 if (hw->mac.type >= e1000_pchlan) { in e1000_post_phy_reset_ich8lan()
3026 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); in e1000_post_phy_reset_ich8lan()
3028 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); in e1000_post_phy_reset_ich8lan()
3032 ret_val = e1000_sw_lcd_config_ich8lan(hw); in e1000_post_phy_reset_ich8lan()
3037 ret_val = e1000_oem_bits_config_ich8lan(hw, true); in e1000_post_phy_reset_ich8lan()
3039 if (hw->mac.type == e1000_pch2lan) { in e1000_post_phy_reset_ich8lan()
3040 /* Ungate automatic PHY configuration on non-managed 82579 */ in e1000_post_phy_reset_ich8lan()
3043 e1000_gate_hw_phy_config_ich8lan(hw, false); in e1000_post_phy_reset_ich8lan()
3047 ret_val = hw->phy.ops.acquire(hw); in e1000_post_phy_reset_ich8lan()
3050 ret_val = e1000_write_emi_reg_locked(hw, in e1000_post_phy_reset_ich8lan()
3053 hw->phy.ops.release(hw); in e1000_post_phy_reset_ich8lan()
3060 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
3061 * @hw: pointer to the HW structure
3067 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) in e1000_phy_hw_reset_ich8lan() argument
3071 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ in e1000_phy_hw_reset_ich8lan()
3072 if ((hw->mac.type == e1000_pch2lan) && in e1000_phy_hw_reset_ich8lan()
3074 e1000_gate_hw_phy_config_ich8lan(hw, true); in e1000_phy_hw_reset_ich8lan()
3076 ret_val = e1000e_phy_hw_reset_generic(hw); in e1000_phy_hw_reset_ich8lan()
3080 return e1000_post_phy_reset_ich8lan(hw); in e1000_phy_hw_reset_ich8lan()
3084 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
3085 * @hw: pointer to the HW structure
3091 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
3094 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) in e1000_set_lplu_state_pchlan() argument
3099 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); in e1000_set_lplu_state_pchlan()
3108 if (!hw->phy.ops.check_reset_block(hw)) in e1000_set_lplu_state_pchlan()
3111 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); in e1000_set_lplu_state_pchlan()
3115 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
3116 * @hw: pointer to the HW structure
3127 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) in e1000_set_d0_lplu_state_ich8lan() argument
3129 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d0_lplu_state_ich8lan()
3134 if (phy->type == e1000_phy_ife) in e1000_set_d0_lplu_state_ich8lan()
3143 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
3149 if (hw->mac.type == e1000_ich8lan) in e1000_set_d0_lplu_state_ich8lan()
3150 e1000e_gig_downshift_workaround_ich8lan(hw); in e1000_set_d0_lplu_state_ich8lan()
3153 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); in e1000_set_d0_lplu_state_ich8lan()
3157 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); in e1000_set_d0_lplu_state_ich8lan()
3164 if (phy->type != e1000_phy_igp_3) in e1000_set_d0_lplu_state_ich8lan()
3172 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d0_lplu_state_ich8lan()
3173 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_ich8lan()
3179 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_ich8lan()
3183 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d0_lplu_state_ich8lan()
3184 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_ich8lan()
3190 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d0_lplu_state_ich8lan()
3201 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3202 * @hw: pointer to the HW structure
3213 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) in e1000_set_d3_lplu_state_ich8lan() argument
3215 struct e1000_phy_info *phy = &hw->phy; in e1000_set_d3_lplu_state_ich8lan()
3226 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3234 if (phy->smart_speed == e1000_smart_speed_on) { in e1000_set_d3_lplu_state_ich8lan()
3235 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d3_lplu_state_ich8lan()
3241 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d3_lplu_state_ich8lan()
3245 } else if (phy->smart_speed == e1000_smart_speed_off) { in e1000_set_d3_lplu_state_ich8lan()
3246 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d3_lplu_state_ich8lan()
3252 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, in e1000_set_d3_lplu_state_ich8lan()
3257 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || in e1000_set_d3_lplu_state_ich8lan()
3258 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || in e1000_set_d3_lplu_state_ich8lan()
3259 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { in e1000_set_d3_lplu_state_ich8lan()
3263 if (phy->type != e1000_phy_igp_3) in e1000_set_d3_lplu_state_ich8lan()
3269 if (hw->mac.type == e1000_ich8lan) in e1000_set_d3_lplu_state_ich8lan()
3270 e1000e_gig_downshift_workaround_ich8lan(hw); in e1000_set_d3_lplu_state_ich8lan()
3273 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); in e1000_set_d3_lplu_state_ich8lan()
3278 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); in e1000_set_d3_lplu_state_ich8lan()
3285 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3286 * @hw: pointer to the HW structure
3292 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) in e1000_valid_nvm_bank_detect_ich8lan() argument
3295 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_valid_nvm_bank_detect_ich8lan()
3296 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); in e1000_valid_nvm_bank_detect_ich8lan()
3302 switch (hw->mac.type) { in e1000_valid_nvm_bank_detect_ich8lan()
3311 bank1_offset = nvm->flash_bank_size; in e1000_valid_nvm_bank_detect_ich8lan()
3318 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, in e1000_valid_nvm_bank_detect_ich8lan()
3330 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + in e1000_valid_nvm_bank_detect_ich8lan()
3343 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3356 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); in e1000_valid_nvm_bank_detect_ich8lan()
3363 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, in e1000_valid_nvm_bank_detect_ich8lan()
3374 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + in e1000_valid_nvm_bank_detect_ich8lan()
3386 return -E1000_ERR_NVM; in e1000_valid_nvm_bank_detect_ich8lan()
3391 * e1000_read_nvm_spt - NVM access for SPT
3392 * @hw: pointer to the HW structure
3399 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, in e1000_read_nvm_spt() argument
3402 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_spt()
3403 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_spt()
3411 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_spt()
3414 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_spt()
3418 nvm->ops.acquire(hw); in e1000_read_nvm_spt()
3420 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_read_nvm_spt()
3426 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_spt()
3432 if (words - i == 1) { in e1000_read_nvm_spt()
3433 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_spt()
3435 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3437 offset_to_read = act_offset + i - in e1000_read_nvm_spt()
3440 e1000_read_flash_dword_ich8lan(hw, in e1000_read_nvm_spt()
3452 if (!(dev_spec->shadow_ram[offset + i].modified) || in e1000_read_nvm_spt()
3453 !(dev_spec->shadow_ram[offset + i + 1].modified)) { in e1000_read_nvm_spt()
3455 e1000_read_flash_dword_ich8lan(hw, in e1000_read_nvm_spt()
3461 if (dev_spec->shadow_ram[offset + i].modified) in e1000_read_nvm_spt()
3463 dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_spt()
3466 if (dev_spec->shadow_ram[offset + i].modified) in e1000_read_nvm_spt()
3468 dev_spec->shadow_ram[offset + i + 1].value; in e1000_read_nvm_spt()
3474 nvm->ops.release(hw); in e1000_read_nvm_spt()
3484 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3485 * @hw: pointer to the HW structure
3492 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, in e1000_read_nvm_ich8lan() argument
3495 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_read_nvm_ich8lan()
3496 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_read_nvm_ich8lan()
3502 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_read_nvm_ich8lan()
3505 ret_val = -E1000_ERR_NVM; in e1000_read_nvm_ich8lan()
3509 nvm->ops.acquire(hw); in e1000_read_nvm_ich8lan()
3511 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_read_nvm_ich8lan()
3517 act_offset = (bank) ? nvm->flash_bank_size : 0; in e1000_read_nvm_ich8lan()
3522 if (dev_spec->shadow_ram[offset + i].modified) { in e1000_read_nvm_ich8lan()
3523 data[i] = dev_spec->shadow_ram[offset + i].value; in e1000_read_nvm_ich8lan()
3525 ret_val = e1000_read_flash_word_ich8lan(hw, in e1000_read_nvm_ich8lan()
3534 nvm->ops.release(hw); in e1000_read_nvm_ich8lan()
3544 * e1000_flash_cycle_init_ich8lan - Initialize flash
3545 * @hw: pointer to the HW structure
3550 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) in e1000_flash_cycle_init_ich8lan() argument
3553 s32 ret_val = -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3560 return -E1000_ERR_NVM; in e1000_flash_cycle_init_ich8lan()
3563 /* Clear FCERR and DAEL in hw status by writing 1 */ in e1000_flash_cycle_init_ich8lan()
3566 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3585 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3609 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_init_ich8lan()
3623 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3624 * @hw: pointer to the HW structure
3629 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) in e1000_flash_cycle_ich8lan() argument
3635 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ in e1000_flash_cycle_ich8lan()
3636 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3642 if (hw->mac.type >= e1000_pch_spt) in e1000_flash_cycle_ich8lan()
3658 return -E1000_ERR_NVM; in e1000_flash_cycle_ich8lan()
3662 * e1000_read_flash_dword_ich8lan - Read dword from flash
3663 * @hw: pointer to the HW structure
3670 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_dword_ich8lan() argument
3675 return e1000_read_flash_data32_ich8lan(hw, offset, data); in e1000_read_flash_dword_ich8lan()
3679 * e1000_read_flash_word_ich8lan - Read word from flash
3680 * @hw: pointer to the HW structure
3687 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_word_ich8lan() argument
3693 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); in e1000_read_flash_word_ich8lan()
3697 * e1000_read_flash_byte_ich8lan - Read byte from flash
3698 * @hw: pointer to the HW structure
3704 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_byte_ich8lan() argument
3713 if (hw->mac.type >= e1000_pch_spt) in e1000_read_flash_byte_ich8lan()
3714 return -E1000_ERR_NVM; in e1000_read_flash_byte_ich8lan()
3716 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); in e1000_read_flash_byte_ich8lan()
3727 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3728 * @hw: pointer to the HW structure
3735 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_data_ich8lan() argument
3742 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3746 return -E1000_ERR_NVM; in e1000_read_flash_data_ich8lan()
3749 hw->nvm.flash_base_addr); in e1000_read_flash_data_ich8lan()
3754 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_read_flash_data_ich8lan()
3760 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_read_flash_data_ich8lan()
3767 e1000_flash_cycle_ich8lan(hw, in e1000_read_flash_data_ich8lan()
3793 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data_ich8lan()
3803 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3804 * @hw: pointer to the HW structure
3811 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_read_flash_data32_ich8lan() argument
3817 s32 ret_val = -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3820 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) in e1000_read_flash_data32_ich8lan()
3821 return -E1000_ERR_NVM; in e1000_read_flash_data32_ich8lan()
3823 hw->nvm.flash_base_addr); in e1000_read_flash_data32_ich8lan()
3828 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_read_flash_data32_ich8lan()
3837 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_read_flash_data32_ich8lan()
3846 e1000_flash_cycle_ich8lan(hw, in e1000_read_flash_data32_ich8lan()
3868 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_read_flash_data32_ich8lan()
3878 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3879 * @hw: pointer to the HW structure
3886 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, in e1000_write_nvm_ich8lan() argument
3889 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_write_nvm_ich8lan()
3890 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_write_nvm_ich8lan()
3893 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || in e1000_write_nvm_ich8lan()
3896 return -E1000_ERR_NVM; in e1000_write_nvm_ich8lan()
3899 nvm->ops.acquire(hw); in e1000_write_nvm_ich8lan()
3902 dev_spec->shadow_ram[offset + i].modified = true; in e1000_write_nvm_ich8lan()
3903 dev_spec->shadow_ram[offset + i].value = data[i]; in e1000_write_nvm_ich8lan()
3906 nvm->ops.release(hw); in e1000_write_nvm_ich8lan()
3912 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3913 * @hw: pointer to the HW structure
3922 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) in e1000_update_nvm_checksum_spt() argument
3924 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_spt()
3925 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_spt()
3930 ret_val = e1000e_update_nvm_checksum_generic(hw); in e1000_update_nvm_checksum_spt()
3934 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_spt()
3937 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_spt()
3943 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_update_nvm_checksum_spt()
3950 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
3952 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); in e1000_update_nvm_checksum_spt()
3956 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_spt()
3958 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); in e1000_update_nvm_checksum_spt()
3967 ret_val = e1000_read_flash_dword_ich8lan(hw, in e1000_update_nvm_checksum_spt()
3971 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_spt()
3973 dword |= (dev_spec->shadow_ram[i].value & 0xffff); in e1000_update_nvm_checksum_spt()
3975 if (dev_spec->shadow_ram[i + 1].modified) { in e1000_update_nvm_checksum_spt()
3977 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) in e1000_update_nvm_checksum_spt()
3990 if (i == E1000_ICH_NVM_SIG_WORD - 1) in e1000_update_nvm_checksum_spt()
4000 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, in e1000_update_nvm_checksum_spt()
4010 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ in e1000_update_nvm_checksum_spt()
4023 --act_offset; in e1000_update_nvm_checksum_spt()
4024 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); in e1000_update_nvm_checksum_spt()
4030 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); in e1000_update_nvm_checksum_spt()
4036 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; in e1000_update_nvm_checksum_spt()
4037 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); in e1000_update_nvm_checksum_spt()
4043 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); in e1000_update_nvm_checksum_spt()
4050 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_spt()
4051 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_spt()
4055 nvm->ops.release(hw); in e1000_update_nvm_checksum_spt()
4061 nvm->ops.reload(hw); in e1000_update_nvm_checksum_spt()
4073 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
4074 * @hw: pointer to the HW structure
4083 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) in e1000_update_nvm_checksum_ich8lan() argument
4085 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_update_nvm_checksum_ich8lan()
4086 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_update_nvm_checksum_ich8lan()
4091 ret_val = e1000e_update_nvm_checksum_generic(hw); in e1000_update_nvm_checksum_ich8lan()
4095 if (nvm->type != e1000_nvm_flash_sw) in e1000_update_nvm_checksum_ich8lan()
4098 nvm->ops.acquire(hw); in e1000_update_nvm_checksum_ich8lan()
4104 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); in e1000_update_nvm_checksum_ich8lan()
4111 new_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
4113 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); in e1000_update_nvm_checksum_ich8lan()
4117 old_bank_offset = nvm->flash_bank_size; in e1000_update_nvm_checksum_ich8lan()
4119 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); in e1000_update_nvm_checksum_ich8lan()
4124 if (dev_spec->shadow_ram[i].modified) { in e1000_update_nvm_checksum_ich8lan()
4125 data = dev_spec->shadow_ram[i].value; in e1000_update_nvm_checksum_ich8lan()
4127 ret_val = e1000_read_flash_word_ich8lan(hw, i + in e1000_update_nvm_checksum_ich8lan()
4149 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, in e1000_update_nvm_checksum_ich8lan()
4156 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, in e1000_update_nvm_checksum_ich8lan()
4167 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ in e1000_update_nvm_checksum_ich8lan()
4178 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); in e1000_update_nvm_checksum_ich8lan()
4183 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, in e1000_update_nvm_checksum_ich8lan()
4195 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); in e1000_update_nvm_checksum_ich8lan()
4201 dev_spec->shadow_ram[i].modified = false; in e1000_update_nvm_checksum_ich8lan()
4202 dev_spec->shadow_ram[i].value = 0xFFFF; in e1000_update_nvm_checksum_ich8lan()
4206 nvm->ops.release(hw); in e1000_update_nvm_checksum_ich8lan()
4212 nvm->ops.reload(hw); in e1000_update_nvm_checksum_ich8lan()
4224 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4225 * @hw: pointer to the HW structure
4231 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) in e1000_validate_nvm_checksum_ich8lan() argument
4243 switch (hw->mac.type) { in e1000_validate_nvm_checksum_ich8lan()
4262 ret_val = e1000_read_nvm(hw, word, 1, &data); in e1000_validate_nvm_checksum_ich8lan()
4269 if (hw->mac.type < e1000_pch_tgp) { in e1000_validate_nvm_checksum_ich8lan()
4271 ret_val = e1000_write_nvm(hw, word, 1, &data); in e1000_validate_nvm_checksum_ich8lan()
4274 ret_val = e1000e_update_nvm_checksum(hw); in e1000_validate_nvm_checksum_ich8lan()
4280 return e1000e_validate_nvm_checksum_generic(hw); in e1000_validate_nvm_checksum_ich8lan()
4284 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4285 * @hw: pointer to the HW structure
4287 * To prevent malicious write/erase of the NVM, set it to be read-only
4289 * the flash control registers. The shadow-ram copy of the NVM will
4293 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) in e1000e_write_protect_nvm_ich8lan() argument
4295 struct e1000_nvm_info *nvm = &hw->nvm; in e1000e_write_protect_nvm_ich8lan()
4300 nvm->ops.acquire(hw); in e1000e_write_protect_nvm_ich8lan()
4304 /* Write-protect GbE Sector of NVM */ in e1000e_write_protect_nvm_ich8lan()
4312 * PR0 to prevent the write-protection from being lifted. in e1000e_write_protect_nvm_ich8lan()
4320 nvm->ops.release(hw); in e1000e_write_protect_nvm_ich8lan()
4324 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4325 * @hw: pointer to the HW structure
4332 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_write_flash_data_ich8lan() argument
4342 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data_ich8lan()
4344 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4347 return -E1000_ERR_NVM; in e1000_write_flash_data_ich8lan()
4351 hw->nvm.flash_base_addr); in e1000_write_flash_data_ich8lan()
4356 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_write_flash_data_ich8lan()
4362 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4368 hsflctl.hsf_ctrl.fldbcount = size - 1; in e1000_write_flash_data_ich8lan()
4374 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data_ich8lan()
4392 e1000_flash_cycle_ich8lan(hw, in e1000_write_flash_data_ich8lan()
4407 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data_ich8lan()
4416 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4417 * @hw: pointer to the HW structure
4423 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_write_flash_data32_ich8lan() argument
4432 if (hw->mac.type >= e1000_pch_spt) { in e1000_write_flash_data32_ich8lan()
4434 return -E1000_ERR_NVM; in e1000_write_flash_data32_ich8lan()
4437 hw->nvm.flash_base_addr); in e1000_write_flash_data32_ich8lan()
4441 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_write_flash_data32_ich8lan()
4448 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4454 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; in e1000_write_flash_data32_ich8lan()
4461 if (hw->mac.type >= e1000_pch_spt) in e1000_write_flash_data32_ich8lan()
4474 e1000_flash_cycle_ich8lan(hw, in e1000_write_flash_data32_ich8lan()
4491 e_dbg("Timeout error - flash cycle did not complete.\n"); in e1000_write_flash_data32_ich8lan()
4500 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4501 * @hw: pointer to the HW structure
4507 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, in e1000_write_flash_byte_ich8lan() argument
4512 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); in e1000_write_flash_byte_ich8lan()
4516 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4517 * @hw: pointer to the HW structure
4524 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, in e1000_retry_write_flash_dword_ich8lan() argument
4532 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); in e1000_retry_write_flash_dword_ich8lan()
4539 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); in e1000_retry_write_flash_dword_ich8lan()
4544 return -E1000_ERR_NVM; in e1000_retry_write_flash_dword_ich8lan()
4550 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4551 * @hw: pointer to the HW structure
4558 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, in e1000_retry_write_flash_byte_ich8lan() argument
4564 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); in e1000_retry_write_flash_byte_ich8lan()
4571 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); in e1000_retry_write_flash_byte_ich8lan()
4576 return -E1000_ERR_NVM; in e1000_retry_write_flash_byte_ich8lan()
4582 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4583 * @hw: pointer to the HW structure
4589 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) in e1000_erase_flash_bank_ich8lan() argument
4591 struct e1000_nvm_info *nvm = &hw->nvm; in e1000_erase_flash_bank_ich8lan()
4595 /* bank size is in 16bit words - adjust to bytes */ in e1000_erase_flash_bank_ich8lan()
4596 u32 flash_bank_size = nvm->flash_bank_size * 2; in e1000_erase_flash_bank_ich8lan()
4603 /* Determine HW Sector size: Read BERASE bits of hw flash status in e1000_erase_flash_bank_ich8lan()
4605 * 00: The Hw sector is 256 bytes, hence we need to erase 16 in e1000_erase_flash_bank_ich8lan()
4606 * consecutive sectors. The start index for the nth Hw sector in e1000_erase_flash_bank_ich8lan()
4608 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. in e1000_erase_flash_bank_ich8lan()
4609 * The start index for the nth Hw sector can be calculated in e1000_erase_flash_bank_ich8lan()
4611 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 in e1000_erase_flash_bank_ich8lan()
4613 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 in e1000_erase_flash_bank_ich8lan()
4617 /* Hw sector size 256 */ in e1000_erase_flash_bank_ich8lan()
4634 return -E1000_ERR_NVM; in e1000_erase_flash_bank_ich8lan()
4638 flash_linear_addr = hw->nvm.flash_base_addr; in e1000_erase_flash_bank_ich8lan()
4646 ret_val = e1000_flash_cycle_init_ich8lan(hw); in e1000_erase_flash_bank_ich8lan()
4651 * Cycle field in hw flash control in e1000_erase_flash_bank_ich8lan()
4653 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4660 if (hw->mac.type >= e1000_pch_spt) in e1000_erase_flash_bank_ich8lan()
4673 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); in e1000_erase_flash_bank_ich8lan()
4694 * e1000_valid_led_default_ich8lan - Set the default LED settings
4695 * @hw: pointer to the HW structure
4702 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) in e1000_valid_led_default_ich8lan() argument
4706 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); in e1000_valid_led_default_ich8lan()
4719 * e1000_id_led_init_pchlan - store LED configurations
4720 * @hw: pointer to the HW structure
4731 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) in e1000_id_led_init_pchlan() argument
4733 struct e1000_mac_info *mac = &hw->mac; in e1000_id_led_init_pchlan()
4740 ret_val = hw->nvm.ops.valid_led_default(hw, &data); in e1000_id_led_init_pchlan()
4744 mac->ledctl_default = er32(LEDCTL); in e1000_id_led_init_pchlan()
4745 mac->ledctl_mode1 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4746 mac->ledctl_mode2 = mac->ledctl_default; in e1000_id_led_init_pchlan()
4755 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4756 mac->ledctl_mode1 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4761 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4762 mac->ledctl_mode1 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4772 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4773 mac->ledctl_mode2 |= (ledctl_on << shift); in e1000_id_led_init_pchlan()
4778 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); in e1000_id_led_init_pchlan()
4779 mac->ledctl_mode2 |= (ledctl_off << shift); in e1000_id_led_init_pchlan()
4791 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4792 * @hw: pointer to the HW structure
4797 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) in e1000_get_bus_info_ich8lan() argument
4799 struct e1000_bus_info *bus = &hw->bus; in e1000_get_bus_info_ich8lan()
4802 ret_val = e1000e_get_bus_info_pcie(hw); in e1000_get_bus_info_ich8lan()
4804 /* ICH devices are "PCI Express"-ish. They have in e1000_get_bus_info_ich8lan()
4809 if (bus->width == e1000_bus_width_unknown) in e1000_get_bus_info_ich8lan()
4810 bus->width = e1000_bus_width_pcie_x1; in e1000_get_bus_info_ich8lan()
4816 * e1000_reset_hw_ich8lan - Reset the hardware
4817 * @hw: pointer to the HW structure
4822 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) in e1000_reset_hw_ich8lan() argument
4824 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_reset_hw_ich8lan()
4826 u32 ctrl, reg; in e1000_reset_hw_ich8lan() local
4829 /* Prevent the PCI-E bus from sticking if there is no TLP connection in e1000_reset_hw_ich8lan()
4832 ret_val = e1000e_disable_pcie_master(hw); in e1000_reset_hw_ich8lan()
4834 e_dbg("PCI-E Master disable polling has failed.\n"); in e1000_reset_hw_ich8lan()
4850 if (hw->mac.type == e1000_ich8lan) { in e1000_reset_hw_ich8lan()
4857 if (hw->mac.type == e1000_pchlan) { in e1000_reset_hw_ich8lan()
4859 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); in e1000_reset_hw_ich8lan()
4864 dev_spec->nvm_k1_enabled = true; in e1000_reset_hw_ich8lan()
4866 dev_spec->nvm_k1_enabled = false; in e1000_reset_hw_ich8lan()
4869 ctrl = er32(CTRL); in e1000_reset_hw_ich8lan()
4871 if (!hw->phy.ops.check_reset_block(hw)) { in e1000_reset_hw_ich8lan()
4872 /* Full-chip reset requires MAC and PHY reset at the same in e1000_reset_hw_ich8lan()
4876 ctrl |= E1000_CTRL_PHY_RST; in e1000_reset_hw_ich8lan()
4879 * non-managed 82579 in e1000_reset_hw_ich8lan()
4881 if ((hw->mac.type == e1000_pch2lan) && in e1000_reset_hw_ich8lan()
4883 e1000_gate_hw_phy_config_ich8lan(hw, true); in e1000_reset_hw_ich8lan()
4885 ret_val = e1000_acquire_swflag_ich8lan(hw); in e1000_reset_hw_ich8lan()
4887 ew32(CTRL, (ctrl | E1000_CTRL_RST)); in e1000_reset_hw_ich8lan()
4892 if (hw->mac.type == e1000_pch2lan) { in e1000_reset_hw_ich8lan()
4900 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); in e1000_reset_hw_ich8lan()
4902 if (ctrl & E1000_CTRL_PHY_RST) { in e1000_reset_hw_ich8lan()
4903 ret_val = hw->phy.ops.get_cfg_done(hw); in e1000_reset_hw_ich8lan()
4907 ret_val = e1000_post_phy_reset_ich8lan(hw); in e1000_reset_hw_ich8lan()
4916 if (hw->mac.type == e1000_pchlan) in e1000_reset_hw_ich8lan()
4930 * e1000_init_hw_ich8lan - Initialize the hardware
4931 * @hw: pointer to the HW structure
4934 * - initialize hardware bits
4935 * - initialize LED identification
4936 * - setup receive address registers
4937 * - setup flow control
4938 * - setup transmit descriptors
4939 * - clear statistics
4941 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) in e1000_init_hw_ich8lan() argument
4943 struct e1000_mac_info *mac = &hw->mac; in e1000_init_hw_ich8lan()
4948 e1000_initialize_hw_bits_ich8lan(hw); in e1000_init_hw_ich8lan()
4949 if (hw->mac.type >= e1000_pch_mtp) { in e1000_init_hw_ich8lan()
4950 ret_val = hw->phy.ops.acquire(hw); in e1000_init_hw_ich8lan()
4954 ret_val = e1000_reconfigure_k1_exit_timeout(hw); in e1000_init_hw_ich8lan()
4955 hw->phy.ops.release(hw); in e1000_init_hw_ich8lan()
4963 ret_val = mac->ops.id_led_init(hw); in e1000_init_hw_ich8lan()
4969 e1000e_init_rx_addrs(hw, mac->rar_entry_count); in e1000_init_hw_ich8lan()
4973 for (i = 0; i < mac->mta_reg_count; i++) in e1000_init_hw_ich8lan()
4974 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); in e1000_init_hw_ich8lan()
4980 if (hw->phy.type == e1000_phy_82578) { in e1000_init_hw_ich8lan()
4981 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); in e1000_init_hw_ich8lan()
4983 e1e_wphy(hw, BM_PORT_GEN_CFG, i); in e1000_init_hw_ich8lan()
4984 ret_val = e1000_phy_hw_reset_ich8lan(hw); in e1000_init_hw_ich8lan()
4989 /* Setup link and flow control */ in e1000_init_hw_ich8lan()
4990 ret_val = mac->ops.setup_link(hw); in e1000_init_hw_ich8lan()
4992 /* Set the transmit descriptor write-back policy for both queues */ in e1000_init_hw_ich8lan()
5009 if (mac->type == e1000_ich8lan) in e1000_init_hw_ich8lan()
5013 e1000e_set_pcie_no_snoop(hw, snoop); in e1000_init_hw_ich8lan()
5018 if (mac->type >= e1000_pch_tgp) { in e1000_init_hw_ich8lan()
5033 e1000_clear_hw_cntrs_ich8lan(hw); in e1000_init_hw_ich8lan()
5039 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
5040 * @hw: pointer to the HW structure
5045 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) in e1000_initialize_hw_bits_ich8lan() argument
5052 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ in e1000_initialize_hw_bits_ich8lan()
5053 if (hw->mac.type >= e1000_pchlan) in e1000_initialize_hw_bits_ich8lan()
5069 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5084 if (hw->mac.type == e1000_ich8lan) { in e1000_initialize_hw_bits_ich8lan()
5090 /* work-around descriptor data corruption issue during nfs v2 udp in e1000_initialize_hw_bits_ich8lan()
5099 if (hw->mac.type == e1000_ich8lan) in e1000_initialize_hw_bits_ich8lan()
5104 if (hw->mac.type >= e1000_pch_lpt) { in e1000_initialize_hw_bits_ich8lan()
5109 reg = er32(CTRL); in e1000_initialize_hw_bits_ich8lan()
5111 ew32(CTRL, reg); in e1000_initialize_hw_bits_ich8lan()
5116 * e1000_setup_link_ich8lan - Setup flow control and link settings
5117 * @hw: pointer to the HW structure
5119 * Determines which flow control settings to use, then configures flow
5120 * control. Calls the appropriate media-specific link configuration
5125 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) in e1000_setup_link_ich8lan() argument
5129 if (hw->phy.ops.check_reset_block(hw)) in e1000_setup_link_ich8lan()
5133 * the default flow control setting, so we explicitly in e1000_setup_link_ich8lan()
5136 if (hw->fc.requested_mode == e1000_fc_default) { in e1000_setup_link_ich8lan()
5137 /* Workaround h/w hang when Tx flow control enabled */ in e1000_setup_link_ich8lan()
5138 if (hw->mac.type == e1000_pchlan) in e1000_setup_link_ich8lan()
5139 hw->fc.requested_mode = e1000_fc_rx_pause; in e1000_setup_link_ich8lan()
5141 hw->fc.requested_mode = e1000_fc_full; in e1000_setup_link_ich8lan()
5144 /* Save off the requested flow control mode for use later. Depending in e1000_setup_link_ich8lan()
5147 hw->fc.current_mode = hw->fc.requested_mode; in e1000_setup_link_ich8lan()
5149 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); in e1000_setup_link_ich8lan()
5152 ret_val = hw->mac.ops.setup_physical_interface(hw); in e1000_setup_link_ich8lan()
5156 ew32(FCTTV, hw->fc.pause_time); in e1000_setup_link_ich8lan()
5157 if ((hw->phy.type == e1000_phy_82578) || in e1000_setup_link_ich8lan()
5158 (hw->phy.type == e1000_phy_82579) || in e1000_setup_link_ich8lan()
5159 (hw->phy.type == e1000_phy_i217) || in e1000_setup_link_ich8lan()
5160 (hw->phy.type == e1000_phy_82577)) { in e1000_setup_link_ich8lan()
5161 ew32(FCRTV_PCH, hw->fc.refresh_time); in e1000_setup_link_ich8lan()
5163 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), in e1000_setup_link_ich8lan()
5164 hw->fc.pause_time); in e1000_setup_link_ich8lan()
5169 return e1000e_set_fc_watermarks(hw); in e1000_setup_link_ich8lan()
5173 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5174 * @hw: pointer to the HW structure
5180 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) in e1000_setup_copper_link_ich8lan() argument
5182 u32 ctrl; in e1000_setup_copper_link_ich8lan() local
5186 ctrl = er32(CTRL); in e1000_setup_copper_link_ich8lan()
5187 ctrl |= E1000_CTRL_SLU; in e1000_setup_copper_link_ich8lan()
5188 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); in e1000_setup_copper_link_ich8lan()
5189 ew32(CTRL, ctrl); in e1000_setup_copper_link_ich8lan()
5195 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); in e1000_setup_copper_link_ich8lan()
5198 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, in e1000_setup_copper_link_ich8lan()
5203 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, in e1000_setup_copper_link_ich8lan()
5208 switch (hw->phy.type) { in e1000_setup_copper_link_ich8lan()
5210 ret_val = e1000e_copper_link_setup_igp(hw); in e1000_setup_copper_link_ich8lan()
5216 ret_val = e1000e_copper_link_setup_m88(hw); in e1000_setup_copper_link_ich8lan()
5222 ret_val = e1000_copper_link_setup_82577(hw); in e1000_setup_copper_link_ich8lan()
5227 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); in e1000_setup_copper_link_ich8lan()
5233 switch (hw->phy.mdix) { in e1000_setup_copper_link_ich8lan()
5245 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); in e1000_setup_copper_link_ich8lan()
5253 return e1000e_setup_copper_link(hw); in e1000_setup_copper_link_ich8lan()
5257 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5258 * @hw: pointer to the HW structure
5264 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) in e1000_setup_copper_link_pch_lpt() argument
5266 u32 ctrl; in e1000_setup_copper_link_pch_lpt() local
5269 ctrl = er32(CTRL); in e1000_setup_copper_link_pch_lpt()
5270 ctrl |= E1000_CTRL_SLU; in e1000_setup_copper_link_pch_lpt()
5271 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); in e1000_setup_copper_link_pch_lpt()
5272 ew32(CTRL, ctrl); in e1000_setup_copper_link_pch_lpt()
5274 ret_val = e1000_copper_link_setup_82577(hw); in e1000_setup_copper_link_pch_lpt()
5278 return e1000e_setup_copper_link(hw); in e1000_setup_copper_link_pch_lpt()
5282 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5283 * @hw: pointer to the HW structure
5291 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, in e1000_get_link_up_info_ich8lan() argument
5296 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); in e1000_get_link_up_info_ich8lan()
5300 if ((hw->mac.type == e1000_ich8lan) && in e1000_get_link_up_info_ich8lan()
5301 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { in e1000_get_link_up_info_ich8lan()
5302 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); in e1000_get_link_up_info_ich8lan()
5309 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5310 * @hw: pointer to the HW structure
5312 * Work-around for 82566 Kumeran PCS lock loss:
5314 * speed is gigabit-
5323 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) in e1000_kmrn_lock_loss_workaround_ich8lan() argument
5325 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_kmrn_lock_loss_workaround_ich8lan()
5331 if (!dev_spec->kmrn_lock_loss_workaround_enabled) in e1000_kmrn_lock_loss_workaround_ich8lan()
5338 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); in e1000_kmrn_lock_loss_workaround_ich8lan()
5344 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); in e1000_kmrn_lock_loss_workaround_ich8lan()
5348 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); in e1000_kmrn_lock_loss_workaround_ich8lan()
5357 e1000_phy_hw_reset(hw); in e1000_kmrn_lock_loss_workaround_ich8lan()
5369 e1000e_gig_downshift_workaround_ich8lan(hw); in e1000_kmrn_lock_loss_workaround_ich8lan()
5372 return -E1000_ERR_PHY; in e1000_kmrn_lock_loss_workaround_ich8lan()
5376 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5377 * @hw: pointer to the HW structure
5380 * If ICH8, set the current Kumeran workaround state (enabled - true
5381 * /disabled - false).
5383 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, in e1000e_set_kmrn_lock_loss_workaround_ich8lan() argument
5386 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5388 if (hw->mac.type != e1000_ich8lan) { in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5393 dev_spec->kmrn_lock_loss_workaround_enabled = state; in e1000e_set_kmrn_lock_loss_workaround_ich8lan()
5397 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5398 * @hw: pointer to the HW structure
5400 * Workaround for 82566 power-down on D3 entry:
5402 * 2) write VR power-down enable
5406 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) in e1000e_igp3_phy_powerdown_workaround_ich8lan() argument
5412 if (hw->phy.type != e1000_phy_igp_3) in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5426 if (hw->mac.type == e1000_ich8lan) in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5427 e1000e_gig_downshift_workaround_ich8lan(hw); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5429 /* Write VR power-down enable */ in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5430 e1e_rphy(hw, IGP3_VR_CTRL, &data); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5432 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5435 e1e_rphy(hw, IGP3_VR_CTRL, &data); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5441 reg = er32(CTRL); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5442 ew32(CTRL, reg | E1000_CTRL_PHY_RST); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
5448 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5449 * @hw: pointer to the HW structure
5453 * 1) Set Kumeran Near-end loopback
5454 * 2) Clear Kumeran Near-end loopback
5457 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) in e1000e_gig_downshift_workaround_ich8lan() argument
5462 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) in e1000e_gig_downshift_workaround_ich8lan()
5465 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, in e1000e_gig_downshift_workaround_ich8lan()
5470 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, in e1000e_gig_downshift_workaround_ich8lan()
5475 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); in e1000e_gig_downshift_workaround_ich8lan()
5479 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5480 * @hw: pointer to the HW structure
5492 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) in e1000_suspend_workarounds_ich8lan() argument
5494 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; in e1000_suspend_workarounds_ich8lan()
5501 if (hw->phy.type == e1000_phy_i217) { in e1000_suspend_workarounds_ich8lan()
5502 u16 phy_reg, device_id = hw->adapter->pdev->device; in e1000_suspend_workarounds_ich8lan()
5508 (hw->mac.type >= e1000_pch_spt)) { in e1000_suspend_workarounds_ich8lan()
5514 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5518 if (!dev_spec->eee_disable) { in e1000_suspend_workarounds_ich8lan()
5522 e1000_read_emi_reg_locked(hw, in e1000_suspend_workarounds_ich8lan()
5534 (dev_spec->eee_lp_ability & in e1000_suspend_workarounds_ich8lan()
5536 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { in e1000_suspend_workarounds_ich8lan()
5541 e1e_rphy_locked(hw, in e1000_suspend_workarounds_ich8lan()
5544 e1e_wphy_locked(hw, in e1000_suspend_workarounds_ich8lan()
5558 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5560 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); in e1000_suspend_workarounds_ich8lan()
5565 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5567 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); in e1000_suspend_workarounds_ich8lan()
5570 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5572 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); in e1000_suspend_workarounds_ich8lan()
5578 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); in e1000_suspend_workarounds_ich8lan()
5580 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); in e1000_suspend_workarounds_ich8lan()
5583 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5588 if (hw->mac.type == e1000_ich8lan) in e1000_suspend_workarounds_ich8lan()
5589 e1000e_gig_downshift_workaround_ich8lan(hw); in e1000_suspend_workarounds_ich8lan()
5591 if (hw->mac.type >= e1000_pchlan) { in e1000_suspend_workarounds_ich8lan()
5592 e1000_oem_bits_config_ich8lan(hw, false); in e1000_suspend_workarounds_ich8lan()
5595 if (hw->mac.type == e1000_pchlan) in e1000_suspend_workarounds_ich8lan()
5596 e1000e_phy_hw_reset_generic(hw); in e1000_suspend_workarounds_ich8lan()
5598 ret_val = hw->phy.ops.acquire(hw); in e1000_suspend_workarounds_ich8lan()
5601 e1000_write_smbus_addr(hw); in e1000_suspend_workarounds_ich8lan()
5602 hw->phy.ops.release(hw); in e1000_suspend_workarounds_ich8lan()
5607 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5608 * @hw: pointer to the HW structure
5610 * During Sx to S0 transitions on non-managed devices or managed devices
5616 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) in e1000_resume_workarounds_pchlan() argument
5620 if (hw->mac.type < e1000_pch2lan) in e1000_resume_workarounds_pchlan()
5623 ret_val = e1000_init_phy_workarounds_pchlan(hw); in e1000_resume_workarounds_pchlan()
5625 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); in e1000_resume_workarounds_pchlan()
5634 if (hw->phy.type == e1000_phy_i217) { in e1000_resume_workarounds_pchlan()
5637 ret_val = hw->phy.ops.acquire(hw); in e1000_resume_workarounds_pchlan()
5644 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); in e1000_resume_workarounds_pchlan()
5646 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); in e1000_resume_workarounds_pchlan()
5652 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); in e1000_resume_workarounds_pchlan()
5656 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); in e1000_resume_workarounds_pchlan()
5659 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); in e1000_resume_workarounds_pchlan()
5662 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); in e1000_resume_workarounds_pchlan()
5666 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); in e1000_resume_workarounds_pchlan()
5670 hw->phy.ops.release(hw); in e1000_resume_workarounds_pchlan()
5675 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5676 * @hw: pointer to the HW structure
5680 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) in e1000_cleanup_led_ich8lan() argument
5682 if (hw->phy.type == e1000_phy_ife) in e1000_cleanup_led_ich8lan()
5683 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); in e1000_cleanup_led_ich8lan()
5685 ew32(LEDCTL, hw->mac.ledctl_default); in e1000_cleanup_led_ich8lan()
5690 * e1000_led_on_ich8lan - Turn LEDs on
5691 * @hw: pointer to the HW structure
5695 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) in e1000_led_on_ich8lan() argument
5697 if (hw->phy.type == e1000_phy_ife) in e1000_led_on_ich8lan()
5698 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_led_on_ich8lan()
5701 ew32(LEDCTL, hw->mac.ledctl_mode2); in e1000_led_on_ich8lan()
5706 * e1000_led_off_ich8lan - Turn LEDs off
5707 * @hw: pointer to the HW structure
5711 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) in e1000_led_off_ich8lan() argument
5713 if (hw->phy.type == e1000_phy_ife) in e1000_led_off_ich8lan()
5714 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, in e1000_led_off_ich8lan()
5718 ew32(LEDCTL, hw->mac.ledctl_mode1); in e1000_led_off_ich8lan()
5723 * e1000_setup_led_pchlan - Configures SW controllable LED
5724 * @hw: pointer to the HW structure
5728 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) in e1000_setup_led_pchlan() argument
5730 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); in e1000_setup_led_pchlan()
5734 * e1000_cleanup_led_pchlan - Restore the default LED operation
5735 * @hw: pointer to the HW structure
5739 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) in e1000_cleanup_led_pchlan() argument
5741 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); in e1000_cleanup_led_pchlan()
5745 * e1000_led_on_pchlan - Turn LEDs on
5746 * @hw: pointer to the HW structure
5750 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) in e1000_led_on_pchlan() argument
5752 u16 data = (u16)hw->mac.ledctl_mode2; in e1000_led_on_pchlan()
5771 return e1e_wphy(hw, HV_LED_CONFIG, data); in e1000_led_on_pchlan()
5775 * e1000_led_off_pchlan - Turn LEDs off
5776 * @hw: pointer to the HW structure
5780 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) in e1000_led_off_pchlan() argument
5782 u16 data = (u16)hw->mac.ledctl_mode1; in e1000_led_off_pchlan()
5801 return e1e_wphy(hw, HV_LED_CONFIG, data); in e1000_led_off_pchlan()
5805 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5806 * @hw: pointer to the HW structure
5809 * and configure the PHY through s/w for EEPROM-less parts.
5811 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5813 * to return with error, EEPROM-less silicon would not be able to be reset
5816 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) in e1000_get_cfg_done_ich8lan() argument
5822 e1000e_get_cfg_done_generic(hw); in e1000_get_cfg_done_ich8lan()
5825 if (hw->mac.type >= e1000_ich10lan) { in e1000_get_cfg_done_ich8lan()
5826 e1000_lan_init_done_ich8lan(hw); in e1000_get_cfg_done_ich8lan()
5828 ret_val = e1000e_get_auto_rd_done(hw); in e1000_get_cfg_done_ich8lan()
5844 e_dbg("PHY Reset Asserted not set - needs delay\n"); in e1000_get_cfg_done_ich8lan()
5847 if (hw->mac.type <= e1000_ich9lan) { in e1000_get_cfg_done_ich8lan()
5849 (hw->phy.type == e1000_phy_igp_3)) { in e1000_get_cfg_done_ich8lan()
5850 e1000e_phy_init_script_igp3(hw); in e1000_get_cfg_done_ich8lan()
5853 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { in e1000_get_cfg_done_ich8lan()
5856 ret_val = -E1000_ERR_CONFIG; in e1000_get_cfg_done_ich8lan()
5864 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5865 * @hw: pointer to the HW structure
5870 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) in e1000_power_down_phy_copper_ich8lan() argument
5873 if (!(hw->mac.ops.check_mng_mode(hw) || in e1000_power_down_phy_copper_ich8lan()
5874 hw->phy.ops.check_reset_block(hw))) in e1000_power_down_phy_copper_ich8lan()
5875 e1000_power_down_phy_copper(hw); in e1000_power_down_phy_copper_ich8lan()
5879 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5880 * @hw: pointer to the HW structure
5885 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) in e1000_clear_hw_cntrs_ich8lan() argument
5890 e1000e_clear_hw_cntrs_base(hw); in e1000_clear_hw_cntrs_ich8lan()
5907 if ((hw->phy.type == e1000_phy_82578) || in e1000_clear_hw_cntrs_ich8lan()
5908 (hw->phy.type == e1000_phy_82579) || in e1000_clear_hw_cntrs_ich8lan()
5909 (hw->phy.type == e1000_phy_i217) || in e1000_clear_hw_cntrs_ich8lan()
5910 (hw->phy.type == e1000_phy_82577)) { in e1000_clear_hw_cntrs_ich8lan()
5911 ret_val = hw->phy.ops.acquire(hw); in e1000_clear_hw_cntrs_ich8lan()
5914 ret_val = hw->phy.ops.set_page(hw, in e1000_clear_hw_cntrs_ich8lan()
5918 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5919 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5920 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5921 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5922 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5923 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5924 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5925 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5926 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5927 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5928 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5929 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5930 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5931 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); in e1000_clear_hw_cntrs_ich8lan()
5933 hw->phy.ops.release(hw); in e1000_clear_hw_cntrs_ich8lan()