Lines Matching +full:auto +full:- +full:flow +full:- +full:control
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
12 /* Wake Up Control */
19 /* Wake Up Filter Control */
34 /* Extended Device Control */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
99 /* Management Control */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
115 /* Receive Control */
143 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
179 /* Device Control */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
192 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
201 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
202 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
238 /* 1000/H is not supported, nor spec-compliant. */
251 /* LED Control */
287 /* Transmit Control */
292 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
295 /* SerDes Control */
299 /* Receive Checksum Control */
333 /* Extended Configuration Control and Size */
351 /* Low Power IDLE Control */
457 /* Transmit Descriptor Control */
467 /* Flow Control Constants */
504 /* Loop limit on how long we wait for auto-negotiation to complete */
515 /* Number of milliseconds for NVM auto read done after MAC reset. */
518 /* Flow Control */
528 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
563 /* PCI Express Control */
578 /* NVM Control */
587 /* NVM Addressing bits based on type (0-small, 1-large) */
590 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
647 /* NVM Commands - SPI */
651 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
679 /* PCI/PCI-X/PCI-EX Config space */
683 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
708 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
710 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
715 /* M88E1000 PHY Specific Control Register */
720 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
722 /* Auto crossover enabled all speeds */
730 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
756 /* BME1000 PHY Specific Control Register */
760 * 15-5: page
761 * 4-0: register offset
770 GG82563_REG(0, 16) /* PHY Specific Control */
774 GG82563_REG(0, 26) /* PHY Specific Control 2 */
779 GG82563_REG(2, 21) /* MAC Specific Control Register */
784 /* Page 193 - Port Control Registers */
786 GG82563_REG(193, 16) /* Kumeran Mode Control */
788 GG82563_REG(193, 20) /* Power Management Control */
790 /* Page 194 - KMRN Registers */
792 GG82563_REG(194, 18) /* Inband Control */
794 /* MDI Control */
803 /* SerDes Control */