Lines Matching +full:cfg +full:- +full:space
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
20 iowrite32be(val, &priv->db_bar2[be32_to_cpu(q_resources->db_index)]); in gve_tx_put_doorbell()
26 struct gve_tx_ring *tx = &priv->tx[tx_qid]; in gve_xdp_tx_flush()
28 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_xdp_tx_flush()
35 * gve_tx_fifo_* manages the Registered Segment as a FIFO - clients must
41 fifo->base = vmap(fifo->qpl->pages, fifo->qpl->num_entries, VM_MAP, in gve_tx_fifo_init()
43 if (unlikely(!fifo->base)) { in gve_tx_fifo_init()
44 netif_err(priv, drv, priv->dev, "Failed to vmap fifo, qpl_id = %d\n", in gve_tx_fifo_init()
45 fifo->qpl->id); in gve_tx_fifo_init()
46 return -ENOMEM; in gve_tx_fifo_init()
49 fifo->size = fifo->qpl->num_entries * PAGE_SIZE; in gve_tx_fifo_init()
50 atomic_set(&fifo->available, fifo->size); in gve_tx_fifo_init()
51 fifo->head = 0; in gve_tx_fifo_init()
57 WARN(atomic_read(&fifo->available) != fifo->size, in gve_tx_fifo_release()
58 "Releasing non-empty fifo"); in gve_tx_fifo_release()
60 vunmap(fifo->base); in gve_tx_fifo_release()
66 return (fifo->head + bytes < fifo->size) ? 0 : fifo->size - fifo->head; in gve_tx_fifo_pad_alloc_one_frag()
71 return (atomic_read(&fifo->available) <= bytes) ? false : true; in gve_tx_fifo_can_alloc()
74 /* gve_tx_alloc_fifo - Allocate fragment(s) from Tx FIFO
77 * @iov: Scatter-gather elements to fill with allocation fragment base/len
97 * are aligned, so if there is space for the data, there is space for in gve_tx_alloc_fifo()
101 "Reached %s when there's not enough space in the fifo", __func__); in gve_tx_alloc_fifo()
105 iov[0].iov_offset = fifo->head; in gve_tx_alloc_fifo()
107 fifo->head += bytes; in gve_tx_alloc_fifo()
109 if (fifo->head > fifo->size) { in gve_tx_alloc_fifo()
114 overflow = fifo->head - fifo->size; in gve_tx_alloc_fifo()
115 iov[0].iov_len -= overflow; in gve_tx_alloc_fifo()
119 fifo->head = overflow; in gve_tx_alloc_fifo()
122 /* Re-align to a cacheline boundary */ in gve_tx_alloc_fifo()
123 aligned_head = L1_CACHE_ALIGN(fifo->head); in gve_tx_alloc_fifo()
124 padding = aligned_head - fifo->head; in gve_tx_alloc_fifo()
125 iov[nfrags - 1].iov_padding = padding; in gve_tx_alloc_fifo()
126 atomic_sub(bytes + padding, &fifo->available); in gve_tx_alloc_fifo()
127 fifo->head = aligned_head; in gve_tx_alloc_fifo()
129 if (fifo->head == fifo->size) in gve_tx_alloc_fifo()
130 fifo->head = 0; in gve_tx_alloc_fifo()
135 /* gve_tx_free_fifo - Return space to Tx FIFO
141 atomic_add(bytes, &fifo->available); in gve_tx_free_fifo()
149 for (i = 0; i < ARRAY_SIZE(info->iov); i++) { in gve_tx_clear_buffer_state()
150 space_freed += info->iov[i].iov_len + info->iov[i].iov_padding; in gve_tx_clear_buffer_state()
151 info->iov[i].iov_len = 0; in gve_tx_clear_buffer_state()
152 info->iov[i].iov_padding = 0; in gve_tx_clear_buffer_state()
168 idx = tx->done & tx->mask; in gve_clean_xdp_done()
169 info = &tx->info[idx]; in gve_clean_xdp_done()
170 tx->done++; in gve_clean_xdp_done()
172 if (unlikely(!info->xdp.size)) in gve_clean_xdp_done()
175 bytes += info->xdp.size; in gve_clean_xdp_done()
177 xsk_complete += info->xdp.is_xsk; in gve_clean_xdp_done()
179 info->xdp.size = 0; in gve_clean_xdp_done()
180 if (info->xdp_frame) { in gve_clean_xdp_done()
181 xdp_return_frame(info->xdp_frame); in gve_clean_xdp_done()
182 info->xdp_frame = NULL; in gve_clean_xdp_done()
187 gve_tx_free_fifo(&tx->tx_fifo, space_freed); in gve_clean_xdp_done()
188 if (xsk_complete > 0 && tx->xsk_pool) in gve_clean_xdp_done()
189 xsk_tx_completed(tx->xsk_pool, xsk_complete); in gve_clean_xdp_done()
190 u64_stats_update_begin(&tx->statss); in gve_clean_xdp_done()
191 tx->bytes_done += bytes; in gve_clean_xdp_done()
192 tx->pkt_done += pkts; in gve_clean_xdp_done()
193 u64_stats_update_end(&tx->statss); in gve_clean_xdp_done()
203 struct gve_tx_ring *tx = &priv->tx[idx]; in gve_tx_stop_ring_gqi()
209 if (tx->q_num < priv->tx_cfg.num_queues) in gve_tx_stop_ring_gqi()
210 gve_clean_tx_done(priv, tx, priv->tx_desc_cnt, false); in gve_tx_stop_ring_gqi()
212 gve_clean_xdp_done(priv, tx, priv->tx_desc_cnt); in gve_tx_stop_ring_gqi()
213 netdev_tx_reset_queue(tx->netdev_txq); in gve_tx_stop_ring_gqi()
218 struct gve_tx_alloc_rings_cfg *cfg) in gve_tx_free_ring_gqi() argument
220 struct device *hdev = &priv->pdev->dev; in gve_tx_free_ring_gqi()
221 int idx = tx->q_num; in gve_tx_free_ring_gqi()
226 slots = tx->mask + 1; in gve_tx_free_ring_gqi()
227 dma_free_coherent(hdev, sizeof(*tx->q_resources), in gve_tx_free_ring_gqi()
228 tx->q_resources, tx->q_resources_bus); in gve_tx_free_ring_gqi()
229 tx->q_resources = NULL; in gve_tx_free_ring_gqi()
231 if (tx->tx_fifo.qpl) { in gve_tx_free_ring_gqi()
232 if (tx->tx_fifo.base) in gve_tx_free_ring_gqi()
233 gve_tx_fifo_release(priv, &tx->tx_fifo); in gve_tx_free_ring_gqi()
235 qpl_id = gve_tx_qpl_id(priv, tx->q_num); in gve_tx_free_ring_gqi()
236 gve_free_queue_page_list(priv, tx->tx_fifo.qpl, qpl_id); in gve_tx_free_ring_gqi()
237 tx->tx_fifo.qpl = NULL; in gve_tx_free_ring_gqi()
240 bytes = sizeof(*tx->desc) * slots; in gve_tx_free_ring_gqi()
241 dma_free_coherent(hdev, bytes, tx->desc, tx->bus); in gve_tx_free_ring_gqi()
242 tx->desc = NULL; in gve_tx_free_ring_gqi()
244 vfree(tx->info); in gve_tx_free_ring_gqi()
245 tx->info = NULL; in gve_tx_free_ring_gqi()
247 netif_dbg(priv, drv, priv->dev, "freed tx queue %d\n", idx); in gve_tx_free_ring_gqi()
253 struct gve_tx_ring *tx = &priv->tx[idx]; in gve_tx_start_ring_gqi()
257 tx->netdev_txq = netdev_get_tx_queue(priv->dev, idx); in gve_tx_start_ring_gqi()
262 struct gve_tx_alloc_rings_cfg *cfg, in gve_tx_alloc_ring_gqi() argument
266 struct device *hdev = &priv->pdev->dev; in gve_tx_alloc_ring_gqi()
273 spin_lock_init(&tx->clean_lock); in gve_tx_alloc_ring_gqi()
274 spin_lock_init(&tx->xdp_lock); in gve_tx_alloc_ring_gqi()
275 tx->q_num = idx; in gve_tx_alloc_ring_gqi()
277 tx->mask = cfg->ring_size - 1; in gve_tx_alloc_ring_gqi()
280 tx->info = vcalloc(cfg->ring_size, sizeof(*tx->info)); in gve_tx_alloc_ring_gqi()
281 if (!tx->info) in gve_tx_alloc_ring_gqi()
282 return -ENOMEM; in gve_tx_alloc_ring_gqi()
285 bytes = sizeof(*tx->desc) * cfg->ring_size; in gve_tx_alloc_ring_gqi()
286 tx->desc = dma_alloc_coherent(hdev, bytes, &tx->bus, GFP_KERNEL); in gve_tx_alloc_ring_gqi()
287 if (!tx->desc) in gve_tx_alloc_ring_gqi()
290 tx->raw_addressing = cfg->raw_addressing; in gve_tx_alloc_ring_gqi()
291 tx->dev = hdev; in gve_tx_alloc_ring_gqi()
292 if (!tx->raw_addressing) { in gve_tx_alloc_ring_gqi()
293 qpl_id = gve_tx_qpl_id(priv, tx->q_num); in gve_tx_alloc_ring_gqi()
294 qpl_page_cnt = priv->tx_pages_per_qpl; in gve_tx_alloc_ring_gqi()
296 tx->tx_fifo.qpl = gve_alloc_queue_page_list(priv, qpl_id, in gve_tx_alloc_ring_gqi()
298 if (!tx->tx_fifo.qpl) in gve_tx_alloc_ring_gqi()
302 if (gve_tx_fifo_init(priv, &tx->tx_fifo)) in gve_tx_alloc_ring_gqi()
306 tx->q_resources = in gve_tx_alloc_ring_gqi()
308 sizeof(*tx->q_resources), in gve_tx_alloc_ring_gqi()
309 &tx->q_resources_bus, in gve_tx_alloc_ring_gqi()
311 if (!tx->q_resources) in gve_tx_alloc_ring_gqi()
317 if (!tx->raw_addressing) in gve_tx_alloc_ring_gqi()
318 gve_tx_fifo_release(priv, &tx->tx_fifo); in gve_tx_alloc_ring_gqi()
320 if (!tx->raw_addressing) { in gve_tx_alloc_ring_gqi()
321 gve_free_queue_page_list(priv, tx->tx_fifo.qpl, qpl_id); in gve_tx_alloc_ring_gqi()
322 tx->tx_fifo.qpl = NULL; in gve_tx_alloc_ring_gqi()
325 dma_free_coherent(hdev, bytes, tx->desc, tx->bus); in gve_tx_alloc_ring_gqi()
326 tx->desc = NULL; in gve_tx_alloc_ring_gqi()
328 vfree(tx->info); in gve_tx_alloc_ring_gqi()
329 tx->info = NULL; in gve_tx_alloc_ring_gqi()
330 return -ENOMEM; in gve_tx_alloc_ring_gqi()
334 struct gve_tx_alloc_rings_cfg *cfg) in gve_tx_alloc_rings_gqi() argument
336 struct gve_tx_ring *tx = cfg->tx; in gve_tx_alloc_rings_gqi()
340 if (cfg->start_idx + cfg->num_rings > cfg->qcfg->max_queues) { in gve_tx_alloc_rings_gqi()
341 netif_err(priv, drv, priv->dev, in gve_tx_alloc_rings_gqi()
343 return -EINVAL; in gve_tx_alloc_rings_gqi()
346 if (cfg->start_idx == 0) { in gve_tx_alloc_rings_gqi()
347 tx = kvcalloc(cfg->qcfg->max_queues, sizeof(struct gve_tx_ring), in gve_tx_alloc_rings_gqi()
350 return -ENOMEM; in gve_tx_alloc_rings_gqi()
352 netif_err(priv, drv, priv->dev, in gve_tx_alloc_rings_gqi()
354 return -EINVAL; in gve_tx_alloc_rings_gqi()
357 for (i = cfg->start_idx; i < cfg->start_idx + cfg->num_rings; i++) { in gve_tx_alloc_rings_gqi()
358 err = gve_tx_alloc_ring_gqi(priv, cfg, &tx[i], i); in gve_tx_alloc_rings_gqi()
360 netif_err(priv, drv, priv->dev, in gve_tx_alloc_rings_gqi()
367 cfg->tx = tx; in gve_tx_alloc_rings_gqi()
372 gve_tx_free_ring_gqi(priv, &tx[j], cfg); in gve_tx_alloc_rings_gqi()
373 if (cfg->start_idx == 0) in gve_tx_alloc_rings_gqi()
379 struct gve_tx_alloc_rings_cfg *cfg) in gve_tx_free_rings_gqi() argument
381 struct gve_tx_ring *tx = cfg->tx; in gve_tx_free_rings_gqi()
387 for (i = cfg->start_idx; i < cfg->start_idx + cfg->num_rings; i++) in gve_tx_free_rings_gqi()
388 gve_tx_free_ring_gqi(priv, &tx[i], cfg); in gve_tx_free_rings_gqi()
390 if (cfg->start_idx == 0) { in gve_tx_free_rings_gqi()
392 cfg->tx = NULL; in gve_tx_free_rings_gqi()
396 /* gve_tx_avail - Calculates the number of slots available in the ring
405 return tx->mask + 1 - (tx->req - tx->done); in gve_tx_avail()
416 min_t(int, GVE_GQ_TX_MIN_PKT_DESC_BYTES, skb->len); in gve_skb_fifo_bytes_required()
418 pad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo, in gve_skb_fifo_bytes_required()
421 align_hdr_pad = L1_CACHE_ALIGN(hlen) - hlen; in gve_skb_fifo_bytes_required()
422 bytes = align_hdr_pad + pad_bytes + skb->len; in gve_skb_fifo_bytes_required()
437 if (info->skb) { in gve_tx_unmap_buf()
450 /* Check if sufficient resources (descriptor ring space, FIFO space) are
457 if (!tx->raw_addressing) in gve_can_tx()
458 can_alloc = gve_tx_fifo_can_alloc(&tx->tx_fifo, bytes_required); in gve_can_tx()
474 if (!tx->raw_addressing) in gve_maybe_stop_tx()
480 ret = -EBUSY; in gve_maybe_stop_tx()
481 spin_lock(&tx->clean_lock); in gve_maybe_stop_tx()
483 to_do = nic_done - tx->done; in gve_maybe_stop_tx()
495 /* No space, so stop the queue */ in gve_maybe_stop_tx()
496 tx->stop_queue++; in gve_maybe_stop_tx()
497 netif_tx_stop_queue(tx->netdev_txq); in gve_maybe_stop_tx()
499 spin_unlock(&tx->clean_lock); in gve_maybe_stop_tx()
509 /* l4_hdr_offset and csum_offset are in units of 16-bit words */ in gve_tx_fill_pkt_desc()
511 pkt_desc->pkt.type_flags = GVE_TXD_TSO | GVE_TXF_L4CSUM; in gve_tx_fill_pkt_desc()
512 pkt_desc->pkt.l4_csum_offset = csum_offset >> 1; in gve_tx_fill_pkt_desc()
513 pkt_desc->pkt.l4_hdr_offset = l4_hdr_offset >> 1; in gve_tx_fill_pkt_desc()
515 pkt_desc->pkt.type_flags = GVE_TXD_STD | GVE_TXF_L4CSUM; in gve_tx_fill_pkt_desc()
516 pkt_desc->pkt.l4_csum_offset = csum_offset >> 1; in gve_tx_fill_pkt_desc()
517 pkt_desc->pkt.l4_hdr_offset = l4_hdr_offset >> 1; in gve_tx_fill_pkt_desc()
519 pkt_desc->pkt.type_flags = GVE_TXD_STD; in gve_tx_fill_pkt_desc()
520 pkt_desc->pkt.l4_csum_offset = 0; in gve_tx_fill_pkt_desc()
521 pkt_desc->pkt.l4_hdr_offset = 0; in gve_tx_fill_pkt_desc()
523 pkt_desc->pkt.desc_cnt = desc_cnt; in gve_tx_fill_pkt_desc()
524 pkt_desc->pkt.len = cpu_to_be16(pkt_len); in gve_tx_fill_pkt_desc()
525 pkt_desc->pkt.seg_len = cpu_to_be16(hlen); in gve_tx_fill_pkt_desc()
526 pkt_desc->pkt.seg_addr = cpu_to_be64(addr); in gve_tx_fill_pkt_desc()
532 BUILD_BUG_ON(sizeof(mtd_desc->mtd) != sizeof(mtd_desc->pkt)); in gve_tx_fill_mtd_desc()
534 mtd_desc->mtd.type_flags = GVE_TXD_MTD | GVE_MTD_SUBTYPE_PATH; in gve_tx_fill_mtd_desc()
535 mtd_desc->mtd.path_state = GVE_MTD_PATH_STATE_DEFAULT | in gve_tx_fill_mtd_desc()
537 mtd_desc->mtd.path_hash = cpu_to_be32(skb->hash); in gve_tx_fill_mtd_desc()
538 mtd_desc->mtd.reserved0 = 0; in gve_tx_fill_mtd_desc()
539 mtd_desc->mtd.reserved1 = 0; in gve_tx_fill_mtd_desc()
547 seg_desc->seg.type_flags = GVE_TXD_SEG; in gve_tx_fill_seg_desc()
550 seg_desc->seg.type_flags |= GVE_TXSF_IPV6; in gve_tx_fill_seg_desc()
551 seg_desc->seg.l3_offset = l3_offset >> 1; in gve_tx_fill_seg_desc()
552 seg_desc->seg.mss = cpu_to_be16(gso_size); in gve_tx_fill_seg_desc()
554 seg_desc->seg.seg_len = cpu_to_be16(len); in gve_tx_fill_seg_desc()
555 seg_desc->seg.seg_addr = cpu_to_be64(addr); in gve_tx_fill_seg_desc()
561 u64 last_page = (iov_offset + iov_len - 1) / PAGE_SIZE; in gve_dma_sync_for_device()
574 int mtd_desc_nr = !!skb->l4_hash; in gve_tx_add_skb_copy()
576 u32 idx = tx->req & tx->mask; in gve_tx_add_skb_copy()
582 info = &tx->info[idx]; in gve_tx_add_skb_copy()
583 pkt_desc = &tx->desc[idx]; in gve_tx_add_skb_copy()
590 min_t(int, GVE_GQ_TX_MIN_PKT_DESC_BYTES, skb->len); in gve_tx_add_skb_copy()
592 info->skb = skb; in gve_tx_add_skb_copy()
596 pad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo, hlen); in gve_tx_add_skb_copy()
597 hdr_nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, hlen + pad_bytes, in gve_tx_add_skb_copy()
598 &info->iov[0]); in gve_tx_add_skb_copy()
600 payload_nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, skb->len - hlen, in gve_tx_add_skb_copy()
601 &info->iov[payload_iov]); in gve_tx_add_skb_copy()
603 gve_tx_fill_pkt_desc(pkt_desc, skb->csum_offset, skb->ip_summed, in gve_tx_add_skb_copy()
606 info->iov[hdr_nfrags - 1].iov_offset, skb->len); in gve_tx_add_skb_copy()
609 tx->tx_fifo.base + info->iov[hdr_nfrags - 1].iov_offset, in gve_tx_add_skb_copy()
611 gve_dma_sync_for_device(&priv->pdev->dev, tx->tx_fifo.qpl->page_buses, in gve_tx_add_skb_copy()
612 info->iov[hdr_nfrags - 1].iov_offset, in gve_tx_add_skb_copy()
613 info->iov[hdr_nfrags - 1].iov_len); in gve_tx_add_skb_copy()
617 next_idx = (tx->req + 1) & tx->mask; in gve_tx_add_skb_copy()
618 gve_tx_fill_mtd_desc(&tx->desc[next_idx], skb); in gve_tx_add_skb_copy()
622 next_idx = (tx->req + 1 + mtd_desc_nr + i - payload_iov) & tx->mask; in gve_tx_add_skb_copy()
623 seg_desc = &tx->desc[next_idx]; in gve_tx_add_skb_copy()
626 skb_shinfo(skb)->gso_size, in gve_tx_add_skb_copy()
628 info->iov[i].iov_len, in gve_tx_add_skb_copy()
629 info->iov[i].iov_offset); in gve_tx_add_skb_copy()
632 tx->tx_fifo.base + info->iov[i].iov_offset, in gve_tx_add_skb_copy()
633 info->iov[i].iov_len); in gve_tx_add_skb_copy()
634 gve_dma_sync_for_device(&priv->pdev->dev, tx->tx_fifo.qpl->page_buses, in gve_tx_add_skb_copy()
635 info->iov[i].iov_offset, in gve_tx_add_skb_copy()
636 info->iov[i].iov_len); in gve_tx_add_skb_copy()
637 copy_offset += info->iov[i].iov_len; in gve_tx_add_skb_copy()
650 int mtd_desc_nr = !!skb->l4_hash; in gve_tx_add_skb_no_copy()
652 u32 idx = tx->req & tx->mask; in gve_tx_add_skb_no_copy()
657 info = &tx->info[idx]; in gve_tx_add_skb_no_copy()
658 pkt_desc = &tx->desc[idx]; in gve_tx_add_skb_no_copy()
663 * of the skb (which will contain the checksum because skb->csum_start and in gve_tx_add_skb_no_copy()
664 * skb->csum_offset are given relative to skb->head) in the first segment. in gve_tx_add_skb_no_copy()
669 info->skb = skb; in gve_tx_add_skb_no_copy()
671 addr = dma_map_single(tx->dev, skb->data, len, DMA_TO_DEVICE); in gve_tx_add_skb_no_copy()
672 if (unlikely(dma_mapping_error(tx->dev, addr))) { in gve_tx_add_skb_no_copy()
673 tx->dma_mapping_error++; in gve_tx_add_skb_no_copy()
679 num_descriptors = 1 + shinfo->nr_frags; in gve_tx_add_skb_no_copy()
685 gve_tx_fill_pkt_desc(pkt_desc, skb->csum_offset, skb->ip_summed, in gve_tx_add_skb_no_copy()
687 num_descriptors, hlen, addr, skb->len); in gve_tx_add_skb_no_copy()
690 idx = (idx + 1) & tx->mask; in gve_tx_add_skb_no_copy()
691 mtd_desc = &tx->desc[idx]; in gve_tx_add_skb_no_copy()
699 len -= hlen; in gve_tx_add_skb_no_copy()
701 idx = (idx + 1) & tx->mask; in gve_tx_add_skb_no_copy()
702 seg_desc = &tx->desc[idx]; in gve_tx_add_skb_no_copy()
704 skb_shinfo(skb)->gso_size, in gve_tx_add_skb_no_copy()
708 for (i = 0; i < shinfo->nr_frags; i++) { in gve_tx_add_skb_no_copy()
709 const skb_frag_t *frag = &shinfo->frags[i]; in gve_tx_add_skb_no_copy()
711 idx = (idx + 1) & tx->mask; in gve_tx_add_skb_no_copy()
712 seg_desc = &tx->desc[idx]; in gve_tx_add_skb_no_copy()
714 addr = skb_frag_dma_map(tx->dev, frag, 0, len, DMA_TO_DEVICE); in gve_tx_add_skb_no_copy()
715 if (unlikely(dma_mapping_error(tx->dev, addr))) { in gve_tx_add_skb_no_copy()
716 tx->dma_mapping_error++; in gve_tx_add_skb_no_copy()
719 tx->info[idx].skb = NULL; in gve_tx_add_skb_no_copy()
720 dma_unmap_len_set(&tx->info[idx], len, len); in gve_tx_add_skb_no_copy()
721 dma_unmap_addr_set(&tx->info[idx], dma, addr); in gve_tx_add_skb_no_copy()
724 skb_shinfo(skb)->gso_size, in gve_tx_add_skb_no_copy()
731 i += num_descriptors - shinfo->nr_frags; in gve_tx_add_skb_no_copy()
732 while (i--) { in gve_tx_add_skb_no_copy()
736 idx--; in gve_tx_add_skb_no_copy()
737 gve_tx_unmap_buf(tx->dev, &tx->info[idx & tx->mask]); in gve_tx_add_skb_no_copy()
740 tx->dropped_pkt++; in gve_tx_add_skb_no_copy()
750 WARN(skb_get_queue_mapping(skb) >= priv->tx_cfg.num_queues, in gve_tx()
752 tx = &priv->tx[skb_get_queue_mapping(skb)]; in gve_tx()
754 /* We need to ring the txq doorbell -- we have stopped the Tx in gve_tx()
759 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_tx()
762 if (tx->raw_addressing) in gve_tx()
769 netdev_tx_sent_queue(tx->netdev_txq, skb->len); in gve_tx()
771 tx->req += nsegs; in gve_tx()
776 if (!netif_xmit_stopped(tx->netdev_txq) && netdev_xmit_more()) in gve_tx()
782 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_tx()
791 u32 reqi = tx->req; in gve_tx_fill_xdp()
793 pad = gve_tx_fifo_pad_alloc_one_frag(&tx->tx_fifo, len); in gve_tx_fill_xdp()
796 info = &tx->info[reqi & tx->mask]; in gve_tx_fill_xdp()
797 info->xdp_frame = frame_p; in gve_tx_fill_xdp()
798 info->xdp.size = len; in gve_tx_fill_xdp()
799 info->xdp.is_xsk = is_xsk; in gve_tx_fill_xdp()
801 nfrags = gve_tx_alloc_fifo(&tx->tx_fifo, pad + len, in gve_tx_fill_xdp()
802 &info->iov[0]); in gve_tx_fill_xdp()
804 ndescs = nfrags - iovi; in gve_tx_fill_xdp()
809 gve_tx_fill_pkt_desc(&tx->desc[reqi & tx->mask], 0, in gve_tx_fill_xdp()
811 info->iov[iovi].iov_len, in gve_tx_fill_xdp()
812 info->iov[iovi].iov_offset, len); in gve_tx_fill_xdp()
814 gve_tx_fill_seg_desc(&tx->desc[reqi & tx->mask], in gve_tx_fill_xdp()
816 info->iov[iovi].iov_len, in gve_tx_fill_xdp()
817 info->iov[iovi].iov_offset); in gve_tx_fill_xdp()
819 memcpy(tx->tx_fifo.base + info->iov[iovi].iov_offset, in gve_tx_fill_xdp()
820 data + offset, info->iov[iovi].iov_len); in gve_tx_fill_xdp()
821 gve_dma_sync_for_device(&priv->pdev->dev, in gve_tx_fill_xdp()
822 tx->tx_fifo.qpl->page_buses, in gve_tx_fill_xdp()
823 info->iov[iovi].iov_offset, in gve_tx_fill_xdp()
824 info->iov[iovi].iov_len); in gve_tx_fill_xdp()
825 offset += info->iov[iovi].iov_len; in gve_tx_fill_xdp()
840 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK) || !priv->xdp_prog) in gve_xdp_xmit()
841 return -EINVAL; in gve_xdp_xmit()
844 return -ENETDOWN; in gve_xdp_xmit()
847 smp_processor_id() % priv->num_xdp_queues); in gve_xdp_xmit()
849 tx = &priv->tx[qid]; in gve_xdp_xmit()
851 spin_lock(&tx->xdp_lock); in gve_xdp_xmit()
853 err = gve_xdp_xmit_one(priv, tx, frames[i]->data, in gve_xdp_xmit()
854 frames[i]->len, frames[i]); in gve_xdp_xmit()
860 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_xdp_xmit()
862 spin_unlock(&tx->xdp_lock); in gve_xdp_xmit()
864 u64_stats_update_begin(&tx->statss); in gve_xdp_xmit()
865 tx->xdp_xmit += n; in gve_xdp_xmit()
866 tx->xdp_xmit_errors += n - i; in gve_xdp_xmit()
867 u64_stats_update_end(&tx->statss); in gve_xdp_xmit()
877 if (!gve_can_tx(tx, len + GVE_GQ_TX_MIN_PKT_DESC_BYTES - 1)) in gve_xdp_xmit_one()
878 return -EBUSY; in gve_xdp_xmit_one()
881 tx->req += nsegs; in gve_xdp_xmit_one()
899 idx = tx->done & tx->mask; in gve_clean_tx_done()
900 netif_info(priv, tx_done, priv->dev, in gve_clean_tx_done()
902 tx->q_num, __func__, idx, tx->req, tx->done); in gve_clean_tx_done()
903 info = &tx->info[idx]; in gve_clean_tx_done()
904 skb = info->skb; in gve_clean_tx_done()
907 if (tx->raw_addressing) in gve_clean_tx_done()
908 gve_tx_unmap_buf(tx->dev, info); in gve_clean_tx_done()
909 tx->done++; in gve_clean_tx_done()
912 info->skb = NULL; in gve_clean_tx_done()
913 bytes += skb->len; in gve_clean_tx_done()
916 if (tx->raw_addressing) in gve_clean_tx_done()
922 if (!tx->raw_addressing) in gve_clean_tx_done()
923 gve_tx_free_fifo(&tx->tx_fifo, space_freed); in gve_clean_tx_done()
924 u64_stats_update_begin(&tx->statss); in gve_clean_tx_done()
925 tx->bytes_done += bytes; in gve_clean_tx_done()
926 tx->pkt_done += pkts; in gve_clean_tx_done()
927 u64_stats_update_end(&tx->statss); in gve_clean_tx_done()
928 netdev_tx_completed_queue(tx->netdev_txq, pkts, bytes); in gve_clean_tx_done()
935 if (try_to_wake && netif_tx_queue_stopped(tx->netdev_txq) && in gve_clean_tx_done()
937 tx->wake_queue++; in gve_clean_tx_done()
938 netif_tx_wake_queue(tx->netdev_txq); in gve_clean_tx_done()
947 u32 counter_index = be32_to_cpu(tx->q_resources->counter_index); in gve_tx_load_event_counter()
948 __be32 counter = READ_ONCE(priv->counter_array[counter_index]); in gve_tx_load_event_counter()
960 spin_lock(&tx->xdp_lock); in gve_xsk_tx()
965 if (!xsk_tx_peek_desc(tx->xsk_pool, &desc)) { in gve_xsk_tx()
966 tx->xdp_xsk_done = tx->xdp_xsk_wakeup; in gve_xsk_tx()
970 data = xsk_buff_raw_get_data(tx->xsk_pool, desc.addr); in gve_xsk_tx()
972 tx->req += nsegs; in gve_xsk_tx()
977 gve_tx_put_doorbell(priv, tx->q_resources, tx->req); in gve_xsk_tx()
978 xsk_tx_release(tx->xsk_pool); in gve_xsk_tx()
980 spin_unlock(&tx->xdp_lock); in gve_xsk_tx()
986 struct gve_rx_ring *rx = rx_block->rx; in gve_xsk_tx_poll()
987 struct gve_priv *priv = rx->gve; in gve_xsk_tx_poll()
991 tx = &priv->tx[gve_xdp_tx_queue_id(priv, rx->q_num)]; in gve_xsk_tx_poll()
992 if (tx->xsk_pool) { in gve_xsk_tx_poll()
995 u64_stats_update_begin(&tx->statss); in gve_xsk_tx_poll()
996 tx->xdp_xsk_sent += sent; in gve_xsk_tx_poll()
997 u64_stats_update_end(&tx->statss); in gve_xsk_tx_poll()
998 if (xsk_uses_need_wakeup(tx->xsk_pool)) in gve_xsk_tx_poll()
999 xsk_set_tx_need_wakeup(tx->xsk_pool); in gve_xsk_tx_poll()
1007 struct gve_priv *priv = block->priv; in gve_xdp_poll()
1008 struct gve_tx_ring *tx = block->tx; in gve_xdp_poll()
1014 to_do = min_t(u32, (nic_done - tx->done), budget); in gve_xdp_poll()
1018 return nic_done != tx->done; in gve_xdp_poll()
1023 struct gve_priv *priv = block->priv; in gve_tx_poll()
1024 struct gve_tx_ring *tx = block->tx; in gve_tx_poll()
1036 spin_lock(&tx->clean_lock); in gve_tx_poll()
1039 to_do = min_t(u32, (nic_done - tx->done), budget); in gve_tx_poll()
1041 spin_unlock(&tx->clean_lock); in gve_tx_poll()
1043 return nic_done != tx->done; in gve_tx_poll()
1050 return nic_done != tx->done; in gve_tx_clean_pending()