Lines Matching +full:extended +full:- +full:range +full:- +full:enable

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) Freescale Semicondutor, Inc. 2006-2009. All rights reserved.
12 * - Rearrange code and style fixes
41 u8 res0[0x100 - sizeof(struct ucc_fast)];
46 u32 hafdup; /* half-duplex reg. */
57 u8 res3[0x180 - 0x15A];
105 u8 res5[0x200 - 0x1c4];
109 #define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics
111 #define TEMODER_SCHEDULER_ENABLE 0x2000 /* enable scheduler */
114 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 /* enable performance
117 #define TEMODER_RMON_STATISTICS 0x0100 /* enable tx statistics
119 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15) /* Number of queues <<
123 #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 /* enable Rx
125 #define REMODER_RX_EXTENDED_FEATURES 0x80000000 /* enable
126 extended
128 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 ) /* vlan operation
130 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
132 #define REMODER_RX_QOS_MODE_SHIFT (31-15) /* rx QoS mode << shift
134 #define REMODER_RMON_STATISTICS 0x00001000 /* enable rx
136 #define REMODER_RX_EXTENDED_FILTERING 0x00000800 /* extended
139 mpc82xx-like
141 #define REMODER_NUM_OF_QUEUES_SHIFT (31-23) /* Number of queues <<
143 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 /* enable
147 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 /* enable
155 4-byte
189 #define ENET_TBI_MII_EXST 0x0F /* Extended status */
223 #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Rx Enable
227 #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
228 #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Tx Enable
232 #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
235 #define MACCFG2_PREL_SHIFT (31 - 19) /* Preamble
245 #define MACCFG2_RESERVED_1 0x00000020 /* Reserved -
275 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
276 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 - 7) /* Non
277 back-to-back
281 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15) /* Non
282 back-to-back
286 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT (31 - 23) /* Mimimum IFG
289 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT (31 - 31) /* back-to-back
293 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX 127 /* Non back-to-back
296 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX 127 /* Non back-to-back
301 #define IPGIFG_BACK_TO_BACK_IFG_MAX 127 /* back-to-back inter
309 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT (31 - 11) /* Alternate
328 #define HALFDUP_MAX_RETRANSMISSION_SHIFT (31 - 19) /* Maximum
334 #define HALFDUP_COLLISION_WINDOW_SHIFT (31 - 31) /* Collision
357 #define MACSTNADDR1_OCTET_6_SHIFT (31 - 7) /* Station
361 #define MACSTNADDR1_OCTET_5_SHIFT (31 - 15) /* Station
365 #define MACSTNADDR1_OCTET_4_SHIFT (31 - 23) /* Station
369 #define MACSTNADDR1_OCTET_3_SHIFT (31 - 31) /* Station
375 #define MACSTNADDR2_OCTET_2_SHIFT (31 - 7) /* Station
379 #define MACSTNADDR2_OCTET_1_SHIFT (31 - 15) /* Station
385 #define UEMPR_PAUSE_TIME_VALUE_SHIFT (31 - 15) /* Pause time
388 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT (31 - 31) /* Extended
394 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) /* Phy address
406 #define UESCR_MAXCOV_SHIFT (15 - 7) /* Max
410 #define UESCR_SCOV_SHIFT (15 - 15) /* Status
426 /* Send Queue Queue-Descriptor */
483 u8 res1[0x70 - 0x64];
511 u32 inrangelenrxer; /* in range length error */
512 u32 outrangelenrxer; /* out of range length error */
568 u8 res0[0x38 - 0x02];
576 u32 vtagtable[0x8]; /* 8 4-byte VLAN tags */
579 u8 res2[0x78 - 0x74];
584 u8 res3[0xa8 - 0x94];
586 u8 res4[0xc0 - 0xac];
589 /* structure representing Extended Filtering Global Parameters in PRAM */
592 u8 res0[0x10 - 0x04];
599 u8 res1[0x20 - 0xC];
605 u8 res3[0x30 - 0x28];
607 u8 res4[0x36 - 0x34];
610 u8 res5[0x46 - 0x37];
624 u32 exfGlobalParam; /* base address for extended filtering global
626 u8 res6[0x100 - 0xC4]; /* Initialize to zero */
642 u8 res2[0x38 - 0x30];
648 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
649 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
678 u8 res0[0x40 - 0x38];
710 u32 inrangelenrxer; /* in range length error */
711 u32 outrangelenrxer; /* out of range length error */
820 #define R_NO 0x00100000 /* Non-octet aligned frame. */
885 #define TX_RING_MOD_MASK(size) (size-1)
886 #define RX_RING_MOD_MASK(size) (size-1)
962 UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */
964 = 0x1, /* Tagged - replace vid portion of q tag */
966 = 0x2, /* Tagged - if vid0 replace vid with default value */
968 = 0x3 /* Tagged - extract q tag from frame */
971 /* UCC GETH vlan operation non-tagged */
973 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */
974 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged -
992 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
998 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
1003 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
1009 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
1017 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */