Lines Matching +full:0 +full:x4010

12 #define NXP_ENETC_VENDOR_ID		0x1131
13 #define NXP_ENETC_PF_DEV_ID		0xe101
16 /* Station interface LSO segmentation flag mask register 0/1 */
17 #define ENETC4_SILSOSFMR0		0x1300
19 #define  SILSOSFMR0_TCP_1ST_SEG		GENMASK(11, 0)
23 #define ENETC4_SILSOSFMR1		0x1304
24 #define  SILSOSFMR1_TCP_LAST_SEG	GENMASK(11, 0)
25 #define   ENETC4_TCP_FLAGS_FIN		BIT(0)
39 #define ENETC4_ECAPR0			0x0
47 #define ENETC4_ECAPR1			0x4
55 #define ENETC4_ECAPR2			0x8
56 #define  ECAPR2_NUM_TX_BDR		GENMASK(9, 0)
59 #define ENETC4_PMR			0x10
63 #define ENETC4_PPAUONTR			0x108
64 #define ENETC4_PPAUOFFTR		0x10c
67 #define ENETC4_PSIPMMR			0x200
72 #define ENETC4_PSIPVMR			0x204
74 /* Port RSS key register n. n = 0,1,2,...,9 */
75 #define ENETC4_PRSSKR(n)		((n) * 0x4 + 0x250)
78 #define ENETC4_PSIMAFCAPR		0x280
79 #define  PSIMAFCAPR_NUM_MAC_AFTE	GENMASK(11, 0)
82 #define ENETC4_PSIVLANFCAPR		0x2c0
83 #define  PSIVLANFCAPR_NUM_VLAN_FTE	GENMASK(11, 0)
86 #define ENETC4_PSIVLANFMR		0x2c4
87 #define  PSIVLANFMR_VS			BIT(0)
90 #define ENETC4_PSIPMAR0(a)		((a) * 0x80 + 0x2000)
91 #define ENETC4_PSIPMAR1(a)		((a) * 0x80 + 0x2004)
93 /* Port station interface a configuration register 0/2 */
94 #define ENETC4_PSICFGR0(a)		((a) * 0x80 + 0x2010)
99 #define ENETC4_PSICFGR2(a)		((a) * 0x80 + 0x2018)
100 #define  PSICFGR2_NUM_MSIX		GENMASK(5, 0)
102 #define ENETC4_PMCAPR			0x4004
107 #define ENETC4_PCR			0x4010
108 #define  PCR_HDR_FMT			BIT(0)
114 /* Port MAC address register 0/1 */
115 #define ENETC4_PMAR0			0x4020
116 #define ENETC4_PMAR1			0x4024
119 #define ENETC4_POR			0x4100
122 #define ENETC4_PTCTMSDUR(a)		((a) * 0x20 + 0x4208)
123 #define  PTCTMSDUR_MAXSDU		GENMASK(15, 0)
125 #define   SDU_TYPE_PPDU			0
129 #define ENETC4_PMAC_OFFSET		0x400
130 #define ENETC4_PM_CMD_CFG(mac)		(0x5008 + (mac) * 0x400)
131 #define  PM_CMD_CFG_TX_EN		BIT(0)
138 #define   LPBCK_MODE_EXT_TX_CLK		0
153 /* Port MAC 0/1 Maximum Frame Length Register */
154 #define ENETC4_PM_MAXFRM(mac)		(0x5014 + (mac) * 0x400)
156 /* Port MAC 0/1 Pause Quanta Register */
157 #define ENETC4_PM_PAUSE_QUANTA(mac)	(0x5054 + (mac) * 0x400)
159 /* Port MAC 0/1 Pause Quanta Threshold Register */
160 #define ENETC4_PM_PAUSE_THRESH(mac)	(0x5064 + (mac) * 0x400)
162 /* Port MAC 0 Interface Mode Control Register */
163 #define ENETC4_PM_IF_MODE(mac)		(0x5300 + (mac) * 0x400)
164 #define  PM_IF_MODE_IFMODE		GENMASK(2, 0)
165 #define   IFMODE_XGMII			0
173 #define   SSP_100M			0