Lines Matching +full:0 +full:x3210
29 #define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
37 #define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
44 #define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
57 #define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000
58 #define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001
59 #define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002
60 #define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003
61 #define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004
62 #define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005
64 #define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006
65 #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE 0x0007
66 #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS 0x0008
67 #define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS 0x0009
68 #define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA 0x000A
69 #define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA 0x000B
71 #define SUNI1x10GEXP_REG_OAM_INTF_CTRL 0x000C
72 #define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D
73 #define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E
74 #define SUNI1x10GEXP_REG_FREE 0x000F
76 #define SUNI1x10GEXP_REG_XTEF_MISC_CTRL 0x0010
77 #define SUNI1x10GEXP_REG_XRF_MISC_CTRL 0x0011
79 #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 0x0100
80 #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 0x0101
81 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102
82 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE 0x0103
83 #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104
84 #define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG 0x0107
86 #define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040
87 #define SUNI1x10GEXP_REG_RXXG_CONFIG_2 0x2041
88 #define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042
89 #define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043
90 #define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045
91 #define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046
92 #define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047
93 #define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048
94 #define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD 0x2049
95 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OF…
96 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OF…
97 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OF…
98 #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTE…
99 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW 0x204A
100 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID 0x204B
101 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH 0x204C
102 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D
103 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E
104 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F
105 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW 0x2050
106 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID 0x2051
107 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH 0x2052
108 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW 0x2053
109 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID 0x2054
110 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH 0x2055
111 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW 0x2056
112 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID 0x2057
113 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH 0x2058
114 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW 0x2059
115 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID 0x205A
116 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH 0x205B
117 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW 0x205C
118 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID 0x205D
119 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH 0x205E
120 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW 0x205F
121 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID 0x2060
122 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH 0x2061
123 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 0x2062
124 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 0x2063
125 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 0x2064
126 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 0x2065
127 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 0x2066
128 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 0x2067
129 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 0x2068
130 #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 0x2069
131 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A
132 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B
133 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C
134 #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D
135 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E
136 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 0x206F
137 #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070
139 #define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL 0x2081
140 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 0x2084
141 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 0x2085
142 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 0x2086
143 #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 0x2087
144 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088
145 #define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089
146 #define SUNI1x10GEXP_REG_XRF_ERR_STATUS 0x208A
147 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B
148 #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C
149 #define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES 0x2092
151 #define SUNI1x10GEXP_REG_RXOAM_CONFIG 0x20C0
152 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG 0x20C1
153 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG 0x20C2
154 #define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 0x20C3
155 #define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG 0x20C4
156 #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES 0x20C5
157 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7
158 #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8
159 #define SUNI1x10GEXP_REG_RXOAM_STATUS 0x20C9
160 #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT 0x20CA
161 #define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT 0x20CB
162 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB 0x20CC
163 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB 0x20CD
164 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB 0x20CE
165 #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB 0x20CF
166 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB 0x20D0
167 #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB 0x20D1
168 #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB 0x20D2
169 #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB 0x20D3
170 #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB 0x20D4
171 #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB 0x20D5
172 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB 0x20D6
173 #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB 0x20D7
175 #define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100
176 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101
177 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102
178 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 0x2103
179 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 0x2104
180 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 0x2105
181 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106
182 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107
183 #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108
184 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS 0x2109
185 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW 0x210A
186 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE 0x210B
187 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH 0x210C
188 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(c…
189 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(c…
190 #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(c…
191 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110
192 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID 0x2111
193 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH 0x2112
194 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD 0x2113
195 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114
196 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID 0x2115
197 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH 0x2116
198 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD 0x2117
199 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW 0x2118
200 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID 0x2119
201 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH 0x211A
202 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD 0x211B
203 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW 0x211C
204 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID 0x211D
205 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH 0x211E
206 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD 0x211F
207 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120
208 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID 0x2121
209 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH 0x2122
210 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD 0x2123
211 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124
212 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID 0x2125
213 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH 0x2126
214 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD 0x2127
215 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128
216 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID 0x2129
217 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH 0x212A
218 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD 0x212B
219 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW 0x212C
220 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID 0x212D
221 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH 0x212E
222 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD 0x212F
223 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130
224 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID 0x2131
225 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH 0x2132
226 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD 0x2133
227 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW 0x2134
228 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID 0x2135
229 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH 0x2136
230 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD 0x2137
231 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138
232 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID 0x2139
233 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH 0x213A
234 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD 0x213B
235 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C
236 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID 0x213D
237 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH 0x213E
238 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD 0x213F
239 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140
240 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID 0x2141
241 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH 0x2142
242 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD 0x2143
243 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144
244 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID 0x2145
245 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH 0x2146
246 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD 0x2147
247 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW 0x2148
248 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID 0x2149
249 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH 0x214A
250 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD 0x214B
251 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C
252 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID 0x214D
253 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH 0x214E
254 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD 0x214F
255 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150
256 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID 0x2151
257 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH 0x2152
258 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD 0x2153
259 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154
260 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID 0x2155
261 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH 0x2156
262 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD 0x2157
263 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158
264 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID 0x2159
265 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH 0x215A
266 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD 0x215B
267 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW 0x215C
268 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID 0x215D
269 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH 0x215E
270 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD 0x215F
271 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW 0x2160
272 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID 0x2161
273 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH 0x2162
274 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD 0x2163
275 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW 0x2164
276 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID 0x2165
277 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH 0x2166
278 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD 0x2167
279 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW 0x2168
280 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID 0x2169
281 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH 0x216A
282 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD 0x216B
283 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW 0x216C
284 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID 0x216D
285 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH 0x216E
286 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD 0x216F
287 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW 0x2170
288 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID 0x2171
289 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH 0x2172
290 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD 0x2173
291 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW 0x2174
292 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID 0x2175
293 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH 0x2176
294 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD 0x2177
295 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW 0x2178
296 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID 0x2179
297 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH 0x217a
298 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD 0x217b
299 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW 0x217c
300 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID 0x217d
301 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH 0x217e
302 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD 0x217f
303 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW 0x2180
304 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID 0x2181
305 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH 0x2182
306 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD 0x2183
307 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW 0x2184
308 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID 0x2185
309 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH 0x2186
310 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD 0x2187
311 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW 0x2188
312 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID 0x2189
313 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH 0x218A
314 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD 0x218B
315 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW 0x218C
316 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID 0x218D
317 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH 0x218E
318 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD 0x218F
319 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW 0x2190
320 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID 0x2191
321 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH 0x2192
322 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD 0x2193
323 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194
324 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID 0x2195
325 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH 0x2196
326 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD 0x2197
327 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW 0x2198
328 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID 0x2199
329 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH 0x219A
330 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD 0x219B
331 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C
332 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID 0x219D
333 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH 0x219E
334 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD 0x219F
335 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0
336 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID 0x21A1
337 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH 0x21A2
338 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD 0x21A3
339 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW 0x21A4
340 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID 0x21A5
341 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH 0x21A6
342 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD 0x21A7
343 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8
344 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID 0x21A9
345 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH 0x21AA
346 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD 0x21AB
347 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW 0x21AC
348 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID 0x21AD
349 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH 0x21AE
350 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD 0x21AF
351 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0
352 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID 0x21B1
353 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH 0x21B2
354 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD 0x21B3
355 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW 0x21B4
356 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID 0x21B5
357 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH 0x21B6
358 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD 0x21B7
359 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8
360 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID 0x21B9
361 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH 0x21BA
362 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD 0x21BB
363 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC
364 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID 0x21BD
365 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH 0x21BE
366 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD 0x21BF
367 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW 0x21C0
368 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID 0x21C1
369 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH 0x21C2
370 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD 0x21C3
371 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW 0x21C4
372 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID 0x21C5
373 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH 0x21C6
374 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD 0x21C7
375 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW 0x21C8
376 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID 0x21C9
377 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH 0x21CA
378 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD 0x21CB
379 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW 0x21CC
380 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID 0x21CD
381 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH 0x21CE
382 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD 0x21CF
383 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW 0x21D0
384 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID 0x21D1
385 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH 0x21D2
386 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD 0x21D3
387 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW 0x21D4
388 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID 0x21D5
389 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH 0x21D6
390 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD 0x21D7
391 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW 0x21D8
392 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID 0x21D9
393 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH 0x21DA
394 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD 0x21DB
395 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW 0x21DC
396 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID 0x21DD
397 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH 0x21DE
398 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD 0x21DF
399 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW 0x21E0
400 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID 0x21E1
401 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH 0x21E2
402 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD 0x21E3
403 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW 0x21E4
404 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID 0x21E5
405 #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH 0x21E6
408 #define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG 0x2200
409 #define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION 0x2201
410 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209
411 #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A
412 #define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS 0x220D
413 #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION 0x220E
414 #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT 0x220F
415 #define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT 0x2210
416 #define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT 0x2211
418 #define SUNI1x10GEXP_REG_PL4MOS_CONFIG 0x2240
419 #define SUNI1x10GEXP_REG_PL4MOS_MASK 0x2241
420 #define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING 0x2242
421 #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 0x2243
422 #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 0x2244
423 #define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE 0x2245
425 #define SUNI1x10GEXP_REG_PL4ODP_CONFIG 0x2280
426 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282
427 #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283
428 #define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T 0x2284
430 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300
431 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301
432 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302
433 #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS 0x2303
434 #define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS 0x2304
435 #define SUNI1x10GEXP_REG_PL4IO_CONFIG 0x2305
437 #define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040
438 #define SUNI1x10GEXP_REG_TXXG_CONFIG_2 0x3041
439 #define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042
440 #define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043
441 #define SUNI1x10GEXP_REG_TXXG_STATUS 0x3044
442 #define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045
443 #define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE 0x3046
444 #define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047
445 #define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048
446 #define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049
447 #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER 0x304D
448 #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL 0x304E
449 #define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER 0x3051
450 #define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG 0x3052
452 #define SUNI1x10GEXP_REG_XTEF_CTRL 0x3080
453 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084
454 #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085
455 #define SUNI1x10GEXP_REG_XTEF_VISIBILITY 0x3086
457 #define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG 0x30C0
458 #define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG 0x30C1
459 #define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG 0x30C2
460 #define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES 0x30C3
461 #define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES 0x30C4
462 #define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES 0x30C5
463 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6
464 #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7
465 #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB 0x30C8
466 #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB 0x30C9
467 #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB 0x30CA
468 #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB 0x30CB
469 #define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK 0x30CC
470 #define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK 0x30CD
471 #define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK 0x30CE
472 #define SUNI1x10GEXP_REG_TXOAM_COSET 0x30CF
473 #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB 0x30D0
474 #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB 0x30D1
475 #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB 0x30D2
476 #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB 0x30D3
479 #define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG 0x3200
480 #define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS 0x3201
481 #define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS 0x3202
482 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT 0x3203
483 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT 0x3204
484 #define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT 0x3205
485 #define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT 0x3206
486 #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD 0x3207
487 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C
488 #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D
489 #define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION 0x3210
491 #define SUNI1x10GEXP_REG_PL4IDU_CONFIG 0x3280
492 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282
493 #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283
497 #define SUNI1x10GEXP_REG_MAX_OFFSET 0x3480
507 #define SUNI1x10GEXP_BITMSK_BITS_1 0x00001
508 #define SUNI1x10GEXP_BITMSK_BITS_2 0x00003
509 #define SUNI1x10GEXP_BITMSK_BITS_3 0x00007
510 #define SUNI1x10GEXP_BITMSK_BITS_4 0x0000f
511 #define SUNI1x10GEXP_BITMSK_BITS_5 0x0001f
512 #define SUNI1x10GEXP_BITMSK_BITS_6 0x0003f
513 #define SUNI1x10GEXP_BITMSK_BITS_7 0x0007f
514 #define SUNI1x10GEXP_BITMSK_BITS_8 0x000ff
515 #define SUNI1x10GEXP_BITMSK_BITS_9 0x001ff
516 #define SUNI1x10GEXP_BITMSK_BITS_10 0x003ff
517 #define SUNI1x10GEXP_BITMSK_BITS_11 0x007ff
518 #define SUNI1x10GEXP_BITMSK_BITS_12 0x00fff
519 #define SUNI1x10GEXP_BITMSK_BITS_13 0x01fff
520 #define SUNI1x10GEXP_BITMSK_BITS_14 0x03fff
521 #define SUNI1x10GEXP_BITMSK_BITS_15 0x07fff
522 #define SUNI1x10GEXP_BITMSK_BITS_16 0x0ffff
540 #define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0)
545 * Register 0x0001: S/UNI-1x10GE-XP Product Revision
546 * Bit 3-0 REVISION
548 #define SUNI1x10GEXP_BITMSK_REVISION 0x000F
551 * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control
554 * Bit 0 DRESETB
556 #define SUNI1x10GEXP_BITMSK_XAUI_ARESET 0x0004
557 #define SUNI1x10GEXP_BITMSK_PL4_ARESET 0x0002
558 #define SUNI1x10GEXP_BITMSK_DRESETB 0x0001
561 * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control
570 * Bit 0 OVERRIDE_LOS
572 #define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL 0x0800
573 #define SUNI1x10GEXP_BITMSK_SYSPCSLB 0x0200
574 #define SUNI1x10GEXP_BITMSK_LINEPCSLB 0x0100
575 #define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS 0x0080
576 #define SUNI1x10GEXP_BITMSK_RXXG_BYPASS 0x0040
577 #define SUNI1x10GEXP_BITMSK_TXXG_BYPASS 0x0020
578 #define SUNI1x10GEXP_BITMSK_SOP_PAD_EN 0x0010
579 #define SUNI1x10GEXP_BITMSK_LOS_INV 0x0002
580 #define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS 0x0001
583 * Register 0x0004: S/UNI-1x10GE-XP Device Status
593 * Bit 0 TOP_PL4_OUT_ROOL
595 #define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200
596 #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY 0x0100
597 #define SUNI1x10GEXP_BITMSK_TOP_DTRB 0x0080
598 #define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040
599 #define SUNI1x10GEXP_BITMSK_TOP_PAUSED 0x0020
600 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010
601 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008
602 #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004
603 #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL 0x0002
604 #define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001
607 * Register 0x0005: Global Performance Update and Clock Monitors
617 * Bit 0 RDCLKA
619 #define SUNI1x10GEXP_BITMSK_TIP 0x8000
620 #define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA 0x0100
621 #define SUNI1x10GEXP_BITMSK_RXLANE3CLKA 0x0080
622 #define SUNI1x10GEXP_BITMSK_RXLANE2CLKA 0x0040
623 #define SUNI1x10GEXP_BITMSK_RXLANE1CLKA 0x0020
624 #define SUNI1x10GEXP_BITMSK_RXLANE0CLKA 0x0010
625 #define SUNI1x10GEXP_BITMSK_CSUCLKA 0x0008
626 #define SUNI1x10GEXP_BITMSK_TDCLKA 0x0004
627 #define SUNI1x10GEXP_BITMSK_RSCLKA 0x0002
628 #define SUNI1x10GEXP_BITMSK_RDCLKA 0x0001
631 * Register 0x0006: MDIO Command
636 * Bit 0 MDIO_SPRE
638 #define SUNI1x10GEXP_BITMSK_MDIO_RDINC 0x0010
639 #define SUNI1x10GEXP_BITMSK_MDIO_RSTAT 0x0008
640 #define SUNI1x10GEXP_BITMSK_MDIO_LCTLD 0x0004
641 #define SUNI1x10GEXP_BITMSK_MDIO_LCTLA 0x0002
642 #define SUNI1x10GEXP_BITMSK_MDIO_SPRE 0x0001
645 * Register 0x0007: MDIO Interrupt Enable
646 * Bit 0 MDIO_BUSY_EN
648 #define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN 0x0001
651 * Register 0x0008: MDIO Interrupt Status
652 * Bit 0 MDIO_BUSYI
654 #define SUNI1x10GEXP_BITMSK_MDIO_BUSYI 0x0001
657 * Register 0x0009: MMD PHY Address
659 * Bit 4-0 MDIO_PRTADR
661 #define SUNI1x10GEXP_BITMSK_MDIO_DEVADR 0x1F00
663 #define SUNI1x10GEXP_BITMSK_MDIO_PRTADR 0x001F
664 #define SUNI1x10GEXP_BITOFF_MDIO_PRTADR 0
667 * Register 0x000C: OAM Interface Control
674 * Bit 0 TXOAMCLKEN
676 #define SUNI1x10GEXP_BITMSK_MDO_OD_ENB 0x0040
677 #define SUNI1x10GEXP_BITMSK_MDI_INV 0x0020
678 #define SUNI1x10GEXP_BITMSK_MDI_SEL 0x0010
679 #define SUNI1x10GEXP_BITMSK_RXOAMEN 0x0008
680 #define SUNI1x10GEXP_BITMSK_RXOAMCLKEN 0x0004
681 #define SUNI1x10GEXP_BITMSK_TXOAMEN 0x0002
682 #define SUNI1x10GEXP_BITMSK_TXOAMCLKEN 0x0001
685 * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status
701 * Bit 0 TOP_PL4IDU_INT
703 #define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT 0x8000
704 #define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT 0x4000
705 #define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT 0x2000
706 #define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT 0x1000
707 #define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT 0x0800
708 #define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT 0x0400
709 #define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT 0x0200
710 #define SUNI1x10GEXP_BITMSK_TOP_XRF_INT 0x0100
711 #define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT 0x0080
712 #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT 0x0040
713 #define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT 0x0020
714 #define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT 0x0010
715 #define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT 0x0008
716 #define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT 0x0004
717 #define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT 0x0002
718 #define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT 0x0001
721 * Register 0x000E:PM3393 Global interrupt enable
724 #define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000
727 * Register 0x0010: XTEF Miscellaneous Control
733 #define SUNI1x10GEXP_BITMSK_RF_VAL 0x0080
734 #define SUNI1x10GEXP_BITMSK_RF_OVERRIDE 0x0040
735 #define SUNI1x10GEXP_BITMSK_LF_VAL 0x0020
736 #define SUNI1x10GEXP_BITMSK_LF_OVERRIDE 0x0010
737 #define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL 0x00F0
740 * Register 0x0011: XRF Miscellaneous Control
743 #define SUNI1x10GEXP_BITMSK_EN_IDLE_REP 0x0070
746 * Register 0x0100: SERDES 3125 Configuration Register 1
752 #define SUNI1x10GEXP_BITMSK_RXEQB 0x0FF0
759 * Register 0x0101: SERDES 3125 Configuration Register 2
766 #define SUNI1x10GEXP_BITMSK_YSEL 0x1000
767 #define SUNI1x10GEXP_BITMSK_PRE_EMPH 0x00F0
768 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_3 0x0080
769 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_2 0x0040
770 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_1 0x0020
771 #define SUNI1x10GEXP_BITMSK_PRE_EMPH_0 0x0010
774 * Register 0x0102: SERDES 3125 Interrupt Enable Register
778 * Bit 0 PLL_LOCKE
780 #define SUNI1x10GEXP_BITMSK_LASIE 0x0008
781 #define SUNI1x10GEXP_BITMSK_SPLL_RAE 0x0004
782 #define SUNI1x10GEXP_BITMSK_MPLL_RAE 0x0002
783 #define SUNI1x10GEXP_BITMSK_PLL_LOCKE 0x0001
786 * Register 0x0103: SERDES 3125 Interrupt Visibility Register
790 * Bit 0 PLL_LOCKV
792 #define SUNI1x10GEXP_BITMSK_LASIV 0x0008
793 #define SUNI1x10GEXP_BITMSK_SPLL_RAV 0x0004
794 #define SUNI1x10GEXP_BITMSK_MPLL_RAV 0x0002
795 #define SUNI1x10GEXP_BITMSK_PLL_LOCKV 0x0001
798 * Register 0x0104: SERDES 3125 Interrupt Status Register
802 * Bit 0 PLL_LOCKI
804 #define SUNI1x10GEXP_BITMSK_LASII 0x0008
805 #define SUNI1x10GEXP_BITMSK_SPLL_RAI 0x0004
806 #define SUNI1x10GEXP_BITMSK_MPLL_RAI 0x0002
807 #define SUNI1x10GEXP_BITMSK_PLL_LOCKI 0x0001
810 * Register 0x0107: SERDES 3125 Test Configuration
815 #define SUNI1x10GEXP_BITMSK_DUALTX 0x1000
816 #define SUNI1x10GEXP_BITMSK_HC 0x0600
820 * Register 0x2040: RXXG Configuration 1
830 * Bit 2-0 RXXG_MIFG
832 #define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000
833 #define SUNI1x10GEXP_BITMSK_RXXG_ROCF 0x4000
834 #define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP 0x2000
835 #define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400
836 #define SUNI1x10GEXP_BITMSK_RXXG_LONGP 0x0200
837 #define SUNI1x10GEXP_BITMSK_RXXG_PARF 0x0100
838 #define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080
839 #define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL 0x0020
840 #define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008
843 * Register 0x02041: RXXG Configuration 2
844 * Bit 7-0 RXXG_HDRSIZE
846 #define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE 0x00FF
849 * Register 0x2042: RXXG Configuration 3
858 #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE 0x8000
859 #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE 0x4000
860 #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE 0x1000
861 #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE 0x0400
862 #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE 0x0200
863 #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE 0x0100
864 #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020
867 * Register 0x2043: RXXG Interrupt
876 #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI 0x8000
877 #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI 0x4000
878 #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI 0x1000
879 #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI 0x0400
880 #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI 0x0200
881 #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI 0x0100
882 #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020
885 * Register 0x2049: RXXG Receive FIFO Threshold
886 * Bit 2-0 RXXG_CUT_THRU
888 #define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU 0x0007
889 #define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU 0
892 * Register 0x2062H - 0x2069: RXXG Exact Match VID
893 * Bit 11-0 RXXG_VID_MATCH
895 #define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH 0x0FFF
896 #define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH 0
899 * Register 0x206EH - 0x206F: RXXG Address Filter Control
903 * Bit 0 RXXG_MATCH_ENABLE
905 #define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE 0x0008
906 #define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE 0x0004
907 #define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR 0x0002
908 #define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE 0x0001
911 * Register 0x2070: RXXG Address Filter Control 2
913 * Bit 0 RXXG_MHASH_EN
915 #define SUNI1x10GEXP_BITMSK_RXXG_PMODE 0x0002
916 #define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001
919 * Register 0x2081: XRF Control Register 2
923 #define SUNI1x10GEXP_BITMSK_EN_PKT_GEN 0x0040
924 #define SUNI1x10GEXP_BITMSK_PATT 0x001C
928 * Register 0x2088: XRF Interrupt Enable
932 * Bit 3-0 LANE_SYNC_STAT_ERRE
934 #define SUNI1x10GEXP_BITMSK_LANE_HICERE 0x1E00
936 #define SUNI1x10GEXP_BITMSK_HS_SD_LANEE 0x01E0
938 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE 0x0010
939 #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE 0x000F
940 #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE 0
943 * Register 0x2089: XRF Interrupt Status
947 * Bit 3-0 LANE_SYNC_STAT_ERRI
949 #define SUNI1x10GEXP_BITMSK_LANE_HICERI 0x1E00
951 #define SUNI1x10GEXP_BITMSK_HS_SD_LANEI 0x01E0
953 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI 0x0010
954 #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI 0x000F
955 #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI 0
958 * Register 0x208A: XRF Error Status
961 * Bit 3-0 LANE_SYNC_STAT_ERR
963 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE3 0x0100
964 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE2 0x0080
965 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE1 0x0040
966 #define SUNI1x10GEXP_BITMSK_HS_SD_LANE0 0x0020
967 #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR 0x0010
968 #define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR 0x0008
969 #define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR 0x0004
970 #define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR 0x0002
971 #define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR 0x0001
974 * Register 0x208B: XRF Diagnostic Interrupt Enable
976 * Bit 3-0 LANE_UNDERRUNE
978 #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE 0x00F0
980 #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE 0x000F
981 #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE 0
984 * Register 0x208C: XRF Diagnostic Interrupt Status
986 * Bit 3-0 LANE_UNDERRUNI
988 #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI 0x00F0
990 #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI 0x000F
991 #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI 0
994 * Register 0x20C0: RXOAM Configuration
999 * Bit 5-0 RXOAM_PX_EN
1001 #define SUNI1x10GEXP_BITMSK_RXOAM_BUSY 0x8000
1002 #define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL 0x7000
1004 #define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL 0x0700
1006 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL 0x00C0
1008 #define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN 0x003F
1009 #define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN 0
1012 * Register 0x20C1,0x20C2: RXOAM Filter Configuration
1014 * Bit 7-0 RXOAM_FX_VAL
1016 #define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK 0xFF00
1018 #define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL 0x00FF
1019 #define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl 0
1022 * Register 0x20C3: RXOAM Configuration Register 2
1025 * Bit 5-0 RXOAM_PX_CLEAR
1027 #define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL 0x2000
1028 #define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE 0x0C00
1030 #define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR 0x003F
1031 #define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR 0
1034 * Register 0x20C4: RXOAM HEC Configuration
1037 * Bit 0 RXOAM_HEC_EN
1039 #define SUNI1x10GEXP_BITMSK_RXOAM_COSET 0xFF00
1041 #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT 0x0004
1042 #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN 0x0001
1045 * Register 0x20C7: RXOAM Interrupt Enable
1056 * Bit 0 RXOAM_OFLE
1058 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE 0x0400
1059 #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE 0x0200
1060 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE 0x0100
1061 #define SUNI1x10GEXP_BITMSK_RXOAM_SOPE 0x0080
1062 #define SUNI1x10GEXP_BITMSK_RXOAM_RFE 0x0040
1063 #define SUNI1x10GEXP_BITMSK_RXOAM_LFE 0x0020
1064 #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE 0x0010
1065 #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE 0x0008
1066 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE 0x0004
1067 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE 0x0002
1068 #define SUNI1x10GEXP_BITMSK_RXOAM_OFLE 0x0001
1071 * Register 0x20C8: RXOAM Interrupt Status
1082 * Bit 0 RXOAM_OFLI
1084 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI 0x0400
1085 #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI 0x0200
1086 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI 0x0100
1087 #define SUNI1x10GEXP_BITMSK_RXOAM_SOPI 0x0080
1088 #define SUNI1x10GEXP_BITMSK_RXOAM_RFI 0x0040
1089 #define SUNI1x10GEXP_BITMSK_RXOAM_LFI 0x0020
1090 #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI 0x0010
1091 #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI 0x0008
1092 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI 0x0004
1093 #define SUNI1x10GEXP_BITMSK_RXOAM_HECI 0x0002
1094 #define SUNI1x10GEXP_BITMSK_RXOAM_OFLI 0x0001
1097 * Register 0x20C9: RXOAM Status
1103 #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV 0x0400
1104 #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV 0x0100
1105 #define SUNI1x10GEXP_BITMSK_RXOAM_RFV 0x0040
1106 #define SUNI1x10GEXP_BITMSK_RXOAM_LFV 0x0020
1109 * Register 0x2100: MSTAT Control
1112 * Bit 0 MSTAT_SNAP
1114 #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE 0x0004
1115 #define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002
1116 #define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001
1119 * Register 0x2109: MSTAT Counter Write Address
1120 * Bit 5-0 MSTAT_WRITE_ADDRESS
1122 #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F
1123 #define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0
1126 * Register 0x2200: IFLX Global Configuration Register
1129 * Bit 13-0 IFLX_IFD_CNT
1131 #define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE 0x8000
1132 #define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE 0x4000
1133 #define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT 0x3FFF
1134 #define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT 0
1137 * Register 0x2209: IFLX FIFO Overflow Enable
1138 * Bit 0 IFLX_OVFE
1140 #define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001
1143 * Register 0x220A: IFLX FIFO Overflow Interrupt
1144 * Bit 0 IFLX_OVFI
1146 #define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001
1149 * Register 0x220D: IFLX Indirect Channel Address
1153 #define SUNI1x10GEXP_BITMSK_IFLX_BUSY 0x8000
1154 #define SUNI1x10GEXP_BITMSK_IFLX_RWB 0x4000
1157 * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision
1158 * Bit 9-0 IFLX_LOLIM
1160 #define SUNI1x10GEXP_BITMSK_IFLX_LOLIM 0x03FF
1161 #define SUNI1x10GEXP_BITOFF_IFLX_LOLIM 0
1164 * Register 0x220F: IFLX Indirect Logical FIFO High Limit
1165 * Bit 9-0 IFLX_HILIM
1167 #define SUNI1x10GEXP_BITMSK_IFLX_HILIM 0x03FF
1168 #define SUNI1x10GEXP_BITOFF_IFLX_HILIM 0
1171 * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit
1174 * Bit 13-0 IFLX_AFTH
1176 #define SUNI1x10GEXP_BITMSK_IFLX_FULL 0x8000
1177 #define SUNI1x10GEXP_BITMSK_IFLX_AFULL 0x4000
1178 #define SUNI1x10GEXP_BITMSK_IFLX_AFTH 0x3FFF
1179 #define SUNI1x10GEXP_BITOFF_IFLX_AFTH 0
1182 * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit
1185 * Bit 13-0 IFLX_AETH
1187 #define SUNI1x10GEXP_BITMSK_IFLX_EMPTY 0x8000
1188 #define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY 0x4000
1189 #define SUNI1x10GEXP_BITMSK_IFLX_AETH 0x3FFF
1190 #define SUNI1x10GEXP_BITOFF_IFLX_AETH 0
1193 * Register 0x2240: PL4MOS Configuration Register
1198 #define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT 0x0008
1199 #define SUNI1x10GEXP_BITMSK_PL4MOS_EN 0x0004
1200 #define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS 0x0002
1203 * Register 0x2243: PL4MOS MaxBurst1 Register
1204 * Bit 11-0 PL4MOS_MAX_BURST1
1206 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1 0x0FFF
1207 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 0
1210 * Register 0x2244: PL4MOS MaxBurst2 Register
1211 * Bit 11-0 PL4MOS_MAX_BURST2
1213 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2 0x0FFF
1214 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 0
1217 * Register 0x2245: PL4MOS Transfer Size Register
1218 * Bit 7-0 PL4MOS_MAX_TRANSFER
1220 #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER 0x00FF
1221 #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER 0
1224 * Register 0x2280: PL4ODP Configuration
1228 * Bit 0 PL4ODP_EN_DFWD
1230 #define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T 0xF000
1232 #define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE 0x0100
1233 #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS 0x0002
1234 #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD 0x0001
1237 * Register 0x2282: PL4ODP Interrupt Mask
1238 * Bit 0 PL4ODP_OUT_DISE
1240 #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE 0x0001
1244 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE 0x0080
1245 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE 0x0040
1246 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE 0x0008
1247 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE 0x0004
1248 #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE 0x0002
1252 * Register 0x2283: PL4ODP Interrupt
1253 * Bit 0 PL4ODP_OUT_DISI
1255 #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI 0x0001
1259 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI 0x0080
1260 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI 0x0040
1261 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI 0x0008
1262 #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI 0x0004
1263 #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI 0x0002
1266 * Register 0x2300: PL4IO Lock Detect Status
1272 * Bit 0 PL4IO_ID_DOOLV
1274 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV 0x8000
1275 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV 0x1000
1276 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV 0x0800
1277 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV 0x0100
1278 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV 0x0010
1279 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV 0x0001
1282 * Register 0x2301: PL4IO Lock Detect Change
1288 * Bit 0 PL4IO_ID_DOOLI
1290 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI 0x8000
1291 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI 0x1000
1292 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI 0x0800
1293 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI 0x0100
1294 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI 0x0010
1295 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI 0x0001
1298 * Register 0x2302: PL4IO Lock Detect Mask
1304 * Bit 0 PL4IO_ID_DOOLE
1306 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE 0x8000
1307 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE 0x1000
1308 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE 0x0800
1309 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE 0x0100
1310 #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE 0x0010
1311 #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE 0x0001
1314 * Register 0x2303: PL4IO Lock Detect Limits
1316 * Bit 7-0 PL4IO_TRAN_LIMIT
1318 #define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT 0xFF00
1320 #define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT 0x00FF
1321 #define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT 0
1324 * Register 0x2304: PL4IO Calendar Repetitions
1326 * Bit 7-0 PL4IO_OUT_MUL
1328 #define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL 0xFF00
1330 #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL 0x00FF
1331 #define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL 0
1334 * Register 0x2305: PL4IO Configuration
1344 * Bit 1-0 PL4IO_OUTSEL
1346 #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK 0x8000
1347 #define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS 0x0800
1348 #define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS 0x0400
1349 #define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS 0x0200
1350 #define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS 0x0100
1351 #define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT 0x0080
1352 #define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL 0x0040
1353 #define SUNI1x10GEXP_BITMSK_PL4IO_INSEL 0x0020
1354 #define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL 0x0010
1355 #define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL 0x0003
1356 #define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL 0
1359 * Register 0x3040: TXXG Configuration Register 1
1368 * Bit 0 TXXG_SPRE
1370 #define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000
1371 #define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE 0x2000
1372 #define SUNI1x10GEXP_BITMSK_TXXG_IPGT 0x1F80
1374 #define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020
1375 #define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010
1376 #define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008
1377 #define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004
1378 #define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002
1379 #define SUNI1x10GEXP_BITMSK_TXXG_SPRE 0x0001
1382 * Register 0x3041: TXXG Configuration Register 2
1383 * Bit 7-0 TXXG_HDRSIZE
1385 #define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE 0x00FF
1388 * Register 0x3042: TXXG Configuration Register 3
1395 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE 0x8000
1396 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE 0x4000
1397 #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE 0x2000
1398 #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE 0x1000
1399 #define SUNI1x10GEXP_BITMSK_TXXG_XFERE 0x0800
1402 * Register 0x3043: TXXG Interrupt
1409 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI 0x8000
1410 #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI 0x4000
1411 #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI 0x2000
1412 #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI 0x1000
1413 #define SUNI1x10GEXP_BITMSK_TXXG_XFERI 0x0800
1416 * Register 0x3044: TXXG Status Register
1418 * Bit 0 TXXG_PAUSED
1420 #define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE 0x0002
1421 #define SUNI1x10GEXP_BITMSK_TXXG_PAUSED 0x0001
1424 * Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register
1425 * Bit 7-0 TXXG_TX_MINFR
1427 #define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR 0x00FF
1428 #define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR 0
1431 * Register 0x3052: TXXG Pause Quantum Value Configuration Register
1432 * Bit 7-0 TXXG_FC_PAUSE_QNTM
1434 #define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM 0x00FF
1435 #define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM 0
1438 * Register 0x3080: XTEF Control
1439 * Bit 3-0 XTEF_FORCE_PARITY_ERR
1441 #define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR 0x000F
1442 #define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR 0
1445 * Register 0x3084: XTEF Interrupt Event Register
1446 * Bit 0 XTEF_LOST_SYNCI
1448 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI 0x0001
1451 * Register 0x3085: XTEF Interrupt Enable Register
1452 * Bit 0 XTEF_LOST_SYNCE
1454 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE 0x0001
1457 * Register 0x3086: XTEF Visibility Register
1458 * Bit 0 XTEF_LOST_SYNCV
1460 #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV 0x0001
1463 * Register 0x30C0: TXOAM OAM Configuration
1469 * Bit 5-0 TXOAM_PX_SEL
1471 #define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN 0x8000
1472 #define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN 0x4000
1473 #define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE 0x2000
1474 #define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE 0x1000
1475 #define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE 0x0FC0
1477 #define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL 0x003F
1478 #define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL 0
1481 * Register 0x30C1: TXOAM Mini-Packet Rate Configuration
1485 * Bit 10-0 TXOAM_MINIRATE
1487 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS 0x8000
1488 #define SUNI1x10GEXP_BITMSK_TXOAM_BUSY 0x4000
1489 #define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN 0x2000
1490 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE 0x07FF
1493 * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration
1496 * Bit 5-0 TXOAM_MINIPRE
1498 #define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH 0x3C00
1500 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST 0x03C0
1502 #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE 0x003F
1505 * Register 0x30C6: TXOAM Interrupt Enable
1508 * Bit 0 TXOAM_ERRE
1510 #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE 0x0004
1511 #define SUNI1x10GEXP_BITMSK_TXOAM_OFLE 0x0002
1512 #define SUNI1x10GEXP_BITMSK_TXOAM_ERRE 0x0001
1515 * Register 0x30C7: TXOAM Interrupt Status
1518 * Bit 0 TXOAM_ERRI
1520 #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI 0x0004
1521 #define SUNI1x10GEXP_BITMSK_TXOAM_OFLI 0x0002
1522 #define SUNI1x10GEXP_BITMSK_TXOAM_ERRI 0x0001
1525 * Register 0x30CF: TXOAM Coset
1526 * Bit 7-0 TXOAM_COSET
1528 #define SUNI1x10GEXP_BITMSK_TXOAM_COSET 0x00FF
1531 * Register 0x3200: EFLX Global Configuration
1535 #define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN 0x8000
1536 #define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT 0x0080
1539 * Register 0x3201: EFLX ERCU Global Status
1542 #define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR 0x2000
1545 * Register 0x3202: EFLX Indirect Channel Address
1549 #define SUNI1x10GEXP_BITMSK_EFLX_BUSY 0x8000
1550 #define SUNI1x10GEXP_BITMSK_EFLX_RDWRB 0x4000
1553 * Register 0x3203: EFLX Indirect Logical FIFO Low Limit
1555 #define SUNI1x10GEXP_BITMSK_EFLX_LOLIM 0x03FF
1556 #define SUNI1x10GEXP_BITOFF_EFLX_LOLIM 0
1559 * Register 0x3204: EFLX Indirect Logical FIFO High Limit
1561 #define SUNI1x10GEXP_BITMSK_EFLX_HILIM 0x03FF
1562 #define SUNI1x10GEXP_BITOFF_EFLX_HILIM 0
1565 * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit
1568 * Bit 13-0 EFLX_AFTH
1570 #define SUNI1x10GEXP_BITMSK_EFLX_FULL 0x8000
1571 #define SUNI1x10GEXP_BITMSK_EFLX_AFULL 0x4000
1572 #define SUNI1x10GEXP_BITMSK_EFLX_AFTH 0x3FFF
1573 #define SUNI1x10GEXP_BITOFF_EFLX_AFTH 0
1576 * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit
1579 * Bit 13-0 EFLX_AETH
1581 #define SUNI1x10GEXP_BITMSK_EFLX_EMPTY 0x8000
1582 #define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY 0x4000
1583 #define SUNI1x10GEXP_BITMSK_EFLX_AETH 0x3FFF
1584 #define SUNI1x10GEXP_BITOFF_EFLX_AETH 0
1587 * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold
1589 #define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU 0x3FFF
1590 #define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU 0
1593 * Register 0x320C: EFLX FIFO Overflow Error Enable
1594 * Bit 0 EFLX_OVFE
1596 #define SUNI1x10GEXP_BITMSK_EFLX_OVFE 0x0001
1599 * Register 0x320D: EFLX FIFO Overflow Error Indication
1600 * Bit 0 EFLX_OVFI
1602 #define SUNI1x10GEXP_BITMSK_EFLX_OVFI 0x0001
1605 * Register 0x3210: EFLX Channel Provision
1606 * Bit 0 EFLX_PROV
1608 #define SUNI1x10GEXP_BITMSK_EFLX_PROV 0x0001
1611 * Register 0x3280: PL4IDU Configuration
1614 * Bit 0 PL4IDU_EN_DFWD
1616 #define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN 0x0004
1617 #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS 0x0002
1618 #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD 0x0001
1621 * Register 0x3282: PL4IDU Interrupt Mask
1624 #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E 0x0002
1627 * Register 0x3283: PL4IDU Interrupt
1630 #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I 0x0002