Lines Matching +full:0 +full:x3210
45 #define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \
88 return 0; in pmread()
94 return 0; in pmwrite()
100 return 0; in pm3393_reset()
117 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
118 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
119 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
120 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
123 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_enable()
124 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_enable()
125 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); in pm3393_interrupt_enable()
126 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); in pm3393_interrupt_enable()
128 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff); in pm3393_interrupt_enable()
129 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff); in pm3393_interrupt_enable()
130 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
131 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
132 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff); in pm3393_interrupt_enable()
133 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff); in pm3393_interrupt_enable()
134 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff); in pm3393_interrupt_enable()
135 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff); in pm3393_interrupt_enable()
136 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff); in pm3393_interrupt_enable()
142 0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ ); in pm3393_interrupt_enable()
148 return 0; in pm3393_interrupt_enable()
156 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
157 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
158 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
159 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
160 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_disable()
161 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_disable()
162 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); in pm3393_interrupt_disable()
163 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); in pm3393_interrupt_disable()
164 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0); in pm3393_interrupt_disable()
165 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0); in pm3393_interrupt_disable()
166 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
167 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
168 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0); in pm3393_interrupt_disable()
169 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0); in pm3393_interrupt_disable()
170 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0); in pm3393_interrupt_disable()
171 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0); in pm3393_interrupt_disable()
172 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0); in pm3393_interrupt_disable()
175 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
187 return 0; in pm3393_interrupt_disable()
197 * bit WCIMODE=0 for a clear-on-read. in pm3393_interrupt_clear()
231 return 0; in pm3393_interrupt_clear()
243 dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n", in pm3393_interrupt_handler()
249 return 0; in pm3393_interrupt_handler()
269 return 0; in pm3393_enable()
278 memset(&cmac->stats, 0, sizeof(struct cmac_statistics)); in pm3393_enable_port()
287 t1_link_changed(cmac->adapter, 0); in pm3393_enable_port()
288 return 0; in pm3393_enable_port()
305 return 0; in pm3393_disable()
310 return 0; in pm3393_loopback_enable()
315 return 0; in pm3393_loopback_disable()
333 return 0; in pm3393_set_mtu()
357 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff); in pm3393_set_rx_mode()
358 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff); in pm3393_set_rx_mode()
359 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff); in pm3393_set_rx_mode()
360 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff); in pm3393_set_rx_mode()
366 u16 mc_filter[4] = { 0, }; in pm3393_set_rx_mode()
370 bit = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x3f; in pm3393_set_rx_mode()
371 mc_filter[bit >> 4] |= 1 << (bit & 0xf); in pm3393_set_rx_mode()
373 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]); in pm3393_set_rx_mode()
385 return 0; in pm3393_set_rx_mode()
397 return 0; in pm3393_get_speed_duplex_fc()
403 if (speed >= 0 && speed != SPEED_10000) in pm3393_set_speed_duplex_fc()
405 if (duplex >= 0 && duplex != DUPLEX_FULL) in pm3393_set_speed_duplex_fc()
415 return 0; in pm3393_set_speed_duplex_fc()
423 (mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
424 ((u64)(val1 & 0xffff) << 16) | \
425 ((u64)(val2 & 0xff) << 32) | \
427 0xffffff0000000000ULL); \
448 ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) | in pm3393_update_statistics()
449 (((u64)val2 & 0xffff) << 32) | (((u64)val3 & 0xffff) << 48); in pm3393_update_statistics()
487 return 0; in pm3393_macaddress_get()
497 * ma[5] = 0x09 in pm3393_macaddress_set()
498 * ma[4] = 0x13 in pm3393_macaddress_set()
499 * ma[3] = 0x00 in pm3393_macaddress_set()
500 * ma[2] = 0x43 in pm3393_macaddress_set()
501 * ma[1] = 0x07 in pm3393_macaddress_set()
502 * ma[0] = 0x00 in pm3393_macaddress_set()
507 * low_bits[15:0] = ma[1]:ma[0] in pm3393_macaddress_set()
515 lo = ((u32) ma[1] << 8) | (u32) ma[0]; in pm3393_macaddress_set()
538 val &= 0xff0f; in pm3393_macaddress_set()
545 val |= 0x0090; in pm3393_macaddress_set()
550 return 0; in pm3393_macaddress_set()
591 t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000); in pm3393_mac_create()
592 t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000); in pm3393_mac_create()
593 t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800); in pm3393_mac_create()
594 t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001); /* PL4IO Enable */ in pm3393_mac_create()
595 t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800); in pm3393_mac_create()
596 t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800); in pm3393_mac_create()
597 t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800); in pm3393_mac_create()
598 t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800); in pm3393_mac_create()
599 t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800); in pm3393_mac_create()
600 t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800); in pm3393_mac_create()
601 t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800); in pm3393_mac_create()
602 t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800); in pm3393_mac_create()
603 t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800); in pm3393_mac_create()
604 t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800); in pm3393_mac_create()
605 t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800); in pm3393_mac_create()
606 t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800); in pm3393_mac_create()
607 t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800); in pm3393_mac_create()
608 t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800); in pm3393_mac_create()
609 t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800); in pm3393_mac_create()
610 t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800); in pm3393_mac_create()
611 t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00); in pm3393_mac_create()
612 t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202); /* PL4IO Calendar Repetitions */ in pm3393_mac_create()
614 t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080); /* EFLX Enable */ in pm3393_mac_create()
615 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000); /* EFLX Channel Deprovision */ in pm3393_mac_create()
616 t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000); /* EFLX Low Limit */ in pm3393_mac_create()
617 t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040); /* EFLX High Limit */ in pm3393_mac_create()
618 t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc); /* EFLX Almost Full */ in pm3393_mac_create()
619 t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199); /* EFLX Almost Empty */ in pm3393_mac_create()
620 t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240); /* EFLX Cut Through Threshold */ in pm3393_mac_create()
621 t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000); /* EFLX Indirect Register Update */ in pm3393_mac_create()
622 t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001); /* EFLX Channel Provision */ in pm3393_mac_create()
623 t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff); /* EFLX Undocumented */ in pm3393_mac_create()
624 t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff); /* EFLX Undocumented */ in pm3393_mac_create()
625 …t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff); /* EFLX enable overflow interrupt The other bit… in pm3393_mac_create()
626 t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff); /* EFLX Undocumented */ in pm3393_mac_create()
628 t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000); /* IFLX Configuration - enable */ in pm3393_mac_create()
629 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000); /* IFLX Channel Deprovision */ in pm3393_mac_create()
630 t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000); /* IFLX Low Limit */ in pm3393_mac_create()
631 t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100); /* IFLX High Limit */ in pm3393_mac_create()
632 t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00); /* IFLX Almost Full Limit */ in pm3393_mac_create()
633 t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599); /* IFLX Almost Empty Limit */ in pm3393_mac_create()
634 t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000); /* IFLX Indirect Register Update */ in pm3393_mac_create()
635 t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001); /* IFLX Channel Provision */ in pm3393_mac_create()
636 t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff); /* IFLX Undocumented */ in pm3393_mac_create()
637 t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff); /* IFLX Undocumented */ in pm3393_mac_create()
638 …t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff); /* IFLX Enable overflow interrupt. The other b… in pm3393_mac_create()
640 t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe); /* PL4MOS Undocumented */ in pm3393_mac_create()
641 t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff); /* PL4MOS Undocumented */ in pm3393_mac_create()
642 t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008); /* PL4MOS Starving Burst Size */ in pm3393_mac_create()
643 t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008); /* PL4MOS Hungry Burst Size */ in pm3393_mac_create()
644 t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008); /* PL4MOS Transfer Size */ in pm3393_mac_create()
645 t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005); /* PL4MOS Disable */ in pm3393_mac_create()
647 t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103); /* PL4ODP Training Repeat and SOP rule */ in pm3393_mac_create()
648 t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000); /* PL4ODP MAX_T setting */ in pm3393_mac_create()
650 …t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087); /* PL4IDU Enable data forward, port state machi… in pm3393_mac_create()
651 t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f); /* PL4IDU Enable Dip4 check error interrupts */ in pm3393_mac_create()
653 t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32); /* # TXXG Config */ in pm3393_mac_create()
655 t1_tpi_write(adapter, OFFSET(0x304d), 0x8000); in pm3393_mac_create()
656 t1_tpi_write(adapter, OFFSET(0x2040), 0x059c); /* # RXXG Config */ in pm3393_mac_create()
657 t1_tpi_write(adapter, OFFSET(0x2049), 0x0001); /* # RXXG Cut Through */ in pm3393_mac_create()
658 t1_tpi_write(adapter, OFFSET(0x2070), 0x0000); /* # Disable promiscuous mode */ in pm3393_mac_create()
660 /* Setup Exact Match Filter 0 to allow broadcast packets. in pm3393_mac_create()
662 t1_tpi_write(adapter, OFFSET(0x206e), 0x0000); /* # Disable Match Enable bit */ in pm3393_mac_create()
663 t1_tpi_write(adapter, OFFSET(0x204a), 0xffff); /* # low addr */ in pm3393_mac_create()
664 t1_tpi_write(adapter, OFFSET(0x204b), 0xffff); /* # mid addr */ in pm3393_mac_create()
665 t1_tpi_write(adapter, OFFSET(0x204c), 0xffff); /* # high addr */ in pm3393_mac_create()
666 t1_tpi_write(adapter, OFFSET(0x206e), 0x0009); /* # Enable Match Enable bit */ in pm3393_mac_create()
668 t1_tpi_write(adapter, OFFSET(0x0003), 0x0000); /* # NO SOP/ PAD_EN setup */ in pm3393_mac_create()
669 t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0); /* # RXEQB disabled */ in pm3393_mac_create()
670 t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f); /* # No Preemphasis */ in pm3393_mac_create()
699 * 1. Assert RSTB pin low ( write 0 ) in pm3393_mac_reset()
714 successful_reset = 0; in pm3393_mac_reset()
715 for (i = 0; i < 3 && !successful_reset; i++) { in pm3393_mac_reset()
768 "PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, " in pm3393_mac_reset()
769 "is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n", in pm3393_mac_reset()
773 return successful_reset ? 0 : 1; in pm3393_mac_reset()