Lines Matching +full:disable +full:- +full:eop
1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
61 adapter->regs + A_ESPI_CMD_ADDR); in tricn_write()
62 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write()
65 busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY; in tricn_write()
66 } while (busy && --attempts); in tricn_write()
69 pr_err("%s: TRICN write timed out\n", adapter->name); in tricn_write()
78 if (!(readl(adapter->regs + A_ESPI_RX_RESET) & F_RX_CLK_STATUS)) { in tricn_init()
79 pr_err("%s: ESPI clock not ready\n", adapter->name); in tricn_init()
80 return -1; in tricn_init()
83 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); in tricn_init()
103 adapter->regs + A_ESPI_RX_RESET); in tricn_init()
110 u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
119 enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK; in t1_espi_intr_enable()
120 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_enable()
121 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable()
126 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_clear()
127 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_clear()
128 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear()
133 u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
135 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_disable()
136 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable()
141 u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
144 espi->intr_cnt.DIP4_err++; in t1_espi_intr_handler()
146 espi->intr_cnt.rx_drops++; in t1_espi_intr_handler()
148 espi->intr_cnt.tx_drops++; in t1_espi_intr_handler()
150 espi->intr_cnt.rx_ovflw++; in t1_espi_intr_handler()
152 espi->intr_cnt.parity_err++; in t1_espi_intr_handler()
154 espi->intr_cnt.DIP2_parity_err++; in t1_espi_intr_handler()
160 readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT); in t1_espi_intr_handler()
167 if (status && t1_is_T1B(espi->adapter)) in t1_espi_intr_handler()
169 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_handler()
175 return &espi->intr_cnt; in t1_espi_get_intr_counts()
182 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); in espi_setup_for_pm3393()
183 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1); in espi_setup_for_pm3393()
184 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); in espi_setup_for_pm3393()
185 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3); in espi_setup_for_pm3393()
186 writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_pm3393()
187 writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_pm3393()
188 writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_pm3393()
189 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); in espi_setup_for_pm3393()
190 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG); in espi_setup_for_pm3393()
195 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); in espi_setup_for_vsc7321()
196 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1); in espi_setup_for_vsc7321()
197 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); in espi_setup_for_vsc7321()
198 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_vsc7321()
199 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_vsc7321()
200 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_vsc7321()
201 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG); in espi_setup_for_vsc7321()
203 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); in espi_setup_for_vsc7321()
211 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); in espi_setup_for_ixf1010()
214 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
215 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
217 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
218 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
221 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); in espi_setup_for_ixf1010()
222 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); in espi_setup_for_ixf1010()
224 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG); in espi_setup_for_ixf1010()
231 adapter_t *adapter = espi->adapter; in t1_espi_init()
233 /* Disable ESPI training. MACs that can handle it enable it below. */ in t1_espi_init()
234 writel(0, adapter->regs + A_ESPI_TRAIN); in t1_espi_init()
239 V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
241 adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); in t1_espi_init()
243 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); in t1_espi_init()
253 return -1; in t1_espi_init()
256 adapter->regs + A_ESPI_FIFO_STATUS_ENABLE); in t1_espi_init()
262 * (sop,eop) counter to reduce PIOs for T/N210 workaround. in t1_espi_init()
264 espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
265 espi->misc_ctrl &= ~MON_MASK; in t1_espi_init()
266 espi->misc_ctrl |= F_MONITORED_DIRECTION; in t1_espi_init()
267 if (adapter->params.nports == 1) in t1_espi_init()
268 espi->misc_ctrl |= F_MONITORED_INTERFACE; in t1_espi_init()
269 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_init()
270 spin_lock_init(&espi->lock); in t1_espi_init()
286 espi->adapter = adapter; in t1_espi_create()
293 struct peespi *espi = adapter->espi;
297 spin_lock(&espi->lock);
298 espi->misc_ctrl = (val & ~MON_MASK) |
299 (espi->misc_ctrl & MON_MASK);
300 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
301 spin_unlock(&espi->lock);
307 struct peespi *espi = adapter->espi; in t1_espi_get_mon()
315 if (!spin_trylock(&espi->lock)) in t1_espi_get_mon()
318 spin_lock(&espi->lock); in t1_espi_get_mon()
320 if ((sel != (espi->misc_ctrl & MON_MASK))) { in t1_espi_get_mon()
321 writel(((espi->misc_ctrl & ~MON_MASK) | sel), in t1_espi_get_mon()
322 adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon()
323 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
324 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon()
326 sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon()
327 spin_unlock(&espi->lock); in t1_espi_get_mon()
338 struct peespi *espi = adapter->espi; in t1_espi_get_mon_t204()
339 u8 i, nport = (u8)adapter->params.nports; in t1_espi_get_mon_t204()
342 if (!spin_trylock(&espi->lock)) in t1_espi_get_mon_t204()
343 return -1; in t1_espi_get_mon_t204()
345 spin_lock(&espi->lock); in t1_espi_get_mon_t204()
347 if ((espi->misc_ctrl & MON_MASK) != F_MONITORED_DIRECTION) { in t1_espi_get_mon_t204()
348 espi->misc_ctrl = (espi->misc_ctrl & ~MON_MASK) | in t1_espi_get_mon_t204()
350 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()
354 writel(espi->misc_ctrl | V_MONITORED_PORT_NUM(i), in t1_espi_get_mon_t204()
355 adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()
357 *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3); in t1_espi_get_mon_t204()
360 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); in t1_espi_get_mon_t204()
361 spin_unlock(&espi->lock); in t1_espi_get_mon_t204()