Lines Matching +full:0 +full:x27200
212 #define OCTNIC_NCMD_AUTONEG_ON 0x1
213 #define OCTNIC_NCMD_PHY_ON 0x2
270 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
282 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
391 return 0; in lio_get_link_ksettings()
425 return 0; in lio_set_link_ksettings()
432 return 0; in lio_set_link_ksettings()
444 memset(drvinfo, 0, sizeof(struct ethtool_drvinfo)); in lio_get_drvinfo()
461 memset(drvinfo, 0, sizeof(struct ethtool_drvinfo)); in lio_get_vf_drvinfo()
475 int ret = 0; in lio_send_queue_count_update()
477 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in lio_send_queue_count_update()
479 nctrl.ncmd.u64 = 0; in lio_send_queue_count_update()
483 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in lio_send_queue_count_update()
489 dev_err(&oct->pci_dev->dev, "Failed to send Queue reset command (ret: 0x%x)\n", in lio_send_queue_count_update()
494 return 0; in lio_send_queue_count_update()
503 u32 max_rx = 0, max_tx = 0, tx_count = 0, rx_count = 0; in lio_ethtool_get_channels()
504 u32 combined_count = 0, max_combined = 0; in lio_ethtool_get_channels()
524 u64 reg_val = 0ULL; in lio_ethtool_get_channels()
525 u64 ctrl = CN23XX_VF_SLI_IQ_PKT_CONTROL64(0); in lio_ethtool_get_channels()
545 int num_msix_irqs = 0; in lio_irq_reallocate_irqs()
549 return 0; in lio_irq_reallocate_irqs()
563 for (i = 0; i < num_msix_irqs; i++) { in lio_irq_reallocate_irqs()
570 oct->ioq_vector[i].vector = 0; in lio_irq_reallocate_irqs()
599 return 0; in lio_irq_reallocate_irqs()
609 int stopped = 0; in lio_ethtool_set_channels()
611 if (strcmp(oct->fw_info.liquidio_firmware_version, "1.6.1") < 0) { in lio_ethtool_set_channels()
634 u64 reg_val = 0ULL; in lio_ethtool_set_channels()
635 u64 ctrl = CN23XX_VF_SLI_IQ_PKT_CONTROL64(0); in lio_ethtool_set_channels()
648 return 0; in lio_ethtool_set_channels()
665 return 0; in lio_ethtool_set_channels()
702 return 0; in lio_get_eeprom()
710 int ret = 0; in octnet_gpio_access()
712 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in octnet_gpio_access()
714 nctrl.ncmd.u64 = 0; in octnet_gpio_access()
718 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_gpio_access()
729 return 0; in octnet_gpio_access()
737 int ret = 0; in octnet_id_active()
739 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in octnet_id_active()
741 nctrl.ncmd.u64 = 0; in octnet_id_active()
744 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_id_active()
755 return 0; in octnet_id_active()
768 int retval = 0; in octnet_mdio45_access()
773 sizeof(struct oct_mdio_cmd_resp), 0); in octnet_mdio45_access()
787 sc->iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_mdio45_access()
790 0, 0, 0); in octnet_mdio45_access()
806 retval = wait_for_sc_completion_timeout(oct_dev, sc, 0); in octnet_mdio45_access()
853 ret = octnet_mdio45_access(lio, 0, in lio_set_phys_id()
859 ret = octnet_mdio45_access(lio, 0, in lio_set_phys_id()
885 return 0; in lio_set_phys_id()
937 return 0; in lio_set_phys_id()
947 return 0; in lio_set_phys_id()
958 u32 tx_max_pending = 0, rx_max_pending = 0, tx_pending = 0, in lio_ethtool_get_ringparam()
959 rx_pending = 0; in lio_ethtool_get_ringparam()
974 rx_pending = oct->droq[0]->max_count; in lio_ethtool_get_ringparam()
975 tx_pending = oct->instr_queue[0]->max_count; in lio_ethtool_get_ringparam()
982 ering->rx_mini_pending = 0; in lio_ethtool_get_ringparam()
983 ering->rx_jumbo_pending = 0; in lio_ethtool_get_ringparam()
984 ering->rx_mini_max_pending = 0; in lio_ethtool_get_ringparam()
985 ering->rx_jumbo_max_pending = 0; in lio_ethtool_get_ringparam()
1004 resp_size, 0); in lio_23xx_reconfigure_queue_count()
1020 if_cfg.u64 = 0; in lio_23xx_reconfigure_queue_count()
1026 sc->iq_no = 0; in lio_23xx_reconfigure_queue_count()
1028 OPCODE_NIC_QCOUNT_UPDATE, 0, in lio_23xx_reconfigure_queue_count()
1029 if_cfg.u64, 0); in lio_23xx_reconfigure_queue_count()
1043 retval = wait_for_sc_completion_timeout(oct, sc, 0); in lio_23xx_reconfigure_queue_count()
1061 for (j = 0; j < lio->linfo.num_rxpciq; j++) { in lio_23xx_reconfigure_queue_count()
1066 for (j = 0; j < lio->linfo.num_txpciq; j++) { in lio_23xx_reconfigure_queue_count()
1074 lio->txq = lio->linfo.txpciq[0].s.q_no; in lio_23xx_reconfigure_queue_count()
1075 lio->rxq = lio->linfo.rxpciq[0].s.q_no; in lio_23xx_reconfigure_queue_count()
1082 return 0; in lio_23xx_reconfigure_queue_count()
1089 int i, queue_count_update = 0; in lio_reset_queues()
1153 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { in lio_reset_queues()
1159 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { in lio_reset_queues()
1217 for (i = 0; i < oct->num_oqs; i++) in lio_reset_queues()
1232 if (liquidio_setup_io_queues(oct, 0, num_qs, num_qs)) { in lio_reset_queues()
1256 return 0; in lio_reset_queues()
1268 int stopped = 0; in lio_ethtool_set_ringparam()
1281 rx_count_old = oct->droq[0]->max_count; in lio_ethtool_set_ringparam()
1282 tx_count_old = oct->instr_queue[0]->max_count; in lio_ethtool_set_ringparam()
1285 return 0; in lio_ethtool_set_ringparam()
1310 return 0; in lio_ethtool_set_ringparam()
1336 OCTNET_CMD_VERBOSE_ENABLE, 0); in lio_set_msglevel()
1339 OCTNET_CMD_VERBOSE_DISABLE, 0); in lio_set_msglevel()
1361 pause->autoneg = 0; in lio_get_pauseparam()
1378 int ret = 0; in lio_set_pauseparam()
1383 if (linfo->link.s.duplex == 0) { in lio_set_pauseparam()
1393 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in lio_set_pauseparam()
1395 nctrl.ncmd.u64 = 0; in lio_set_pauseparam()
1397 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in lio_set_pauseparam()
1406 nctrl.ncmd.s.param1 = 0; in lio_set_pauseparam()
1414 nctrl.ncmd.s.param2 = 0; in lio_set_pauseparam()
1427 return 0; in lio_set_pauseparam()
1438 int i = 0, j; in lio_get_ethtool_stats()
1639 for (j = 0; j < MAX_OCTEON_INSTR_QUEUES(oct_dev); j++) { in lio_get_ethtool_stats()
1682 for (j = 0; j < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); j++) { in lio_get_ethtool_stats()
1727 int i = 0, j, vj; in lio_vf_get_ethtool_stats()
1761 for (vj = 0; vj < oct_dev->num_iqs; vj++) { in lio_vf_get_ethtool_stats()
1803 for (vj = 0; vj < oct_dev->num_oqs; vj++) { in lio_vf_get_ethtool_stats()
1840 for (i = 0; i < ARRAY_SIZE(oct_priv_flags_strings); i++) { in lio_get_priv_flags_strings()
1864 for (j = 0; j < num_stats; j++) { in lio_get_strings()
1870 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) { in lio_get_strings()
1873 for (j = 0; j < num_iq_stats; j++) { in lio_get_strings()
1881 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) { in lio_get_strings()
1884 for (j = 0; j < num_oq_stats; j++) { in lio_get_strings()
1912 for (j = 0; j < num_stats; j++) { in lio_vf_get_strings()
1918 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) { in lio_vf_get_strings()
1921 for (j = 0; j < num_iq_stats; j++) { in lio_vf_get_strings()
1929 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) { in lio_vf_get_strings()
1932 for (j = 0; j < num_oq_stats; j++) { in lio_vf_get_strings()
2012 0, in octnet_get_intrmod_cfg()
2013 sizeof(struct oct_intrmod_resp), 0); in octnet_get_intrmod_cfg()
2019 memset(resp, 0, sizeof(struct oct_intrmod_resp)); in octnet_get_intrmod_cfg()
2021 sc->iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_get_intrmod_cfg()
2024 OPCODE_NIC_INTRMOD_PARAMS, 0, 0, 0); in octnet_get_intrmod_cfg()
2038 retval = wait_for_sc_completion_timeout(oct_dev, sc, 0); in octnet_get_intrmod_cfg()
2054 return 0; in octnet_get_intrmod_cfg()
2070 16, 0); in octnet_set_intrmod_cfg()
2080 sc->iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_set_intrmod_cfg()
2083 OPCODE_NIC_INTRMOD_CFG, 0, 0, 0); in octnet_set_intrmod_cfg()
2097 retval = wait_for_sc_completion_timeout(oct_dev, sc, 0); in octnet_set_intrmod_cfg()
2102 if (retval == 0) { in octnet_set_intrmod_cfg()
2108 return 0; in octnet_set_intrmod_cfg()
2154 iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no]; in lio_get_intr_coalesce()
2189 return 0; in lio_get_intr_coalesce()
2197 int ret = 0; in oct_cfg_adaptive_intr()
2259 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2265 (0x3fffff00000000UL)) | in oct_cfg_rx_intrcnt()
2281 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2286 (0x3fffff00000000UL)) | in oct_cfg_rx_intrcnt()
2297 return 0; in oct_cfg_rx_intrcnt()
2337 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2360 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2375 return 0; in oct_cfg_rx_intrtime()
2403 for (q_no = 0; q_no < oct->num_iqs; q_no++) { in oct_cfg_tx_intrcnt()
2407 val = (val & 0xFFFF000000000000ULL) | in oct_cfg_tx_intrcnt()
2420 return 0; in oct_cfg_tx_intrcnt()
2431 struct oct_intrmod_cfg intrmod = {0}; in lio_set_intr_coalesce()
2442 for (j = 0; j < lio->linfo.num_txpciq; j++) { in lio_set_intr_coalesce()
2462 intrmod.rx_enable = intr_coal->use_adaptive_rx_coalesce ? 1 : 0; in lio_set_intr_coalesce()
2463 intrmod.tx_enable = intr_coal->use_adaptive_tx_coalesce ? 1 : 0; in lio_set_intr_coalesce()
2494 return 0; in lio_set_intr_coalesce()
2521 return 0; in lio_get_ts_info()
2545 int len = 0; in cn23xx_read_csr_reg()
2552 /*0x29030 or 0x29040*/ in cn23xx_read_csr_reg()
2559 /*0x27080 or 0x27090*/ in cn23xx_read_csr_reg()
2566 /*0x27000 or 0x27010*/ in cn23xx_read_csr_reg()
2573 /*0x29120*/ in cn23xx_read_csr_reg()
2574 reg = 0x29120; in cn23xx_read_csr_reg()
2578 /*0x27300*/ in cn23xx_read_csr_reg()
2579 reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2585 /*0x27200*/ in cn23xx_read_csr_reg()
2586 reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2598 /*0x29140*/ in cn23xx_read_csr_reg()
2603 /*0x29160*/ in cn23xx_read_csr_reg()
2604 reg = 0x29160; in cn23xx_read_csr_reg()
2608 /*0x29180*/ in cn23xx_read_csr_reg()
2613 /*0x291E0*/ in cn23xx_read_csr_reg()
2618 /*0x29210*/ in cn23xx_read_csr_reg()
2624 /*0x29220*/ in cn23xx_read_csr_reg()
2625 reg = 0x29220; in cn23xx_read_csr_reg()
2630 if (pf_num == 0) { in cn23xx_read_csr_reg()
2631 /*0x29260*/ in cn23xx_read_csr_reg()
2637 /*0x29270*/ in cn23xx_read_csr_reg()
2644 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2651 /*0x10040*/ in cn23xx_read_csr_reg()
2652 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2659 /*0x10080*/ in cn23xx_read_csr_reg()
2660 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2667 /*0x10090*/ in cn23xx_read_csr_reg()
2668 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2675 /*0x10050*/ in cn23xx_read_csr_reg()
2676 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2684 /*0x10070*/ in cn23xx_read_csr_reg()
2685 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2692 /*0x100a0*/ in cn23xx_read_csr_reg()
2693 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2700 /*0x100b0*/ in cn23xx_read_csr_reg()
2701 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2707 /*0x100c0*/ in cn23xx_read_csr_reg()
2708 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2709 reg = 0x100c0 + i * CN23XX_OQ_OFFSET; in cn23xx_read_csr_reg()
2714 /*0x10000*/ in cn23xx_read_csr_reg()
2715 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2723 /*0x10010*/ in cn23xx_read_csr_reg()
2724 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2732 /*0x10020*/ in cn23xx_read_csr_reg()
2733 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2741 /*0x10030*/ in cn23xx_read_csr_reg()
2742 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2750 /*0x10040*/ in cn23xx_read_csr_reg()
2751 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) in cn23xx_read_csr_reg()
2763 int len = 0; in cn23xx_vf_read_csr_reg()
2771 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2778 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2785 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2792 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2799 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2806 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2813 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2820 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2826 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2827 reg = 0x100c0 + i * CN23XX_VF_OQ_OFFSET; in cn23xx_vf_read_csr_reg()
2833 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2834 reg = 0x100d0 + i * CN23XX_VF_IQ_OFFSET; in cn23xx_vf_read_csr_reg()
2840 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2847 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2854 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2861 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2868 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2881 int i, len = 0; in cn6xxx_read_csr_reg()
2909 len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 0): %08x\n", in cn6xxx_read_csr_reg()
2919 for (i = 0; i < oct->num_oqs; i++) { in cn6xxx_read_csr_reg()
2935 for (i = 0; i <= 3; i++) { in cn6xxx_read_csr_reg()
2949 CN6XXX_DMA_CNT(0), in cn6xxx_read_csr_reg()
2950 octeon_read_csr(oct, CN6XXX_DMA_CNT(0))); in cn6xxx_read_csr_reg()
2951 reg = CN6XXX_DMA_PKT_INT_LEVEL(0); in cn6xxx_read_csr_reg()
2953 CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2954 reg = CN6XXX_DMA_TIME_INT_LEVEL(0); in cn6xxx_read_csr_reg()
2956 CN6XXX_DMA_TIME_INT_LEVEL(0), in cn6xxx_read_csr_reg()
2975 for (i = 0; i < 16; i++) { in cn6xxx_read_csr_reg()
2987 int i, len = 0; in cn6xxx_read_config_reg()
2994 for (i = 0; i <= 13; i++) { in cn6xxx_read_config_reg()
2996 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n", in cn6xxx_read_config_reg()
3002 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n", in cn6xxx_read_config_reg()
3014 int len = 0; in lio_get_regs()
3021 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX); in lio_get_regs()
3025 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX_VF); in lio_get_regs()
3030 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN); in lio_get_regs()
3050 bool intr_by_tx_bytes = !!(flags & (0x1 << OCT_PRIV_FLAG_TX_BYTES)); in lio_set_priv_flags()
3054 return 0; in lio_set_priv_flags()
3069 return 0; in lio_get_fecparam()
3079 return 0; in lio_get_fecparam()
3094 liquidio_set_fec(lio, 0); in lio_set_fecparam()
3103 return 0; in lio_set_fecparam()