39 static int cn23xx_pf_soft_reset(struct octeon_device *oct)  in cn23xx_pf_soft_reset()  argument
41 	octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF);  in cn23xx_pf_soft_reset()
43 	dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: BIST enabled for CN23XX soft reset\n",  in cn23xx_pf_soft_reset()
44 		oct->octeon_id);  in cn23xx_pf_soft_reset()
46 	octeon_write_csr64(oct, CN23XX_SLI_SCRATCH1, 0x1234ULL);  in cn23xx_pf_soft_reset()
49 	lio_pci_readq(oct, CN23XX_RST_SOFT_RST);  in cn23xx_pf_soft_reset()
50 	lio_pci_writeq(oct, 1, CN23XX_RST_SOFT_RST);  in cn23xx_pf_soft_reset()
55 	if (octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1)) {  in cn23xx_pf_soft_reset()
56 		dev_err(&oct->pci_dev->dev, "OCTEON[%d]: Soft reset failed\n",  in cn23xx_pf_soft_reset()
57 			oct->octeon_id);  in cn23xx_pf_soft_reset()
61 	dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Reset completed\n",  in cn23xx_pf_soft_reset()
62 		oct->octeon_id);  in cn23xx_pf_soft_reset()
65 	octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF);  in cn23xx_pf_soft_reset()
70 static void cn23xx_enable_error_reporting(struct octeon_device *oct)  in cn23xx_enable_error_reporting()  argument
75 	pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);  in cn23xx_enable_error_reporting()
79 		pci_read_config_dword(oct->pci_dev,  in cn23xx_enable_error_reporting()
82 		pci_read_config_dword(oct->pci_dev,  in cn23xx_enable_error_reporting()
85 		dev_err(&oct->pci_dev->dev, "PCI-E Fatal error detected;\n"  in cn23xx_enable_error_reporting()
95 	dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Enabling PCI-E error reporting..\n",  in cn23xx_enable_error_reporting()
96 		oct->octeon_id);  in cn23xx_enable_error_reporting()
97 	pci_write_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, regval);  in cn23xx_enable_error_reporting()
100 static u32 cn23xx_coprocessor_clock(struct octeon_device *oct)  in cn23xx_coprocessor_clock()  argument
107 	return (((lio_pci_readq(oct, CN23XX_RST_BOOT) >> 24) & 0x3f) * 50);  in cn23xx_coprocessor_clock()
110 u32 cn23xx_pf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us)  in cn23xx_pf_get_oq_ticks()  argument
113 	u32 oqticks_per_us = cn23xx_coprocessor_clock(oct);  in cn23xx_pf_get_oq_ticks()
115 	oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us;  in cn23xx_pf_get_oq_ticks()
132 static void cn23xx_setup_global_mac_regs(struct octeon_device *oct)  in cn23xx_setup_global_mac_regs()  argument
134 	u16 mac_no = oct->pcie_port;  in cn23xx_setup_global_mac_regs()
135 	u16 pf_num = oct->pf_num;  in cn23xx_setup_global_mac_regs()
141 	dev_dbg(&oct->pci_dev->dev, "%s:Using pcie port %d\n",  in cn23xx_setup_global_mac_regs()
146 	    octeon_read_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num));  in cn23xx_setup_global_mac_regs()
148 	if (oct->rev_id == OCTEON_CN23XX_REV_1_1) {  in cn23xx_setup_global_mac_regs()
158 		  (oct->sriov_info.trs << CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS);  in cn23xx_setup_global_mac_regs()
160 	temp = oct->sriov_info.rings_per_vf & 0xff;  in cn23xx_setup_global_mac_regs()
164 	temp = oct->sriov_info.max_vfs & 0xff;  in cn23xx_setup_global_mac_regs()
168 	octeon_write_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num),  in cn23xx_setup_global_mac_regs()
171 	dev_dbg(&oct->pci_dev->dev, "SLI_PKT_MAC(%d)_PF(%d)_RINFO : 0x%016llx\n",  in cn23xx_setup_global_mac_regs()
173 		(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num)));  in cn23xx_setup_global_mac_regs()
176 static int cn23xx_reset_io_queues(struct octeon_device *oct)  in cn23xx_reset_io_queues()  argument
183 	srn = oct->sriov_info.pf_srn;  in cn23xx_reset_io_queues()
184 	ern = srn + oct->sriov_info.num_pf_rings;  in cn23xx_reset_io_queues()
192 		d64 = octeon_read_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));  in cn23xx_reset_io_queues()
194 		octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), d64);  in cn23xx_reset_io_queues()
199 		u64 reg_val = octeon_read_csr64(oct,  in cn23xx_reset_io_queues()
205 			    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)));  in cn23xx_reset_io_queues()
208 			dev_err(&oct->pci_dev->dev,  in cn23xx_reset_io_queues()
215 		octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),  in cn23xx_reset_io_queues()
219 			   oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)));  in cn23xx_reset_io_queues()
221 			dev_err(&oct->pci_dev->dev,  in cn23xx_reset_io_queues()
231 static int cn23xx_pf_setup_global_input_regs(struct octeon_device *oct)  in cn23xx_pf_setup_global_input_regs()  argument
233 	struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;  in cn23xx_pf_setup_global_input_regs()
240 	pf_num = oct->pf_num;  in cn23xx_pf_setup_global_input_regs()
242 	srn = oct->sriov_info.pf_srn;  in cn23xx_pf_setup_global_input_regs()
243 	ern = srn + oct->sriov_info.num_pf_rings;  in cn23xx_pf_setup_global_input_regs()
245 	if (cn23xx_reset_io_queues(oct))  in cn23xx_pf_setup_global_input_regs()
254 		reg_val = (u64)oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;  in cn23xx_pf_setup_global_input_regs()
257 		if (q_no < oct->sriov_info.pf_srn) {  in cn23xx_pf_setup_global_input_regs()
258 			vf_num = q_no / oct->sriov_info.rings_per_vf;  in cn23xx_pf_setup_global_input_regs()
267 		octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),  in cn23xx_pf_setup_global_input_regs()
277 		iq = oct->instr_queue[q_no];  in cn23xx_pf_setup_global_input_regs()
281 			inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr +  in cn23xx_pf_setup_global_input_regs()
285 		    octeon_read_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));  in cn23xx_pf_setup_global_input_regs()
289 		octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),  in cn23xx_pf_setup_global_input_regs()
306 static void cn23xx_pf_setup_global_output_regs(struct octeon_device *oct)  in cn23xx_pf_setup_global_output_regs()  argument
312 	struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;  in cn23xx_pf_setup_global_output_regs()
314 	srn = oct->sriov_info.pf_srn;  in cn23xx_pf_setup_global_output_regs()
315 	ern = srn + oct->sriov_info.num_pf_rings;  in cn23xx_pf_setup_global_output_regs()
318 		octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 32);  in cn23xx_pf_setup_global_output_regs()
321 		octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 0);  in cn23xx_pf_setup_global_output_regs()
325 		reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no));  in cn23xx_pf_setup_global_output_regs()
358 		octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no), reg_val);  in cn23xx_pf_setup_global_output_regs()
360 		/* Enabling these interrupt in oct->fn_list.enable_interrupt()  in cn23xx_pf_setup_global_output_regs()
366 		    oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));  in cn23xx_pf_setup_global_output_regs()
368 		octeon_write_csr64(oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),  in cn23xx_pf_setup_global_output_regs()
374 	writeq(0x40, (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_WMARK);  in cn23xx_pf_setup_global_output_regs()
380 	if ((oct->rev_id == OCTEON_CN23XX_REV_1_0) ||  in cn23xx_pf_setup_global_output_regs()
381 	    (oct->rev_id == OCTEON_CN23XX_REV_1_1))  in cn23xx_pf_setup_global_output_regs()
382 		writeq(readq((u8 *)oct->mmio[0].hw_addr +  in cn23xx_pf_setup_global_output_regs()
384 		       (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_GBL_CONTROL);  in cn23xx_pf_setup_global_output_regs()
387 	if (oct->pf_num)  in cn23xx_pf_setup_global_output_regs()
389 		       (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN2_W1S);  in cn23xx_pf_setup_global_output_regs()
392 		       (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN_W1S);  in cn23xx_pf_setup_global_output_regs()
395 static int cn23xx_setup_pf_device_regs(struct octeon_device *oct)  in cn23xx_setup_pf_device_regs()  argument
397 	cn23xx_enable_error_reporting(oct);  in cn23xx_setup_pf_device_regs()
400 	cn23xx_setup_global_mac_regs(oct);  in cn23xx_setup_pf_device_regs()
402 	if (cn23xx_pf_setup_global_input_regs(oct))  in cn23xx_setup_pf_device_regs()
405 	cn23xx_pf_setup_global_output_regs(oct);  in cn23xx_setup_pf_device_regs()
410 	octeon_write_csr64(oct, CN23XX_SLI_WINDOW_CTL,  in cn23xx_setup_pf_device_regs()
414 	octeon_write_csr64(oct, CN23XX_SLI_PKT_IN_JABBER, CN23XX_INPUT_JABBER);  in cn23xx_setup_pf_device_regs()
418 static void cn23xx_setup_iq_regs(struct octeon_device *oct, u32 iq_no)  in cn23xx_setup_iq_regs()  argument
420 	struct octeon_instr_queue *iq = oct->instr_queue[iq_no];  in cn23xx_setup_iq_regs()
423 	iq_no += oct->sriov_info.pf_srn;  in cn23xx_setup_iq_regs()
426 	octeon_write_csr64(oct, CN23XX_SLI_IQ_BASE_ADDR64(iq_no),  in cn23xx_setup_iq_regs()
428 	octeon_write_csr(oct, CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count);  in cn23xx_setup_iq_regs()
434 	    (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_DOORBELL(iq_no);  in cn23xx_setup_iq_regs()
436 	    (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_INSTR_COUNT64(iq_no);  in cn23xx_setup_iq_regs()
437 	dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",  in cn23xx_setup_iq_regs()
445 	if (oct->msix_on) {  in cn23xx_setup_iq_regs()
459 static void cn23xx_setup_oq_regs(struct octeon_device *oct, u32 oq_no)  in cn23xx_setup_oq_regs()  argument
462 	struct octeon_droq *droq = oct->droq[oq_no];  in cn23xx_setup_oq_regs()
463 	struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;  in cn23xx_setup_oq_regs()
467 	oq_no += oct->sriov_info.pf_srn;  in cn23xx_setup_oq_regs()
469 	octeon_write_csr64(oct, CN23XX_SLI_OQ_BASE_ADDR64(oq_no),  in cn23xx_setup_oq_regs()
471 	octeon_write_csr(oct, CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count);  in cn23xx_setup_oq_regs()
473 	octeon_write_csr(oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no),  in cn23xx_setup_oq_regs()
478 	    (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_PKTS_SENT(oq_no);  in cn23xx_setup_oq_regs()
480 	    (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_PKTS_CREDIT(oq_no);  in cn23xx_setup_oq_regs()
482 	if (!oct->msix_on) {  in cn23xx_setup_oq_regs()
486 		    octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no));  in cn23xx_setup_oq_regs()
488 		octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no),  in cn23xx_setup_oq_regs()
494 		    octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no));  in cn23xx_setup_oq_regs()
496 		octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no),  in cn23xx_setup_oq_regs()
500 		    oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));  in cn23xx_setup_oq_regs()
504 		    oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(oq_no),  in cn23xx_setup_oq_regs()
513 	struct octeon_device *oct = mbox->oct_dev;  in cn23xx_pf_mbox_thread()  local
517 	if (oct->rev_id < OCTEON_CN23XX_REV_1_1) {  in cn23xx_pf_mbox_thread()
522 		for (i = 0; i < oct->sriov_info.num_vfs_alloced; i++) {  in cn23xx_pf_mbox_thread()
523 			q_no = i * oct->sriov_info.rings_per_vf;  in cn23xx_pf_mbox_thread()
525 			val64 = readq(oct->mbox[q_no]->mbox_write_reg);  in cn23xx_pf_mbox_thread()
528 				if (octeon_mbox_read(oct->mbox[q_no]))  in cn23xx_pf_mbox_thread()
530 					    oct->mbox[q_no]);  in cn23xx_pf_mbox_thread()
540 static int cn23xx_setup_pf_mbox(struct octeon_device *oct)  in cn23xx_setup_pf_mbox()  argument
543 	u16 mac_no = oct->pcie_port;  in cn23xx_setup_pf_mbox()
544 	u16 pf_num = oct->pf_num;  in cn23xx_setup_pf_mbox()
547 	if (!oct->sriov_info.max_vfs)  in cn23xx_setup_pf_mbox()
550 	for (i = 0; i < oct->sriov_info.max_vfs; i++) {  in cn23xx_setup_pf_mbox()
551 		q_no = i * oct->sriov_info.rings_per_vf;  in cn23xx_setup_pf_mbox()
559 		mbox->oct_dev = oct;  in cn23xx_setup_pf_mbox()
566 		mbox->mbox_int_reg = (u8 *)oct->mmio[0].hw_addr +  in cn23xx_setup_pf_mbox()
570 		mbox->mbox_write_reg = (u8 *)oct->mmio[0].hw_addr +  in cn23xx_setup_pf_mbox()
574 		mbox->mbox_read_reg = (u8 *)oct->mmio[0].hw_addr +  in cn23xx_setup_pf_mbox()
582 		oct->mbox[q_no] = mbox;  in cn23xx_setup_pf_mbox()
587 	if (oct->rev_id < OCTEON_CN23XX_REV_1_1)  in cn23xx_setup_pf_mbox()
588 		schedule_delayed_work(&oct->mbox[0]->mbox_poll_wk.work,  in cn23xx_setup_pf_mbox()
596 		vfree(oct->mbox[i]);  in cn23xx_setup_pf_mbox()
602 static int cn23xx_free_pf_mbox(struct octeon_device *oct)  in cn23xx_free_pf_mbox()  argument
606 	if (!oct->sriov_info.max_vfs)  in cn23xx_free_pf_mbox()
609 	for (i = 0; i < oct->sriov_info.max_vfs; i++) {  in cn23xx_free_pf_mbox()
610 		q_no = i * oct->sriov_info.rings_per_vf;  in cn23xx_free_pf_mbox()
612 		    &oct->mbox[q_no]->mbox_poll_wk.work);  in cn23xx_free_pf_mbox()
613 		vfree(oct->mbox[q_no]);  in cn23xx_free_pf_mbox()
619 static int cn23xx_enable_io_queues(struct octeon_device *oct)  in cn23xx_enable_io_queues()  argument
625 	srn = oct->sriov_info.pf_srn;  in cn23xx_enable_io_queues()
626 	ern = srn + oct->num_iqs;  in cn23xx_enable_io_queues()
630 		if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) {  in cn23xx_enable_io_queues()
632 			    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));  in cn23xx_enable_io_queues()
635 			    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);  in cn23xx_enable_io_queues()
639 		if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) {  in cn23xx_enable_io_queues()
644 			    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));  in cn23xx_enable_io_queues()
652 					    oct,  in cn23xx_enable_io_queues()
656 					dev_err(&oct->pci_dev->dev,  in cn23xx_enable_io_queues()
663 				    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),  in cn23xx_enable_io_queues()
667 				    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));  in cn23xx_enable_io_queues()
669 					dev_err(&oct->pci_dev->dev,  in cn23xx_enable_io_queues()
676 			    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));  in cn23xx_enable_io_queues()
679 			    oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);  in cn23xx_enable_io_queues()
685 		if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) {  in cn23xx_enable_io_queues()
687 			    oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no));  in cn23xx_enable_io_queues()
689 			octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no),  in cn23xx_enable_io_queues()
696 static void cn23xx_disable_io_queues(struct octeon_device *oct)  in cn23xx_disable_io_queues()  argument
703 	srn = oct->sriov_info.pf_srn;  in cn23xx_disable_io_queues()
704 	ern = srn + oct->num_iqs;  in cn23xx_disable_io_queues()
712 			   oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)));  in cn23xx_disable_io_queues()
716 		octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),  in cn23xx_disable_io_queues()
723 					oct, CN23XX_SLI_PKT_IOQ_RING_RST));  in cn23xx_disable_io_queues()
726 					oct, CN23XX_SLI_PKT_IOQ_RING_RST));  in cn23xx_disable_io_queues()
731 		octeon_write_csr(oct, CN23XX_SLI_IQ_DOORBELL(q_no), 0xFFFFFFFF);  in cn23xx_disable_io_queues()
732 		while (octeon_read_csr64(oct, CN23XX_SLI_IQ_DOORBELL(q_no)) &&  in cn23xx_disable_io_queues()
747 					oct, CN23XX_SLI_PKT_IOQ_RING_RST));  in cn23xx_disable_io_queues()
750 					oct, CN23XX_SLI_PKT_IOQ_RING_RST));  in cn23xx_disable_io_queues()
755 		octeon_write_csr(oct, CN23XX_SLI_OQ_PKTS_CREDIT(q_no),  in cn23xx_disable_io_queues()
757 		while (octeon_read_csr64(oct,  in cn23xx_disable_io_queues()
765 					oct, CN23XX_SLI_OQ_PKTS_SENT(q_no)));  in cn23xx_disable_io_queues()
766 		octeon_write_csr(oct, CN23XX_SLI_OQ_PKTS_SENT(q_no),  in cn23xx_disable_io_queues()
774 	struct octeon_device *oct = ioq_vector->oct_dev;  in cn23xx_pf_msix_interrupt_handler()  local
777 	struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];  in cn23xx_pf_msix_interrupt_handler()
779 	dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct);  in cn23xx_pf_msix_interrupt_handler()
782 …dev_err(&oct->pci_dev->dev, "23XX bringup FIXME: oct pfnum:%d ioq_vector->ioq_num :%d droq is NULL…  in cn23xx_pf_msix_interrupt_handler()
783 			oct->pf_num, ioq_vector->ioq_num);  in cn23xx_pf_msix_interrupt_handler()
813 static void cn23xx_handle_pf_mbox_intr(struct octeon_device *oct)  in cn23xx_handle_pf_mbox_intr()  argument
819 	mbox_int_val = readq(oct->mbox[0]->mbox_int_reg);  in cn23xx_handle_pf_mbox_intr()
821 	for (i = 0; i < oct->sriov_info.num_vfs_alloced; i++) {  in cn23xx_handle_pf_mbox_intr()
822 		q_no = i * oct->sriov_info.rings_per_vf;  in cn23xx_handle_pf_mbox_intr()
826 			       oct->mbox[0]->mbox_int_reg);  in cn23xx_handle_pf_mbox_intr()
827 			if (octeon_mbox_read(oct->mbox[q_no])) {  in cn23xx_handle_pf_mbox_intr()
828 				work = &oct->mbox[q_no]->mbox_poll_wk.work;  in cn23xx_handle_pf_mbox_intr()
838 	struct octeon_device *oct = (struct octeon_device *)dev;  in cn23xx_interrupt_handler()  local
839 	struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;  in cn23xx_interrupt_handler()
842 	dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct);  in cn23xx_interrupt_handler()
845 	oct->int_status = 0;  in cn23xx_interrupt_handler()
848 		dev_err(&oct->pci_dev->dev, "OCTEON[%d]: Error Intr: 0x%016llx\n",  in cn23xx_interrupt_handler()
849 			oct->octeon_id, CVM_CAST64(intr64));  in cn23xx_interrupt_handler()
853 		cn23xx_handle_pf_mbox_intr(oct);  in cn23xx_interrupt_handler()
855 	if (oct->msix_on != LIO_FLAG_MSIX_ENABLED) {  in cn23xx_interrupt_handler()
857 			oct->int_status |= OCT_DEV_INTR_PKT_DATA;  in cn23xx_interrupt_handler()
861 		oct->int_status |= OCT_DEV_INTR_DMA0_FORCE;  in cn23xx_interrupt_handler()
863 		oct->int_status |= OCT_DEV_INTR_DMA1_FORCE;  in cn23xx_interrupt_handler()
871 static void cn23xx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr,  in cn23xx_bar1_idx_setup()  argument
879 			oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_setup()
881 		lio_pci_writeq(oct, (READ_ONCE(bar1) & 0xFFFFFFFEULL),  in cn23xx_bar1_idx_setup()
882 			       CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_setup()
884 			oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_setup()
892 	lio_pci_writeq(oct, (((core_addr >> 22) << 4) | PCI_BAR1_MASK),  in cn23xx_bar1_idx_setup()
893 		       CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_setup()
896 		   oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)));  in cn23xx_bar1_idx_setup()
899 static void cn23xx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask)  in cn23xx_bar1_idx_write()  argument
901 	lio_pci_writeq(oct, mask,  in cn23xx_bar1_idx_write()
902 		       CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_write()
905 static u32 cn23xx_bar1_idx_read(struct octeon_device *oct, u32 idx)  in cn23xx_bar1_idx_read()  argument
908 	    oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));  in cn23xx_bar1_idx_read()
932 static void cn23xx_enable_pf_interrupt(struct octeon_device *oct, u8 intr_flag)  in cn23xx_enable_pf_interrupt()  argument
934 	struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;  in cn23xx_enable_pf_interrupt()
946 		   (oct->sriov_info.max_vfs > 0)) {  in cn23xx_enable_pf_interrupt()
947 		if (oct->rev_id >= OCTEON_CN23XX_REV_1_1) {  in cn23xx_enable_pf_interrupt()
955 static void cn23xx_disable_pf_interrupt(struct octeon_device *oct, u8 intr_flag)  in cn23xx_disable_pf_interrupt()  argument
957 	struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;  in cn23xx_disable_pf_interrupt()
968 		   (oct->sriov_info.max_vfs > 0)) {  in cn23xx_disable_pf_interrupt()
969 		if (oct->rev_id >= OCTEON_CN23XX_REV_1_1) {  in cn23xx_disable_pf_interrupt()
977 static void cn23xx_get_pcie_qlmport(struct octeon_device *oct)  in cn23xx_get_pcie_qlmport()  argument
979 	oct->pcie_port = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff;  in cn23xx_get_pcie_qlmport()
981 	dev_dbg(&oct->pci_dev->dev, "OCTEON: CN23xx uses PCIE Port %d\n",  in cn23xx_get_pcie_qlmport()
982 		oct->pcie_port);  in cn23xx_get_pcie_qlmport()
985 static int cn23xx_get_pf_num(struct octeon_device *oct)  in cn23xx_get_pf_num()  argument
994 	if (pci_read_config_dword(oct->pci_dev, CN23XX_PCIE_SRIOV_FDL,  in cn23xx_get_pf_num()
996 		oct->pf_num = ((fdl_bit >> CN23XX_PCIE_SRIOV_FDL_BIT_POS) &  in cn23xx_get_pf_num()
1006 		pkt0_in_ctl = octeon_read_csr64(oct,  in cn23xx_get_pf_num()
1010 		mac = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff;  in cn23xx_get_pf_num()
1013 		d64 = octeon_read_csr64(oct,  in cn23xx_get_pf_num()
1017 			dev_err(&oct->pci_dev->dev,  in cn23xx_get_pf_num()
1020 			oct->pf_num = pfnum;  in cn23xx_get_pf_num()
1023 			dev_err(&oct->pci_dev->dev,  in cn23xx_get_pf_num()
1031 static void cn23xx_setup_reg_address(struct octeon_device *oct)  in cn23xx_setup_reg_address()  argument
1033 	u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr;  in cn23xx_setup_reg_address()
1034 	struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;  in cn23xx_setup_reg_address()
1036 	oct->reg_list.pci_win_wr_addr_hi =  in cn23xx_setup_reg_address()
1038 	oct->reg_list.pci_win_wr_addr_lo =  in cn23xx_setup_reg_address()
1040 	oct->reg_list.pci_win_wr_addr =  in cn23xx_setup_reg_address()
1043 	oct->reg_list.pci_win_rd_addr_hi =  in cn23xx_setup_reg_address()
1045 	oct->reg_list.pci_win_rd_addr_lo =  in cn23xx_setup_reg_address()
1047 	oct->reg_list.pci_win_rd_addr =  in cn23xx_setup_reg_address()
1050 	oct->reg_list.pci_win_wr_data_hi =  in cn23xx_setup_reg_address()
1052 	oct->reg_list.pci_win_wr_data_lo =  in cn23xx_setup_reg_address()
1054 	oct->reg_list.pci_win_wr_data =  in cn23xx_setup_reg_address()
1057 	oct->reg_list.pci_win_rd_data_hi =  in cn23xx_setup_reg_address()
1059 	oct->reg_list.pci_win_rd_data_lo =  in cn23xx_setup_reg_address()
1061 	oct->reg_list.pci_win_rd_data =  in cn23xx_setup_reg_address()
1064 	cn23xx_get_pcie_qlmport(oct);  in cn23xx_setup_reg_address()
1067 	if (!oct->msix_on)  in cn23xx_setup_reg_address()
1069 	if (oct->rev_id >= OCTEON_CN23XX_REV_1_1)  in cn23xx_setup_reg_address()
1074 	    CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);  in cn23xx_setup_reg_address()
1077 	    CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);  in cn23xx_setup_reg_address()
1080 int cn23xx_sriov_config(struct octeon_device *oct)  in cn23xx_sriov_config()  argument
1082 	struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;  in cn23xx_sriov_config()
1088 		(struct octeon_config *)oct_get_config_info(oct, LIO_23XX);  in cn23xx_sriov_config()
1089 	switch (oct->rev_id) {  in cn23xx_sriov_config()
1104 	if (oct->sriov_info.num_pf_rings)  in cn23xx_sriov_config()
1105 		num_pf_rings = oct->sriov_info.num_pf_rings;  in cn23xx_sriov_config()
1123 	oct->sriov_info.trs = total_rings;  in cn23xx_sriov_config()
1124 	oct->sriov_info.max_vfs = max_vfs;  in cn23xx_sriov_config()
1125 	oct->sriov_info.rings_per_vf = rings_per_vf;  in cn23xx_sriov_config()
1126 	oct->sriov_info.pf_srn = pf_srn;  in cn23xx_sriov_config()
1127 	oct->sriov_info.num_pf_rings = num_pf_rings;  in cn23xx_sriov_config()
1128 	dev_notice(&oct->pci_dev->dev, "trs:%d max_vfs:%d rings_per_vf:%d pf_srn:%d num_pf_rings:%d\n",  in cn23xx_sriov_config()
1129 		   oct->sriov_info.trs, oct->sriov_info.max_vfs,  in cn23xx_sriov_config()
1130 		   oct->sriov_info.rings_per_vf, oct->sriov_info.pf_srn,  in cn23xx_sriov_config()
1131 		   oct->sriov_info.num_pf_rings);  in cn23xx_sriov_config()
1133 	oct->sriov_info.sriov_enabled = 0;  in cn23xx_sriov_config()
1138 int setup_cn23xx_octeon_pf_device(struct octeon_device *oct)  in setup_cn23xx_octeon_pf_device()  argument
1143 	pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_0, &data32);  in setup_cn23xx_octeon_pf_device()
1145 	pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_1, &data32);  in setup_cn23xx_octeon_pf_device()
1147 	pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_2, &data32);  in setup_cn23xx_octeon_pf_device()
1149 	pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_3, &data32);  in setup_cn23xx_octeon_pf_device()
1154 			dev_err(&oct->pci_dev->dev, "device BAR0 unassigned\n");  in setup_cn23xx_octeon_pf_device()
1156 			dev_err(&oct->pci_dev->dev, "device BAR1 unassigned\n");  in setup_cn23xx_octeon_pf_device()
1160 	if (octeon_map_pci_barx(oct, 0, 0))  in setup_cn23xx_octeon_pf_device()
1163 	if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) {  in setup_cn23xx_octeon_pf_device()
1164 		dev_err(&oct->pci_dev->dev, "%s CN23XX BAR1 map failed\n",  in setup_cn23xx_octeon_pf_device()
1166 		octeon_unmap_pci_barx(oct, 0);  in setup_cn23xx_octeon_pf_device()
1170 	if (cn23xx_get_pf_num(oct) != 0)  in setup_cn23xx_octeon_pf_device()
1173 	if (cn23xx_sriov_config(oct)) {  in setup_cn23xx_octeon_pf_device()
1174 		octeon_unmap_pci_barx(oct, 0);  in setup_cn23xx_octeon_pf_device()
1175 		octeon_unmap_pci_barx(oct, 1);  in setup_cn23xx_octeon_pf_device()
1179 	octeon_write_csr64(oct, CN23XX_SLI_MAC_CREDIT_CNT, 0x3F802080802080ULL);  in setup_cn23xx_octeon_pf_device()
1181 	oct->fn_list.setup_iq_regs = cn23xx_setup_iq_regs;  in setup_cn23xx_octeon_pf_device()
1182 	oct->fn_list.setup_oq_regs = cn23xx_setup_oq_regs;  in setup_cn23xx_octeon_pf_device()
1183 	oct->fn_list.setup_mbox = cn23xx_setup_pf_mbox;  in setup_cn23xx_octeon_pf_device()
1184 	oct->fn_list.free_mbox = cn23xx_free_pf_mbox;  in setup_cn23xx_octeon_pf_device()
1186 	oct->fn_list.process_interrupt_regs = cn23xx_interrupt_handler;  in setup_cn23xx_octeon_pf_device()
1187 	oct->fn_list.msix_interrupt_handler = cn23xx_pf_msix_interrupt_handler;  in setup_cn23xx_octeon_pf_device()
1189 	oct->fn_list.soft_reset = cn23xx_pf_soft_reset;  in setup_cn23xx_octeon_pf_device()
1190 	oct->fn_list.setup_device_regs = cn23xx_setup_pf_device_regs;  in setup_cn23xx_octeon_pf_device()
1191 	oct->fn_list.update_iq_read_idx = cn23xx_update_read_index;  in setup_cn23xx_octeon_pf_device()
1193 	oct->fn_list.bar1_idx_setup = cn23xx_bar1_idx_setup;  in setup_cn23xx_octeon_pf_device()
1194 	oct->fn_list.bar1_idx_write = cn23xx_bar1_idx_write;  in setup_cn23xx_octeon_pf_device()
1195 	oct->fn_list.bar1_idx_read = cn23xx_bar1_idx_read;  in setup_cn23xx_octeon_pf_device()
1197 	oct->fn_list.enable_interrupt = cn23xx_enable_pf_interrupt;  in setup_cn23xx_octeon_pf_device()
1198 	oct->fn_list.disable_interrupt = cn23xx_disable_pf_interrupt;  in setup_cn23xx_octeon_pf_device()
1200 	oct->fn_list.enable_io_queues = cn23xx_enable_io_queues;  in setup_cn23xx_octeon_pf_device()
1201 	oct->fn_list.disable_io_queues = cn23xx_disable_io_queues;  in setup_cn23xx_octeon_pf_device()
1203 	cn23xx_setup_reg_address(oct);  in setup_cn23xx_octeon_pf_device()
1205 	oct->coproc_clock_rate = 1000000ULL * cn23xx_coprocessor_clock(oct);  in setup_cn23xx_octeon_pf_device()
1211 int validate_cn23xx_pf_config_info(struct octeon_device *oct,  in validate_cn23xx_pf_config_info()  argument
1215 		dev_err(&oct->pci_dev->dev, "%s: Num IQ (%d) exceeds Max (%d)\n",  in validate_cn23xx_pf_config_info()
1222 		dev_err(&oct->pci_dev->dev, "%s: Num OQ (%d) exceeds Max (%d)\n",  in validate_cn23xx_pf_config_info()
1230 		dev_err(&oct->pci_dev->dev, "%s: Invalid instr type for IQ\n",  in validate_cn23xx_pf_config_info()
1236 		dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n",  in validate_cn23xx_pf_config_info()
1242 		dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n",  in validate_cn23xx_pf_config_info()
1250 int cn23xx_fw_loaded(struct octeon_device *oct)  in cn23xx_fw_loaded()  argument
1262 	if (atomic_read(oct->adapter_refcount) > 1)  in cn23xx_fw_loaded()
1265 	val = octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2);  in cn23xx_fw_loaded()
1270 void cn23xx_tell_vf_its_macaddr_changed(struct octeon_device *oct, int vfidx,  in cn23xx_tell_vf_its_macaddr_changed()  argument
1273 	if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vfidx)) {  in cn23xx_tell_vf_its_macaddr_changed()
1286 		mbox_cmd.q_no = vfidx * oct->sriov_info.rings_per_vf;  in cn23xx_tell_vf_its_macaddr_changed()
1287 		octeon_mbox_write(oct, &mbox_cmd);  in cn23xx_tell_vf_its_macaddr_changed()
1293 cn23xx_get_vf_stats_callback(struct octeon_device *oct,  in cn23xx_get_vf_stats_callback()  argument
1302 int cn23xx_get_vf_stats(struct octeon_device *oct, int vfidx,  in cn23xx_get_vf_stats()  argument
1310 	if (!(oct->sriov_info.vf_drv_loaded_mask & (1ULL << vfidx)))  in cn23xx_get_vf_stats()
1321 	mbox_cmd.q_no = vfidx * oct->sriov_info.rings_per_vf;  in cn23xx_get_vf_stats()
1329 	octeon_mbox_write(oct, &mbox_cmd);  in cn23xx_get_vf_stats()
1337 		octeon_mbox_cancel(oct, 0);  in cn23xx_get_vf_stats()
1338 		dev_err(&oct->pci_dev->dev, "Unable to get stats from VF-%d, timedout\n",  in cn23xx_get_vf_stats()