Lines Matching +full:zynq +full:- +full:gpio +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
25 #include <linux/dma-mapping.h>
40 #include <linux/firmware/xlnx-zynqmp.h>
58 * (bp)->rx_ring_size)
64 * (bp)->tx_ring_size)
67 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
78 …define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX…
91 #define MACB_SERDES_RATE_10G 1
94 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
104 * 1. dma address width 32 bits:
105 * word 1: 32 bit address of Data Buffer
109 * word 1: 32 bit address of Data Buffer
115 * word 1: 32 bit address of Data Buffer
117 * word 3: timestamp word 1
121 * word 1: 32 bit address of Data Buffer
125 * word 5: timestamp word 1
133 switch (bp->hw_dma_cap) { in macb_dma_desc_get_size()
158 switch (bp->hw_dma_cap) { in macb_adj_dma_desc_idx()
161 desc_idx <<= 1; in macb_adj_dma_desc_idx()
184 return index & (bp->tx_ring_size - 1); in macb_tx_ring_wrap()
190 index = macb_tx_ring_wrap(queue->bp, index); in macb_tx_desc()
191 index = macb_adj_dma_desc_idx(queue->bp, index); in macb_tx_desc()
192 return &queue->tx_ring[index]; in macb_tx_desc()
198 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)]; in macb_tx_skb()
205 offset = macb_tx_ring_wrap(queue->bp, index) * in macb_tx_dma()
206 macb_dma_desc_get_size(queue->bp); in macb_tx_dma()
208 return queue->tx_ring_dma + offset; in macb_tx_dma()
213 return index & (bp->rx_ring_size - 1); in macb_rx_ring_wrap()
218 index = macb_rx_ring_wrap(queue->bp, index); in macb_rx_desc()
219 index = macb_adj_dma_desc_idx(queue->bp, index); in macb_rx_desc()
220 return &queue->rx_ring[index]; in macb_rx_desc()
225 return queue->rx_buffers + queue->bp->rx_buffer_size * in macb_rx_buffer()
226 macb_rx_ring_wrap(queue->bp, index); in macb_rx_buffer()
232 return __raw_readl(bp->regs + offset); in hw_readl_native()
237 __raw_writel(value, bp->regs + offset); in hw_writel_native()
242 return readl_relaxed(bp->regs + offset); in hw_readl()
247 writel_relaxed(value, bp->regs + offset); in hw_writel()
284 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); in macb_set_hwaddr()
286 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); in macb_set_hwaddr()
316 addr[1] = (bottom >> 8) & 0xff; in macb_get_hwaddr()
323 eth_hw_addr_set(bp->dev, addr); in macb_get_hwaddr()
328 dev_info(&bp->pdev->dev, "invalid hw address, using random\n"); in macb_get_hwaddr()
329 eth_hw_addr_random(bp->dev); in macb_get_hwaddr()
337 1, MACB_MDIO_TIMEOUT); in macb_mdio_wait_for_idle()
342 struct macb *bp = bus->priv; in macb_mdio_read_c22()
345 status = pm_runtime_resume_and_get(&bp->pdev->dev); in macb_mdio_read_c22()
366 pm_runtime_mark_last_busy(&bp->pdev->dev); in macb_mdio_read_c22()
367 pm_runtime_put_autosuspend(&bp->pdev->dev); in macb_mdio_read_c22()
375 struct macb *bp = bus->priv; in macb_mdio_read_c45()
378 status = pm_runtime_get_sync(&bp->pdev->dev); in macb_mdio_read_c45()
380 pm_runtime_put_noidle(&bp->pdev->dev); in macb_mdio_read_c45()
412 pm_runtime_mark_last_busy(&bp->pdev->dev); in macb_mdio_read_c45()
413 pm_runtime_put_autosuspend(&bp->pdev->dev); in macb_mdio_read_c45()
421 struct macb *bp = bus->priv; in macb_mdio_write_c22()
424 status = pm_runtime_resume_and_get(&bp->pdev->dev); in macb_mdio_write_c22()
444 pm_runtime_mark_last_busy(&bp->pdev->dev); in macb_mdio_write_c22()
445 pm_runtime_put_autosuspend(&bp->pdev->dev); in macb_mdio_write_c22()
454 struct macb *bp = bus->priv; in macb_mdio_write_c45()
457 status = pm_runtime_get_sync(&bp->pdev->dev); in macb_mdio_write_c45()
459 pm_runtime_put_noidle(&bp->pdev->dev); in macb_mdio_write_c45()
490 pm_runtime_mark_last_busy(&bp->pdev->dev); in macb_mdio_write_c45()
491 pm_runtime_put_autosuspend(&bp->pdev->dev); in macb_mdio_write_c45()
501 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in macb_init_buffers()
502 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma)); in macb_init_buffers()
504 if (bp->hw_dma_cap & HW_DMA_CAP_64B) in macb_init_buffers()
506 upper_32_bits(queue->rx_ring_dma)); in macb_init_buffers()
508 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); in macb_init_buffers()
510 if (bp->hw_dma_cap & HW_DMA_CAP_64B) in macb_init_buffers()
512 upper_32_bits(queue->tx_ring_dma)); in macb_init_buffers()
518 * macb_set_tx_clk() - Set a clock to a new frequency
526 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG)) in macb_set_tx_clk()
530 if (bp->phy_interface == PHY_INTERFACE_MODE_MII) in macb_set_tx_clk()
537 rate_rounded = clk_round_rate(bp->tx_clk, rate); in macb_set_tx_clk()
544 ferr = abs(rate_rounded - rate); in macb_set_tx_clk()
547 netdev_warn(bp->dev, in macb_set_tx_clk()
551 if (clk_set_rate(bp->tx_clk, rate_rounded)) in macb_set_tx_clk()
552 netdev_err(bp->dev, "adjusting tx_clk failed.\n"); in macb_set_tx_clk()
577 state->speed = SPEED_10000; in macb_usx_pcs_get_state()
578 state->duplex = 1; in macb_usx_pcs_get_state()
579 state->an_complete = 1; in macb_usx_pcs_get_state()
582 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK)); in macb_usx_pcs_get_state()
585 state->pause = MLO_PAUSE_RX; in macb_usx_pcs_get_state()
605 state->link = 0; in macb_pcs_get_state()
637 struct net_device *ndev = to_net_dev(config->dev); in macb_mac_config()
643 spin_lock_irqsave(&bp->lock, flags); in macb_mac_config()
648 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) { in macb_mac_config()
649 if (state->interface == PHY_INTERFACE_MODE_RMII) in macb_mac_config()
655 if (state->interface == PHY_INTERFACE_MODE_SGMII) { in macb_mac_config()
657 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) { in macb_mac_config()
660 } else if (bp->caps & MACB_CAPS_MIIONRGMII && in macb_mac_config()
661 bp->phy_interface == PHY_INTERFACE_MODE_MII) { in macb_mac_config()
677 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) { in macb_mac_config()
689 spin_unlock_irqrestore(&bp->lock, flags); in macb_mac_config()
695 struct net_device *ndev = to_net_dev(config->dev); in macb_mac_link_down()
701 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) in macb_mac_link_down()
702 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) in macb_mac_link_down()
704 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP)); in macb_mac_link_down()
719 struct net_device *ndev = to_net_dev(config->dev); in macb_mac_link_up()
726 spin_lock_irqsave(&bp->lock, flags); in macb_mac_link_up()
738 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) { in macb_mac_link_up()
753 bp->macbgem_ops.mog_init_rings(bp); in macb_mac_link_up()
756 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) in macb_mac_link_up()
758 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP)); in macb_mac_link_up()
763 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER) in macb_mac_link_up()
767 spin_unlock_irqrestore(&bp->lock, flags); in macb_mac_link_up()
769 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) in macb_mac_link_up()
785 struct net_device *ndev = to_net_dev(config->dev); in macb_mac_select_pcs()
789 return &bp->phylink_usx_pcs; in macb_mac_select_pcs()
791 return &bp->phylink_sgmii_pcs; in macb_mac_select_pcs()
805 dn = of_parse_phandle(dn, "phy-handle", 0); in macb_phy_handle_exists()
812 struct device_node *dn = bp->pdev->dev.of_node; in macb_phylink_connect()
813 struct net_device *dev = bp->dev; in macb_phylink_connect()
818 ret = phylink_of_phy_connect(bp->phylink, dn, 0); in macb_phylink_connect()
821 phydev = phy_find_first(bp->mii_bus); in macb_phylink_connect()
824 return -ENXIO; in macb_phylink_connect()
828 ret = phylink_connect_phy(bp->phylink, phydev); in macb_phylink_connect()
836 phylink_start(bp->phylink); in macb_phylink_connect()
844 struct net_device *ndev = to_net_dev(config->dev); in macb_get_pcs_fixed_state()
847 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0; in macb_get_pcs_fixed_state()
855 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops; in macb_mii_probe()
856 bp->phylink_sgmii_pcs.neg_mode = true; in macb_mii_probe()
857 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops; in macb_mii_probe()
858 bp->phylink_usx_pcs.neg_mode = true; in macb_mii_probe()
860 bp->phylink_config.dev = &dev->dev; in macb_mii_probe()
861 bp->phylink_config.type = PHYLINK_NETDEV; in macb_mii_probe()
862 bp->phylink_config.mac_managed_pm = true; in macb_mii_probe()
864 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { in macb_mii_probe()
865 bp->phylink_config.poll_fixed_state = true; in macb_mii_probe()
866 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state; in macb_mii_probe()
869 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | in macb_mii_probe()
873 bp->phylink_config.supported_interfaces); in macb_mii_probe()
875 bp->phylink_config.supported_interfaces); in macb_mii_probe()
878 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) { in macb_mii_probe()
879 bp->phylink_config.mac_capabilities |= MAC_1000FD; in macb_mii_probe()
880 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF)) in macb_mii_probe()
881 bp->phylink_config.mac_capabilities |= MAC_1000HD; in macb_mii_probe()
884 bp->phylink_config.supported_interfaces); in macb_mii_probe()
885 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces); in macb_mii_probe()
887 if (bp->caps & MACB_CAPS_PCS) in macb_mii_probe()
889 bp->phylink_config.supported_interfaces); in macb_mii_probe()
891 if (bp->caps & MACB_CAPS_HIGH_SPEED) { in macb_mii_probe()
893 bp->phylink_config.supported_interfaces); in macb_mii_probe()
894 bp->phylink_config.mac_capabilities |= MAC_10000FD; in macb_mii_probe()
898 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode, in macb_mii_probe()
899 bp->phy_interface, &macb_phylink_ops); in macb_mii_probe()
900 if (IS_ERR(bp->phylink)) { in macb_mii_probe()
902 PTR_ERR(bp->phylink)); in macb_mii_probe()
903 return PTR_ERR(bp->phylink); in macb_mii_probe()
911 struct device_node *child, *np = bp->pdev->dev.of_node; in macb_mdiobus_register()
917 return of_mdiobus_register(bp->mii_bus, mdio_np); in macb_mdiobus_register()
931 return of_mdiobus_register(bp->mii_bus, np); in macb_mdiobus_register()
934 return mdiobus_register(bp->mii_bus); in macb_mdiobus_register()
939 struct device_node *mdio_np, *np = bp->pdev->dev.of_node; in macb_mii_init()
940 int err = -ENXIO; in macb_mii_init()
942 /* With fixed-link, we don't need to register the MDIO bus, in macb_mii_init()
948 return macb_mii_probe(bp->dev); in macb_mii_init()
953 bp->mii_bus = mdiobus_alloc(); in macb_mii_init()
954 if (!bp->mii_bus) { in macb_mii_init()
955 err = -ENOMEM; in macb_mii_init()
959 bp->mii_bus->name = "MACB_mii_bus"; in macb_mii_init()
960 bp->mii_bus->read = &macb_mdio_read_c22; in macb_mii_init()
961 bp->mii_bus->write = &macb_mdio_write_c22; in macb_mii_init()
962 bp->mii_bus->read_c45 = &macb_mdio_read_c45; in macb_mii_init()
963 bp->mii_bus->write_c45 = &macb_mdio_write_c45; in macb_mii_init()
964 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", in macb_mii_init()
965 bp->pdev->name, bp->pdev->id); in macb_mii_init()
966 bp->mii_bus->priv = bp; in macb_mii_init()
967 bp->mii_bus->parent = &bp->pdev->dev; in macb_mii_init()
969 dev_set_drvdata(&bp->dev->dev, bp->mii_bus); in macb_mii_init()
975 err = macb_mii_probe(bp->dev); in macb_mii_init()
982 mdiobus_unregister(bp->mii_bus); in macb_mii_init()
984 mdiobus_free(bp->mii_bus); in macb_mii_init()
993 u32 *p = &bp->hw_stats.macb.rx_pause_frames; in macb_update_stats()
994 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1; in macb_update_stats()
997 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4); in macb_update_stats()
1000 *p += bp->macb_reg_readl(bp, offset); in macb_update_stats()
1020 return -ETIMEDOUT; in macb_halt_tx()
1025 if (tx_skb->mapping) { in macb_tx_unmap()
1026 if (tx_skb->mapped_as_page) in macb_tx_unmap()
1027 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping, in macb_tx_unmap()
1028 tx_skb->size, DMA_TO_DEVICE); in macb_tx_unmap()
1030 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, in macb_tx_unmap()
1031 tx_skb->size, DMA_TO_DEVICE); in macb_tx_unmap()
1032 tx_skb->mapping = 0; in macb_tx_unmap()
1035 if (tx_skb->skb) { in macb_tx_unmap()
1036 napi_consume_skb(tx_skb->skb, budget); in macb_tx_unmap()
1037 tx_skb->skb = NULL; in macb_tx_unmap()
1046 if (bp->hw_dma_cap & HW_DMA_CAP_64B) { in macb_set_addr()
1048 desc_64->addrh = upper_32_bits(addr); in macb_set_addr()
1056 desc->addr = lower_32_bits(addr); in macb_set_addr()
1065 if (bp->hw_dma_cap & HW_DMA_CAP_64B) { in macb_get_addr()
1067 addr = ((u64)(desc_64->addrh) << 32); in macb_get_addr()
1070 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); in macb_get_addr()
1072 if (bp->hw_dma_cap & HW_DMA_CAP_PTP) in macb_get_addr()
1083 struct macb *bp = queue->bp; in macb_tx_error_task()
1090 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n", in macb_tx_error_task()
1091 (unsigned int)(queue - bp->queues), in macb_tx_error_task()
1092 queue->tx_tail, queue->tx_head); in macb_tx_error_task()
1100 napi_disable(&queue->napi_tx); in macb_tx_error_task()
1101 spin_lock_irqsave(&bp->lock, flags); in macb_tx_error_task()
1104 netif_tx_stop_all_queues(bp->dev); in macb_tx_error_task()
1111 netdev_err(bp->dev, "BUG: halt tx timed out\n"); in macb_tx_error_task()
1119 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) { in macb_tx_error_task()
1123 ctrl = desc->ctrl; in macb_tx_error_task()
1125 skb = tx_skb->skb; in macb_tx_error_task()
1133 skb = tx_skb->skb; in macb_tx_error_task()
1140 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n", in macb_tx_error_task()
1142 skb->data); in macb_tx_error_task()
1143 bp->dev->stats.tx_packets++; in macb_tx_error_task()
1144 queue->stats.tx_packets++; in macb_tx_error_task()
1145 bp->dev->stats.tx_bytes += skb->len; in macb_tx_error_task()
1146 queue->stats.tx_bytes += skb->len; in macb_tx_error_task()
1149 /* "Buffers exhausted mid-frame" errors may only happen in macb_tx_error_task()
1154 netdev_err(bp->dev, in macb_tx_error_task()
1155 "BUG: TX buffers exhausted mid-frame\n"); in macb_tx_error_task()
1157 desc->ctrl = ctrl | MACB_BIT(TX_USED); in macb_tx_error_task()
1166 desc->ctrl = MACB_BIT(TX_USED); in macb_tx_error_task()
1172 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma)); in macb_tx_error_task()
1174 if (bp->hw_dma_cap & HW_DMA_CAP_64B) in macb_tx_error_task()
1175 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma)); in macb_tx_error_task()
1178 queue->tx_head = 0; in macb_tx_error_task()
1179 queue->tx_tail = 0; in macb_tx_error_task()
1189 netif_tx_start_all_queues(bp->dev); in macb_tx_error_task()
1192 spin_unlock_irqrestore(&bp->lock, flags); in macb_tx_error_task()
1193 napi_enable(&queue->napi_tx); in macb_tx_error_task()
1203 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) in ptp_one_step_sync()
1215 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP) in ptp_one_step_sync()
1228 struct macb *bp = queue->bp; in macb_tx_complete()
1229 u16 queue_index = queue - bp->queues; in macb_tx_complete()
1234 spin_lock(&queue->tx_ptr_lock); in macb_tx_complete()
1235 head = queue->tx_head; in macb_tx_complete()
1236 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) { in macb_tx_complete()
1247 ctrl = desc->ctrl; in macb_tx_complete()
1258 skb = tx_skb->skb; in macb_tx_complete()
1262 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && in macb_tx_complete()
1266 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n", in macb_tx_complete()
1268 skb->data); in macb_tx_complete()
1269 bp->dev->stats.tx_packets++; in macb_tx_complete()
1270 queue->stats.tx_packets++; in macb_tx_complete()
1271 bp->dev->stats.tx_bytes += skb->len; in macb_tx_complete()
1272 queue->stats.tx_bytes += skb->len; in macb_tx_complete()
1288 queue->tx_tail = tail; in macb_tx_complete()
1289 if (__netif_subqueue_stopped(bp->dev, queue_index) && in macb_tx_complete()
1290 CIRC_CNT(queue->tx_head, queue->tx_tail, in macb_tx_complete()
1291 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp)) in macb_tx_complete()
1292 netif_wake_subqueue(bp->dev, queue_index); in macb_tx_complete()
1293 spin_unlock(&queue->tx_ptr_lock); in macb_tx_complete()
1303 struct macb *bp = queue->bp; in gem_rx_refill()
1306 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail, in gem_rx_refill()
1307 bp->rx_ring_size) > 0) { in gem_rx_refill()
1308 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head); in gem_rx_refill()
1315 if (!queue->rx_skbuff[entry]) { in gem_rx_refill()
1317 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size); in gem_rx_refill()
1319 netdev_err(bp->dev, in gem_rx_refill()
1325 paddr = dma_map_single(&bp->pdev->dev, skb->data, in gem_rx_refill()
1326 bp->rx_buffer_size, in gem_rx_refill()
1328 if (dma_mapping_error(&bp->pdev->dev, paddr)) { in gem_rx_refill()
1333 queue->rx_skbuff[entry] = skb; in gem_rx_refill()
1335 if (entry == bp->rx_ring_size - 1) in gem_rx_refill()
1337 desc->ctrl = 0; in gem_rx_refill()
1347 desc->ctrl = 0; in gem_rx_refill()
1349 desc->addr &= ~MACB_BIT(RX_USED); in gem_rx_refill()
1351 queue->rx_prepared_head++; in gem_rx_refill()
1357 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n", in gem_rx_refill()
1358 queue, queue->rx_prepared_head, queue->rx_tail); in gem_rx_refill()
1370 desc->addr &= ~MACB_BIT(RX_USED); in discard_partial_frame()
1385 struct macb *bp = queue->bp; in gem_rx()
1397 entry = macb_rx_ring_wrap(bp, queue->rx_tail); in gem_rx()
1403 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false; in gem_rx()
1409 /* Ensure ctrl is at least as up-to-date as rxused */ in gem_rx()
1412 ctrl = desc->ctrl; in gem_rx()
1414 queue->rx_tail++; in gem_rx()
1418 netdev_err(bp->dev, in gem_rx()
1420 bp->dev->stats.rx_dropped++; in gem_rx()
1421 queue->stats.rx_dropped++; in gem_rx()
1424 skb = queue->rx_skbuff[entry]; in gem_rx()
1426 netdev_err(bp->dev, in gem_rx()
1428 bp->dev->stats.rx_dropped++; in gem_rx()
1429 queue->stats.rx_dropped++; in gem_rx()
1433 queue->rx_skbuff[entry] = NULL; in gem_rx()
1434 len = ctrl & bp->rx_frm_len_mask; in gem_rx()
1436 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len); in gem_rx()
1439 dma_unmap_single(&bp->pdev->dev, addr, in gem_rx()
1440 bp->rx_buffer_size, DMA_FROM_DEVICE); in gem_rx()
1442 skb->protocol = eth_type_trans(skb, bp->dev); in gem_rx()
1444 if (bp->dev->features & NETIF_F_RXCSUM && in gem_rx()
1445 !(bp->dev->flags & IFF_PROMISC) && in gem_rx()
1447 skb->ip_summed = CHECKSUM_UNNECESSARY; in gem_rx()
1449 bp->dev->stats.rx_packets++; in gem_rx()
1450 queue->stats.rx_packets++; in gem_rx()
1451 bp->dev->stats.rx_bytes += skb->len; in gem_rx()
1452 queue->stats.rx_bytes += skb->len; in gem_rx()
1457 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", in gem_rx()
1458 skb->len, skb->csum); in gem_rx()
1459 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1, in gem_rx()
1461 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1, in gem_rx()
1462 skb->data, 32, true); in gem_rx()
1481 struct macb *bp = queue->bp; in macb_rx_frame()
1484 len = desc->ctrl & bp->rx_frm_len_mask; in macb_rx_frame()
1486 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n", in macb_rx_frame()
1492 * payload word-aligned. in macb_rx_frame()
1498 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN); in macb_rx_frame()
1500 bp->dev->stats.rx_dropped++; in macb_rx_frame()
1503 desc->addr &= ~MACB_BIT(RX_USED); in macb_rx_frame()
1511 return 1; in macb_rx_frame()
1520 unsigned int frag_len = bp->rx_buffer_size; in macb_rx_frame()
1525 return -1; in macb_rx_frame()
1527 frag_len = len - offset; in macb_rx_frame()
1532 offset += bp->rx_buffer_size; in macb_rx_frame()
1534 desc->addr &= ~MACB_BIT(RX_USED); in macb_rx_frame()
1544 skb->protocol = eth_type_trans(skb, bp->dev); in macb_rx_frame()
1546 bp->dev->stats.rx_packets++; in macb_rx_frame()
1547 bp->dev->stats.rx_bytes += skb->len; in macb_rx_frame()
1548 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n", in macb_rx_frame()
1549 skb->len, skb->csum); in macb_rx_frame()
1557 struct macb *bp = queue->bp; in macb_init_rx_ring()
1562 addr = queue->rx_buffers_dma; in macb_init_rx_ring()
1563 for (i = 0; i < bp->rx_ring_size; i++) { in macb_init_rx_ring()
1566 desc->ctrl = 0; in macb_init_rx_ring()
1567 addr += bp->rx_buffer_size; in macb_init_rx_ring()
1569 desc->addr |= MACB_BIT(RX_WRAP); in macb_init_rx_ring()
1570 queue->rx_tail = 0; in macb_init_rx_ring()
1576 struct macb *bp = queue->bp; in macb_rx()
1580 int first_frag = -1; in macb_rx()
1582 for (tail = queue->rx_tail; budget > 0; tail++) { in macb_rx()
1589 if (!(desc->addr & MACB_BIT(RX_USED))) in macb_rx()
1592 /* Ensure ctrl is at least as up-to-date as addr */ in macb_rx()
1595 ctrl = desc->ctrl; in macb_rx()
1598 if (first_frag != -1) in macb_rx()
1606 if (unlikely(first_frag == -1)) { in macb_rx()
1612 first_frag = -1; in macb_rx()
1619 budget--; in macb_rx()
1628 netdev_err(bp->dev, "RX queue corruption: reset it\n"); in macb_rx()
1630 spin_lock_irqsave(&bp->lock, flags); in macb_rx()
1636 queue_writel(queue, RBQP, queue->rx_ring_dma); in macb_rx()
1640 spin_unlock_irqrestore(&bp->lock, flags); in macb_rx()
1644 if (first_frag != -1) in macb_rx()
1645 queue->rx_tail = first_frag; in macb_rx()
1647 queue->rx_tail = tail; in macb_rx()
1654 struct macb *bp = queue->bp; in macb_rx_pending()
1658 entry = macb_rx_ring_wrap(bp, queue->rx_tail); in macb_rx_pending()
1664 return (desc->addr & MACB_BIT(RX_USED)) != 0; in macb_rx_pending()
1670 struct macb *bp = queue->bp; in macb_rx_poll()
1673 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget); in macb_rx_poll()
1675 netdev_vdbg(bp->dev, "RX poll: queue = %u, work_done = %d, budget = %d\n", in macb_rx_poll()
1676 (unsigned int)(queue - bp->queues), work_done, budget); in macb_rx_poll()
1679 queue_writel(queue, IER, bp->rx_intr_mask); in macb_rx_poll()
1685 * interrupts are re-enabled. in macb_rx_poll()
1692 queue_writel(queue, IDR, bp->rx_intr_mask); in macb_rx_poll()
1693 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_rx_poll()
1695 netdev_vdbg(bp->dev, "poll: packets pending, reschedule\n"); in macb_rx_poll()
1707 struct macb *bp = queue->bp; in macb_tx_restart()
1710 spin_lock(&queue->tx_ptr_lock); in macb_tx_restart()
1712 if (queue->tx_head == queue->tx_tail) in macb_tx_restart()
1717 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head)); in macb_tx_restart()
1722 spin_lock_irq(&bp->lock); in macb_tx_restart()
1724 spin_unlock_irq(&bp->lock); in macb_tx_restart()
1727 spin_unlock(&queue->tx_ptr_lock); in macb_tx_restart()
1734 spin_lock(&queue->tx_ptr_lock); in macb_tx_complete_pending()
1735 if (queue->tx_head != queue->tx_tail) { in macb_tx_complete_pending()
1739 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED)) in macb_tx_complete_pending()
1742 spin_unlock(&queue->tx_ptr_lock); in macb_tx_complete_pending()
1749 struct macb *bp = queue->bp; in macb_tx_poll()
1755 if (queue->txubr_pending) { in macb_tx_poll()
1756 queue->txubr_pending = false; in macb_tx_poll()
1757 netdev_vdbg(bp->dev, "poll: tx restart\n"); in macb_tx_poll()
1761 netdev_vdbg(bp->dev, "TX poll: queue = %u, work_done = %d, budget = %d\n", in macb_tx_poll()
1762 (unsigned int)(queue - bp->queues), work_done, budget); in macb_tx_poll()
1771 * interrupts are re-enabled. in macb_tx_poll()
1779 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_tx_poll()
1781 netdev_vdbg(bp->dev, "TX poll: packets pending, reschedule\n"); in macb_tx_poll()
1792 struct net_device *dev = bp->dev; in macb_hresp_error_task()
1797 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in macb_hresp_error_task()
1798 queue_writel(queue, IDR, bp->rx_intr_mask | in macb_hresp_error_task()
1809 bp->macbgem_ops.mog_init_rings(bp); in macb_hresp_error_task()
1815 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) in macb_hresp_error_task()
1817 bp->rx_intr_mask | in macb_hresp_error_task()
1831 struct macb *bp = queue->bp; in macb_wol_interrupt()
1839 spin_lock(&bp->lock); in macb_wol_interrupt()
1844 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n", in macb_wol_interrupt()
1845 (unsigned int)(queue - bp->queues), in macb_wol_interrupt()
1847 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_wol_interrupt()
1849 pm_wakeup_event(&bp->pdev->dev, 0); in macb_wol_interrupt()
1852 spin_unlock(&bp->lock); in macb_wol_interrupt()
1860 struct macb *bp = queue->bp; in gem_wol_interrupt()
1868 spin_lock(&bp->lock); in gem_wol_interrupt()
1873 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n", in gem_wol_interrupt()
1874 (unsigned int)(queue - bp->queues), in gem_wol_interrupt()
1876 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in gem_wol_interrupt()
1878 pm_wakeup_event(&bp->pdev->dev, 0); in gem_wol_interrupt()
1881 spin_unlock(&bp->lock); in gem_wol_interrupt()
1889 struct macb *bp = queue->bp; in macb_interrupt()
1890 struct net_device *dev = bp->dev; in macb_interrupt()
1898 spin_lock(&bp->lock); in macb_interrupt()
1903 queue_writel(queue, IDR, -1); in macb_interrupt()
1904 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_interrupt()
1905 queue_writel(queue, ISR, -1); in macb_interrupt()
1909 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n", in macb_interrupt()
1910 (unsigned int)(queue - bp->queues), in macb_interrupt()
1913 if (status & bp->rx_intr_mask) { in macb_interrupt()
1920 queue_writel(queue, IDR, bp->rx_intr_mask); in macb_interrupt()
1921 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_interrupt()
1924 if (napi_schedule_prep(&queue->napi_rx)) { in macb_interrupt()
1925 netdev_vdbg(bp->dev, "scheduling RX softirq\n"); in macb_interrupt()
1926 __napi_schedule(&queue->napi_rx); in macb_interrupt()
1933 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_interrupt()
1938 queue->txubr_pending = true; in macb_interrupt()
1942 if (napi_schedule_prep(&queue->napi_tx)) { in macb_interrupt()
1943 netdev_vdbg(bp->dev, "scheduling TX softirq\n"); in macb_interrupt()
1944 __napi_schedule(&queue->napi_tx); in macb_interrupt()
1950 schedule_work(&queue->tx_error_task); in macb_interrupt()
1952 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_interrupt()
1959 * add that if/when we get our hands on a full-blown MII PHY. in macb_interrupt()
1964 * interrupts but it can be cleared by re-enabling RX. See in macb_interrupt()
1965 * the at91rm9200 manual, section 41.3.1 or the Zynq manual in macb_interrupt()
1975 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_interrupt()
1981 spin_lock(&bp->stats_lock); in macb_interrupt()
1983 bp->hw_stats.gem.rx_overruns++; in macb_interrupt()
1985 bp->hw_stats.macb.rx_overruns++; in macb_interrupt()
1986 spin_unlock(&bp->stats_lock); in macb_interrupt()
1988 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_interrupt()
1993 queue_work(system_bh_wq, &bp->hresp_err_bh_work); in macb_interrupt()
1996 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_interrupt()
2002 spin_unlock(&bp->lock); in macb_interrupt()
2008 /* Polling receive - used by netconsole and other diagnostic tools
2019 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) in macb_poll_controller()
2020 macb_interrupt(dev->irq, queue); in macb_poll_controller()
2031 unsigned int len, entry, i, tx_head = queue->tx_head; in macb_tx_map()
2035 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags; in macb_tx_map()
2036 unsigned int eof = 1, mss_mfs = 0; in macb_tx_map()
2040 if (skb_shinfo(skb)->gso_size != 0) { in macb_tx_map()
2041 if (ip_hdr(skb)->protocol == IPPROTO_UDP) in macb_tx_map()
2042 /* UDP - UFO */ in macb_tx_map()
2045 /* TCP - TSO */ in macb_tx_map()
2049 /* First, map non-paged data */ in macb_tx_map()
2058 tx_skb = &queue->tx_skb[entry]; in macb_tx_map()
2060 mapping = dma_map_single(&bp->pdev->dev, in macb_tx_map()
2061 skb->data + offset, in macb_tx_map()
2063 if (dma_mapping_error(&bp->pdev->dev, mapping)) in macb_tx_map()
2067 tx_skb->skb = NULL; in macb_tx_map()
2068 tx_skb->mapping = mapping; in macb_tx_map()
2069 tx_skb->size = size; in macb_tx_map()
2070 tx_skb->mapped_as_page = false; in macb_tx_map()
2072 len -= size; in macb_tx_map()
2077 size = min(len, bp->max_tx_length); in macb_tx_map()
2082 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; in macb_tx_map()
2087 size = min(len, bp->max_tx_length); in macb_tx_map()
2089 tx_skb = &queue->tx_skb[entry]; in macb_tx_map()
2091 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, in macb_tx_map()
2093 if (dma_mapping_error(&bp->pdev->dev, mapping)) in macb_tx_map()
2097 tx_skb->skb = NULL; in macb_tx_map()
2098 tx_skb->mapping = mapping; in macb_tx_map()
2099 tx_skb->size = size; in macb_tx_map()
2100 tx_skb->mapped_as_page = true; in macb_tx_map()
2102 len -= size; in macb_tx_map()
2111 netdev_err(bp->dev, "BUG! empty skb!\n"); in macb_tx_map()
2116 tx_skb->skb = skb; in macb_tx_map()
2129 desc->ctrl = ctrl; in macb_tx_map()
2134 mss_mfs = skb_shinfo(skb)->gso_size + in macb_tx_map()
2138 mss_mfs = skb_shinfo(skb)->gso_size; in macb_tx_map()
2147 i--; in macb_tx_map()
2149 tx_skb = &queue->tx_skb[entry]; in macb_tx_map()
2152 ctrl = (u32)tx_skb->size; in macb_tx_map()
2157 if (unlikely(entry == (bp->tx_ring_size - 1))) in macb_tx_map()
2161 if (i == queue->tx_head) { in macb_tx_map()
2164 if ((bp->dev->features & NETIF_F_HW_CSUM) && in macb_tx_map()
2165 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl && in macb_tx_map()
2175 macb_set_addr(bp, desc, tx_skb->mapping); in macb_tx_map()
2176 /* desc->addr must be visible to hardware before clearing in macb_tx_map()
2177 * 'TX_USED' bit in desc->ctrl. in macb_tx_map()
2180 desc->ctrl = ctrl; in macb_tx_map()
2181 } while (i != queue->tx_head); in macb_tx_map()
2183 queue->tx_head = tx_head; in macb_tx_map()
2188 netdev_err(bp->dev, "TX DMA map failed\n"); in macb_tx_map()
2190 for (i = queue->tx_head; i != tx_head; i++) { in macb_tx_map()
2209 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP)) in macb_features_check()
2219 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN)) in macb_features_check()
2222 nr_frags = skb_shinfo(skb)->nr_frags; in macb_features_check()
2224 nr_frags--; in macb_features_check()
2226 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; in macb_features_check()
2237 if (skb->ip_summed != CHECKSUM_PARTIAL) in macb_clear_csum()
2242 return -1; in macb_clear_csum()
2245 * This is required - at least for Zynq, which otherwise calculates in macb_clear_csum()
2248 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0; in macb_clear_csum()
2256 int padlen = ETH_ZLEN - (*skb)->len; in macb_pad_and_fcs()
2261 if (!(ndev->features & NETIF_F_HW_CSUM) || in macb_pad_and_fcs()
2262 !((*skb)->ip_summed != CHECKSUM_PARTIAL) || in macb_pad_and_fcs()
2263 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb)) in macb_pad_and_fcs()
2281 return -ENOMEM; in macb_pad_and_fcs()
2288 skb_put_zero(*skb, padlen - ETH_FCS_LEN); in macb_pad_and_fcs()
2292 fcs = crc32_le(~0, (*skb)->data, (*skb)->len); in macb_pad_and_fcs()
2307 struct macb_queue *queue = &bp->queues[queue_index]; in macb_start_xmit()
2324 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && in macb_start_xmit()
2325 (bp->hw_dma_cap & HW_DMA_CAP_PTP)) in macb_start_xmit()
2326 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in macb_start_xmit()
2329 is_lso = (skb_shinfo(skb)->gso_size != 0); in macb_start_xmit()
2333 if (ip_hdr(skb)->protocol == IPPROTO_UDP) in macb_start_xmit()
2339 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n"); in macb_start_xmit()
2344 hdrlen = min(skb_headlen(skb), bp->max_tx_length); in macb_start_xmit()
2347 netdev_vdbg(bp->dev, in macb_start_xmit()
2349 queue_index, skb->len, skb->head, skb->data, in macb_start_xmit()
2351 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1, in macb_start_xmit()
2352 skb->data, 16, true); in macb_start_xmit()
2361 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1; in macb_start_xmit()
2363 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length); in macb_start_xmit()
2364 nr_frags = skb_shinfo(skb)->nr_frags; in macb_start_xmit()
2366 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]); in macb_start_xmit()
2367 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length); in macb_start_xmit()
2370 spin_lock_bh(&queue->tx_ptr_lock); in macb_start_xmit()
2373 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, in macb_start_xmit()
2374 bp->tx_ring_size) < desc_cnt) { in macb_start_xmit()
2376 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n", in macb_start_xmit()
2377 queue->tx_head, queue->tx_tail); in macb_start_xmit()
2392 spin_lock_irq(&bp->lock); in macb_start_xmit()
2394 spin_unlock_irq(&bp->lock); in macb_start_xmit()
2396 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1) in macb_start_xmit()
2400 spin_unlock_bh(&queue->tx_ptr_lock); in macb_start_xmit()
2408 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE; in macb_init_rx_buffer_size()
2410 bp->rx_buffer_size = size; in macb_init_rx_buffer_size()
2412 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) { in macb_init_rx_buffer_size()
2413 netdev_dbg(bp->dev, in macb_init_rx_buffer_size()
2416 bp->rx_buffer_size = in macb_init_rx_buffer_size()
2417 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE); in macb_init_rx_buffer_size()
2421 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n", in macb_init_rx_buffer_size()
2422 bp->dev->mtu, bp->rx_buffer_size); in macb_init_rx_buffer_size()
2434 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in gem_free_rx_buffers()
2435 if (!queue->rx_skbuff) in gem_free_rx_buffers()
2438 for (i = 0; i < bp->rx_ring_size; i++) { in gem_free_rx_buffers()
2439 skb = queue->rx_skbuff[i]; in gem_free_rx_buffers()
2447 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size, in gem_free_rx_buffers()
2453 kfree(queue->rx_skbuff); in gem_free_rx_buffers()
2454 queue->rx_skbuff = NULL; in gem_free_rx_buffers()
2460 struct macb_queue *queue = &bp->queues[0]; in macb_free_rx_buffers()
2462 if (queue->rx_buffers) { in macb_free_rx_buffers()
2463 dma_free_coherent(&bp->pdev->dev, in macb_free_rx_buffers()
2464 bp->rx_ring_size * bp->rx_buffer_size, in macb_free_rx_buffers()
2465 queue->rx_buffers, queue->rx_buffers_dma); in macb_free_rx_buffers()
2466 queue->rx_buffers = NULL; in macb_free_rx_buffers()
2476 if (bp->rx_ring_tieoff) { in macb_free_consistent()
2477 dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp), in macb_free_consistent()
2478 bp->rx_ring_tieoff, bp->rx_ring_tieoff_dma); in macb_free_consistent()
2479 bp->rx_ring_tieoff = NULL; in macb_free_consistent()
2482 bp->macbgem_ops.mog_free_rx_buffers(bp); in macb_free_consistent()
2484 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in macb_free_consistent()
2485 kfree(queue->tx_skb); in macb_free_consistent()
2486 queue->tx_skb = NULL; in macb_free_consistent()
2487 if (queue->tx_ring) { in macb_free_consistent()
2488 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch; in macb_free_consistent()
2489 dma_free_coherent(&bp->pdev->dev, size, in macb_free_consistent()
2490 queue->tx_ring, queue->tx_ring_dma); in macb_free_consistent()
2491 queue->tx_ring = NULL; in macb_free_consistent()
2493 if (queue->rx_ring) { in macb_free_consistent()
2494 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; in macb_free_consistent()
2495 dma_free_coherent(&bp->pdev->dev, size, in macb_free_consistent()
2496 queue->rx_ring, queue->rx_ring_dma); in macb_free_consistent()
2497 queue->rx_ring = NULL; in macb_free_consistent()
2508 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in gem_alloc_rx_buffers()
2509 size = bp->rx_ring_size * sizeof(struct sk_buff *); in gem_alloc_rx_buffers()
2510 queue->rx_skbuff = kzalloc(size, GFP_KERNEL); in gem_alloc_rx_buffers()
2511 if (!queue->rx_skbuff) in gem_alloc_rx_buffers()
2512 return -ENOMEM; in gem_alloc_rx_buffers()
2514 netdev_dbg(bp->dev, in gem_alloc_rx_buffers()
2516 bp->rx_ring_size, queue->rx_skbuff); in gem_alloc_rx_buffers()
2523 struct macb_queue *queue = &bp->queues[0]; in macb_alloc_rx_buffers()
2526 size = bp->rx_ring_size * bp->rx_buffer_size; in macb_alloc_rx_buffers()
2527 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size, in macb_alloc_rx_buffers()
2528 &queue->rx_buffers_dma, GFP_KERNEL); in macb_alloc_rx_buffers()
2529 if (!queue->rx_buffers) in macb_alloc_rx_buffers()
2530 return -ENOMEM; in macb_alloc_rx_buffers()
2532 netdev_dbg(bp->dev, in macb_alloc_rx_buffers()
2534 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers); in macb_alloc_rx_buffers()
2544 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in macb_alloc_consistent()
2545 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch; in macb_alloc_consistent()
2546 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size, in macb_alloc_consistent()
2547 &queue->tx_ring_dma, in macb_alloc_consistent()
2549 if (!queue->tx_ring) in macb_alloc_consistent()
2551 netdev_dbg(bp->dev, in macb_alloc_consistent()
2553 q, size, (unsigned long)queue->tx_ring_dma, in macb_alloc_consistent()
2554 queue->tx_ring); in macb_alloc_consistent()
2556 size = bp->tx_ring_size * sizeof(struct macb_tx_skb); in macb_alloc_consistent()
2557 queue->tx_skb = kmalloc(size, GFP_KERNEL); in macb_alloc_consistent()
2558 if (!queue->tx_skb) in macb_alloc_consistent()
2561 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch; in macb_alloc_consistent()
2562 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size, in macb_alloc_consistent()
2563 &queue->rx_ring_dma, GFP_KERNEL); in macb_alloc_consistent()
2564 if (!queue->rx_ring) in macb_alloc_consistent()
2566 netdev_dbg(bp->dev, in macb_alloc_consistent()
2568 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring); in macb_alloc_consistent()
2570 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp)) in macb_alloc_consistent()
2574 if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) { in macb_alloc_consistent()
2575 bp->rx_ring_tieoff = dma_alloc_coherent(&bp->pdev->dev, in macb_alloc_consistent()
2577 &bp->rx_ring_tieoff_dma, in macb_alloc_consistent()
2579 if (!bp->rx_ring_tieoff) in macb_alloc_consistent()
2587 return -ENOMEM; in macb_alloc_consistent()
2592 struct macb_dma_desc *desc = bp->rx_ring_tieoff; in macb_init_tieoff()
2594 if (bp->caps & MACB_CAPS_QUEUE_DISABLE) in macb_init_tieoff()
2600 desc->ctrl = 0; in macb_init_tieoff()
2610 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in gem_init_rings()
2611 for (i = 0; i < bp->tx_ring_size; i++) { in gem_init_rings()
2614 desc->ctrl = MACB_BIT(TX_USED); in gem_init_rings()
2616 desc->ctrl |= MACB_BIT(TX_WRAP); in gem_init_rings()
2617 queue->tx_head = 0; in gem_init_rings()
2618 queue->tx_tail = 0; in gem_init_rings()
2620 queue->rx_tail = 0; in gem_init_rings()
2621 queue->rx_prepared_head = 0; in gem_init_rings()
2634 macb_init_rx_ring(&bp->queues[0]); in macb_init_rings()
2636 for (i = 0; i < bp->tx_ring_size; i++) { in macb_init_rings()
2637 desc = macb_tx_desc(&bp->queues[0], i); in macb_init_rings()
2639 desc->ctrl = MACB_BIT(TX_USED); in macb_init_rings()
2641 bp->queues[0].tx_head = 0; in macb_init_rings()
2642 bp->queues[0].tx_tail = 0; in macb_init_rings()
2643 desc->ctrl |= MACB_BIT(TX_WRAP); in macb_init_rings()
2665 macb_writel(bp, TSR, -1); in macb_reset_hw()
2666 macb_writel(bp, RSR, -1); in macb_reset_hw()
2672 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in macb_reset_hw()
2673 queue_writel(queue, IDR, -1); in macb_reset_hw()
2675 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_reset_hw()
2676 queue_writel(queue, ISR, -1); in macb_reset_hw()
2683 unsigned long pclk_hz = clk_get_rate(bp->pclk); in gem_mdc_clk_div()
2713 pclk_hz = clk_get_rate(bp->pclk); in macb_mdc_clk_div()
2740 case 1: in macb_dbw()
2747 * - use the correct receive buffer size
2748 * - set best burst length for DMA operations
2750 * - set both rx/tx packet buffers to full memory size
2760 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE; in macb_configure_dma()
2762 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L); in macb_configure_dma()
2763 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in macb_configure_dma()
2769 if (bp->dma_burst_length) in macb_configure_dma()
2770 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg); in macb_configure_dma()
2771 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); in macb_configure_dma()
2774 if (bp->native_io) in macb_configure_dma()
2779 if (bp->dev->features & NETIF_F_HW_CSUM) in macb_configure_dma()
2786 if (bp->hw_dma_cap & HW_DMA_CAP_64B) in macb_configure_dma()
2790 if (bp->hw_dma_cap & HW_DMA_CAP_PTP) in macb_configure_dma()
2793 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n", in macb_configure_dma()
2809 if (bp->caps & MACB_CAPS_JUMBO) in macb_init_hw()
2813 if (bp->dev->flags & IFF_PROMISC) in macb_init_hw()
2815 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM) in macb_init_hw()
2817 if (!(bp->dev->flags & IFF_BROADCAST)) in macb_init_hw()
2821 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len) in macb_init_hw()
2822 gem_writel(bp, JML, bp->jumbo_max_len); in macb_init_hw()
2823 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK; in macb_init_hw()
2824 if (bp->caps & MACB_CAPS_JUMBO) in macb_init_hw()
2825 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK; in macb_init_hw()
2830 if (bp->rx_watermark) in macb_init_hw()
2831 gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU))); in macb_init_hw()
2849 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2858 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2869 if (addr[bitnr / 8] & (1 << (bitnr % 8))) in hash_bit_value()
2870 return 1; in hash_bit_value()
2890 /* Add multicast addresses to the internal multicast-hash table. */
2899 mc_filter[1] = 0; in macb_sethashtable()
2902 bitnr = hash_get_index(ha->addr); in macb_sethashtable()
2903 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31); in macb_sethashtable()
2907 macb_or_gem_writel(bp, HRT, mc_filter[1]); in macb_sethashtable()
2918 if (dev->flags & IFF_PROMISC) { in macb_set_rx_mode()
2930 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM) in macb_set_rx_mode()
2934 if (dev->flags & IFF_ALLMULTI) { in macb_set_rx_mode()
2936 macb_or_gem_writel(bp, HRB, -1); in macb_set_rx_mode()
2937 macb_or_gem_writel(bp, HRT, -1); in macb_set_rx_mode()
2943 } else if (dev->flags & (~IFF_ALLMULTI)) { in macb_set_rx_mode()
2955 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN; in macb_open()
2961 netdev_dbg(bp->dev, "open\n"); in macb_open()
2963 err = pm_runtime_resume_and_get(&bp->pdev->dev); in macb_open()
2977 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in macb_open()
2978 napi_enable(&queue->napi_rx); in macb_open()
2979 napi_enable(&queue->napi_tx); in macb_open()
2984 err = phy_power_on(bp->sgmii_phy); in macb_open()
2994 if (bp->ptp_info) in macb_open()
2995 bp->ptp_info->ptp_init(dev); in macb_open()
3000 phy_power_off(bp->sgmii_phy); in macb_open()
3004 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in macb_open()
3005 napi_disable(&queue->napi_rx); in macb_open()
3006 napi_disable(&queue->napi_tx); in macb_open()
3010 pm_runtime_put_sync(&bp->pdev->dev); in macb_open()
3023 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in macb_close()
3024 napi_disable(&queue->napi_rx); in macb_close()
3025 napi_disable(&queue->napi_tx); in macb_close()
3028 phylink_stop(bp->phylink); in macb_close()
3029 phylink_disconnect_phy(bp->phylink); in macb_close()
3031 phy_power_off(bp->sgmii_phy); in macb_close()
3033 spin_lock_irqsave(&bp->lock, flags); in macb_close()
3036 spin_unlock_irqrestore(&bp->lock, flags); in macb_close()
3040 if (bp->ptp_info) in macb_close()
3041 bp->ptp_info->ptp_remove(dev); in macb_close()
3043 pm_runtime_put(&bp->pdev->dev); in macb_close()
3051 return -EBUSY; in macb_change_mtu()
3053 WRITE_ONCE(dev->mtu, new_mtu); in macb_change_mtu()
3076 u32 *p = &bp->hw_stats.gem.tx_octets_31_0; in gem_update_stats()
3080 u64 val = bp->macb_reg_readl(bp, offset); in gem_update_stats()
3082 bp->ethtool_stats[i] += val; in gem_update_stats()
3087 val = bp->macb_reg_readl(bp, offset + 4); in gem_update_stats()
3088 bp->ethtool_stats[i] += ((u64)val) << 32; in gem_update_stats()
3094 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) in gem_update_stats()
3095 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat) in gem_update_stats()
3096 bp->ethtool_stats[idx++] = *stat; in gem_update_stats()
3101 struct gem_stats *hwstat = &bp->hw_stats.gem; in gem_get_stats()
3102 struct net_device_stats *nstat = &bp->dev->stats; in gem_get_stats()
3104 if (!netif_running(bp->dev)) in gem_get_stats()
3107 spin_lock_irq(&bp->stats_lock); in gem_get_stats()
3110 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors + in gem_get_stats()
3111 hwstat->rx_alignment_errors + in gem_get_stats()
3112 hwstat->rx_resource_errors + in gem_get_stats()
3113 hwstat->rx_overruns + in gem_get_stats()
3114 hwstat->rx_oversize_frames + in gem_get_stats()
3115 hwstat->rx_jabbers + in gem_get_stats()
3116 hwstat->rx_undersized_frames + in gem_get_stats()
3117 hwstat->rx_length_field_frame_errors); in gem_get_stats()
3118 nstat->tx_errors = (hwstat->tx_late_collisions + in gem_get_stats()
3119 hwstat->tx_excessive_collisions + in gem_get_stats()
3120 hwstat->tx_underrun + in gem_get_stats()
3121 hwstat->tx_carrier_sense_errors); in gem_get_stats()
3122 nstat->multicast = hwstat->rx_multicast_frames; in gem_get_stats()
3123 nstat->collisions = (hwstat->tx_single_collision_frames + in gem_get_stats()
3124 hwstat->tx_multiple_collision_frames + in gem_get_stats()
3125 hwstat->tx_excessive_collisions); in gem_get_stats()
3126 nstat->rx_length_errors = (hwstat->rx_oversize_frames + in gem_get_stats()
3127 hwstat->rx_jabbers + in gem_get_stats()
3128 hwstat->rx_undersized_frames + in gem_get_stats()
3129 hwstat->rx_length_field_frame_errors); in gem_get_stats()
3130 nstat->rx_over_errors = hwstat->rx_resource_errors; in gem_get_stats()
3131 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors; in gem_get_stats()
3132 nstat->rx_frame_errors = hwstat->rx_alignment_errors; in gem_get_stats()
3133 nstat->rx_fifo_errors = hwstat->rx_overruns; in gem_get_stats()
3134 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions; in gem_get_stats()
3135 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors; in gem_get_stats()
3136 nstat->tx_fifo_errors = hwstat->tx_underrun; in gem_get_stats()
3137 spin_unlock_irq(&bp->stats_lock); in gem_get_stats()
3147 spin_lock_irq(&bp->stats_lock); in gem_get_ethtool_stats()
3149 memcpy(data, &bp->ethtool_stats, sizeof(u64) in gem_get_ethtool_stats()
3151 spin_unlock_irq(&bp->stats_lock); in gem_get_ethtool_stats()
3160 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN; in gem_get_sset_count()
3162 return -EOPNOTSUPP; in gem_get_sset_count()
3180 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) { in gem_get_ethtool_strings()
3194 struct net_device_stats *nstat = &bp->dev->stats; in macb_get_stats()
3195 struct macb_stats *hwstat = &bp->hw_stats.macb; in macb_get_stats()
3201 spin_lock_irq(&bp->stats_lock); in macb_get_stats()
3205 nstat->rx_errors = (hwstat->rx_fcs_errors + in macb_get_stats()
3206 hwstat->rx_align_errors + in macb_get_stats()
3207 hwstat->rx_resource_errors + in macb_get_stats()
3208 hwstat->rx_overruns + in macb_get_stats()
3209 hwstat->rx_oversize_pkts + in macb_get_stats()
3210 hwstat->rx_jabbers + in macb_get_stats()
3211 hwstat->rx_undersize_pkts + in macb_get_stats()
3212 hwstat->rx_length_mismatch); in macb_get_stats()
3213 nstat->tx_errors = (hwstat->tx_late_cols + in macb_get_stats()
3214 hwstat->tx_excessive_cols + in macb_get_stats()
3215 hwstat->tx_underruns + in macb_get_stats()
3216 hwstat->tx_carrier_errors + in macb_get_stats()
3217 hwstat->sqe_test_errors); in macb_get_stats()
3218 nstat->collisions = (hwstat->tx_single_cols + in macb_get_stats()
3219 hwstat->tx_multiple_cols + in macb_get_stats()
3220 hwstat->tx_excessive_cols); in macb_get_stats()
3221 nstat->rx_length_errors = (hwstat->rx_oversize_pkts + in macb_get_stats()
3222 hwstat->rx_jabbers + in macb_get_stats()
3223 hwstat->rx_undersize_pkts + in macb_get_stats()
3224 hwstat->rx_length_mismatch); in macb_get_stats()
3225 nstat->rx_over_errors = hwstat->rx_resource_errors + in macb_get_stats()
3226 hwstat->rx_overruns; in macb_get_stats()
3227 nstat->rx_crc_errors = hwstat->rx_fcs_errors; in macb_get_stats()
3228 nstat->rx_frame_errors = hwstat->rx_align_errors; in macb_get_stats()
3229 nstat->rx_fifo_errors = hwstat->rx_overruns; in macb_get_stats()
3231 nstat->tx_aborted_errors = hwstat->tx_excessive_cols; in macb_get_stats()
3232 nstat->tx_carrier_errors = hwstat->tx_carrier_errors; in macb_get_stats()
3233 nstat->tx_fifo_errors = hwstat->tx_underruns; in macb_get_stats()
3235 spin_unlock_irq(&bp->stats_lock); in macb_get_stats()
3252 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1)) in macb_get_regs()
3255 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail); in macb_get_regs()
3256 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head); in macb_get_regs()
3259 regs_buff[1] = macb_or_gem_readl(bp, NCFGR); in macb_get_regs()
3269 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail); in macb_get_regs()
3270 regs_buff[11] = macb_tx_dma(&bp->queues[0], head); in macb_get_regs()
3272 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) in macb_get_regs()
3282 phylink_ethtool_get_wol(bp->phylink, wol); in macb_get_wol()
3283 wol->supported |= (WAKE_MAGIC | WAKE_ARP); in macb_get_wol()
3286 wol->wolopts |= bp->wolopts; in macb_get_wol()
3295 ret = phylink_ethtool_set_wol(bp->phylink, wol); in macb_set_wol()
3297 if (ret && ret != -EOPNOTSUPP) in macb_set_wol()
3300 bp->wolopts = (wol->wolopts & WAKE_MAGIC) ? WAKE_MAGIC : 0; in macb_set_wol()
3301 bp->wolopts |= (wol->wolopts & WAKE_ARP) ? WAKE_ARP : 0; in macb_set_wol()
3302 bp->wol = (wol->wolopts) ? MACB_WOL_ENABLED : 0; in macb_set_wol()
3304 device_set_wakeup_enable(&bp->pdev->dev, bp->wol); in macb_set_wol()
3314 return phylink_ethtool_ksettings_get(bp->phylink, kset); in macb_get_link_ksettings()
3322 return phylink_ethtool_ksettings_set(bp->phylink, kset); in macb_set_link_ksettings()
3332 ring->rx_max_pending = MAX_RX_RING_SIZE; in macb_get_ringparam()
3333 ring->tx_max_pending = MAX_TX_RING_SIZE; in macb_get_ringparam()
3335 ring->rx_pending = bp->rx_ring_size; in macb_get_ringparam()
3336 ring->tx_pending = bp->tx_ring_size; in macb_get_ringparam()
3348 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) in macb_set_ringparam()
3349 return -EINVAL; in macb_set_ringparam()
3351 new_rx_size = clamp_t(u32, ring->rx_pending, in macb_set_ringparam()
3355 new_tx_size = clamp_t(u32, ring->tx_pending, in macb_set_ringparam()
3359 if ((new_tx_size == bp->tx_ring_size) && in macb_set_ringparam()
3360 (new_rx_size == bp->rx_ring_size)) { in macb_set_ringparam()
3365 if (netif_running(bp->dev)) { in macb_set_ringparam()
3366 reset = 1; in macb_set_ringparam()
3367 macb_close(bp->dev); in macb_set_ringparam()
3370 bp->rx_ring_size = new_rx_size; in macb_set_ringparam()
3371 bp->tx_ring_size = new_tx_size; in macb_set_ringparam()
3374 macb_open(bp->dev); in macb_set_ringparam()
3385 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk"); in gem_get_tsu_rate()
3389 else if (!IS_ERR(bp->pclk)) { in gem_get_tsu_rate()
3390 tsu_clk = bp->pclk; in gem_get_tsu_rate()
3393 return -ENOTSUPP; in gem_get_tsu_rate()
3407 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) { in gem_get_ts_info()
3412 info->so_timestamping = in gem_get_ts_info()
3417 info->tx_types = in gem_get_ts_info()
3418 (1 << HWTSTAMP_TX_ONESTEP_SYNC) | in gem_get_ts_info()
3419 (1 << HWTSTAMP_TX_OFF) | in gem_get_ts_info()
3420 (1 << HWTSTAMP_TX_ON); in gem_get_ts_info()
3421 info->rx_filters = in gem_get_ts_info()
3422 (1 << HWTSTAMP_FILTER_NONE) | in gem_get_ts_info()
3423 (1 << HWTSTAMP_FILTER_ALL); in gem_get_ts_info()
3425 if (bp->ptp_clock) in gem_get_ts_info()
3426 info->phc_index = ptp_clock_index(bp->ptp_clock); in gem_get_ts_info()
3447 if (bp->ptp_info) in macb_get_ts_info()
3448 return bp->ptp_info->get_ts_info(netdev, info); in macb_get_ts_info()
3455 struct net_device *netdev = bp->dev; in gem_enable_flow_filters()
3460 if (!(netdev->features & NETIF_F_NTUPLE)) in gem_enable_flow_filters()
3465 list_for_each_entry(item, &bp->rx_fs_list.list, list) { in gem_enable_flow_filters()
3466 struct ethtool_rx_flow_spec *fs = &item->fs; in gem_enable_flow_filters()
3469 if (fs->location >= num_t2_scr) in gem_enable_flow_filters()
3472 t2_scr = gem_readl_n(bp, SCRT2, fs->location); in gem_enable_flow_filters()
3478 tp4sp_m = &(fs->m_u.tcp_ip4_spec); in gem_enable_flow_filters()
3480 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF)) in gem_enable_flow_filters()
3481 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr); in gem_enable_flow_filters()
3485 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF)) in gem_enable_flow_filters()
3486 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr); in gem_enable_flow_filters()
3490 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF))) in gem_enable_flow_filters()
3491 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr); in gem_enable_flow_filters()
3495 gem_writel_n(bp, SCRT2, fs->location, t2_scr); in gem_enable_flow_filters()
3502 uint16_t index = fs->location; in gem_prog_cmp_regs()
3511 tp4sp_v = &(fs->h_u.tcp_ip4_spec); in gem_prog_cmp_regs()
3512 tp4sp_m = &(fs->m_u.tcp_ip4_spec); in gem_prog_cmp_regs()
3515 if (tp4sp_m->ip4src == 0xFFFFFFFF) { in gem_prog_cmp_regs()
3516 /* 1st compare reg - IP source address */ in gem_prog_cmp_regs()
3519 w0 = tp4sp_v->ip4src; in gem_prog_cmp_regs()
3520 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ in gem_prog_cmp_regs()
3529 if (tp4sp_m->ip4dst == 0xFFFFFFFF) { in gem_prog_cmp_regs()
3530 /* 2nd compare reg - IP destination address */ in gem_prog_cmp_regs()
3533 w0 = tp4sp_v->ip4dst; in gem_prog_cmp_regs()
3534 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ in gem_prog_cmp_regs()
3543 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) { in gem_prog_cmp_regs()
3544 /* 3rd compare reg - source port, destination port */ in gem_prog_cmp_regs()
3548 if (tp4sp_m->psrc == tp4sp_m->pdst) { in gem_prog_cmp_regs()
3549 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0); in gem_prog_cmp_regs()
3550 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); in gem_prog_cmp_regs()
3551 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */ in gem_prog_cmp_regs()
3555 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */ in gem_prog_cmp_regs()
3557 if (tp4sp_m->psrc == 0xFFFF) { /* src port */ in gem_prog_cmp_regs()
3558 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0); in gem_prog_cmp_regs()
3561 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0); in gem_prog_cmp_regs()
3571 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr); in gem_prog_cmp_regs()
3586 struct ethtool_rx_flow_spec *fs = &cmd->fs; in gem_add_flow_filter()
3589 int ret = -EINVAL; in gem_add_flow_filter()
3594 return -ENOMEM; in gem_add_flow_filter()
3595 memcpy(&newfs->fs, fs, sizeof(newfs->fs)); in gem_add_flow_filter()
3599 fs->flow_type, (int)fs->ring_cookie, fs->location, in gem_add_flow_filter()
3600 htonl(fs->h_u.tcp_ip4_spec.ip4src), in gem_add_flow_filter()
3601 htonl(fs->h_u.tcp_ip4_spec.ip4dst), in gem_add_flow_filter()
3602 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc), in gem_add_flow_filter()
3603 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst)); in gem_add_flow_filter()
3605 spin_lock_irqsave(&bp->rx_fs_lock, flags); in gem_add_flow_filter()
3608 list_for_each_entry(item, &bp->rx_fs_list.list, list) { in gem_add_flow_filter()
3609 if (item->fs.location > newfs->fs.location) { in gem_add_flow_filter()
3610 list_add_tail(&newfs->list, &item->list); in gem_add_flow_filter()
3613 } else if (item->fs.location == fs->location) { in gem_add_flow_filter()
3615 fs->location); in gem_add_flow_filter()
3616 ret = -EBUSY; in gem_add_flow_filter()
3621 list_add_tail(&newfs->list, &bp->rx_fs_list.list); in gem_add_flow_filter()
3624 bp->rx_fs_list.count++; in gem_add_flow_filter()
3626 gem_enable_flow_filters(bp, 1); in gem_add_flow_filter()
3628 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); in gem_add_flow_filter()
3632 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); in gem_add_flow_filter()
3645 spin_lock_irqsave(&bp->rx_fs_lock, flags); in gem_del_flow_filter()
3647 list_for_each_entry(item, &bp->rx_fs_list.list, list) { in gem_del_flow_filter()
3648 if (item->fs.location == cmd->fs.location) { in gem_del_flow_filter()
3650 fs = &(item->fs); in gem_del_flow_filter()
3653 fs->flow_type, (int)fs->ring_cookie, fs->location, in gem_del_flow_filter()
3654 htonl(fs->h_u.tcp_ip4_spec.ip4src), in gem_del_flow_filter()
3655 htonl(fs->h_u.tcp_ip4_spec.ip4dst), in gem_del_flow_filter()
3656 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc), in gem_del_flow_filter()
3657 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst)); in gem_del_flow_filter()
3659 gem_writel_n(bp, SCRT2, fs->location, 0); in gem_del_flow_filter()
3661 list_del(&item->list); in gem_del_flow_filter()
3662 bp->rx_fs_list.count--; in gem_del_flow_filter()
3663 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); in gem_del_flow_filter()
3669 spin_unlock_irqrestore(&bp->rx_fs_lock, flags); in gem_del_flow_filter()
3670 return -EINVAL; in gem_del_flow_filter()
3679 list_for_each_entry(item, &bp->rx_fs_list.list, list) { in gem_get_flow_entry()
3680 if (item->fs.location == cmd->fs.location) { in gem_get_flow_entry()
3681 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs)); in gem_get_flow_entry()
3685 return -EINVAL; in gem_get_flow_entry()
3695 list_for_each_entry(item, &bp->rx_fs_list.list, list) { in gem_get_all_flow_entries()
3696 if (cnt == cmd->rule_cnt) in gem_get_all_flow_entries()
3697 return -EMSGSIZE; in gem_get_all_flow_entries()
3698 rule_locs[cnt] = item->fs.location; in gem_get_all_flow_entries()
3701 cmd->data = bp->max_tuples; in gem_get_all_flow_entries()
3702 cmd->rule_cnt = cnt; in gem_get_all_flow_entries()
3713 switch (cmd->cmd) { in gem_get_rxnfc()
3715 cmd->data = bp->num_queues; in gem_get_rxnfc()
3718 cmd->rule_cnt = bp->rx_fs_list.count; in gem_get_rxnfc()
3728 "Command parameter %d is not supported\n", cmd->cmd); in gem_get_rxnfc()
3729 ret = -EOPNOTSUPP; in gem_get_rxnfc()
3740 switch (cmd->cmd) { in gem_set_rxnfc()
3742 if ((cmd->fs.location >= bp->max_tuples) in gem_set_rxnfc()
3743 || (cmd->fs.ring_cookie >= bp->num_queues)) { in gem_set_rxnfc()
3744 ret = -EINVAL; in gem_set_rxnfc()
3754 "Command parameter %d is not supported\n", cmd->cmd); in gem_set_rxnfc()
3755 ret = -EOPNOTSUPP; in gem_set_rxnfc()
3797 return -EINVAL; in macb_ioctl()
3799 return phylink_mii_ioctl(bp->phylink, rq, cmd); in macb_ioctl()
3808 return -EINVAL; in macb_hwtstamp_get()
3810 if (!bp->ptp_info) in macb_hwtstamp_get()
3811 return -EOPNOTSUPP; in macb_hwtstamp_get()
3813 return bp->ptp_info->get_hwtst(dev, cfg); in macb_hwtstamp_get()
3823 return -EINVAL; in macb_hwtstamp_set()
3825 if (!bp->ptp_info) in macb_hwtstamp_set()
3826 return -EOPNOTSUPP; in macb_hwtstamp_set()
3828 return bp->ptp_info->set_hwtst(dev, cfg, extack); in macb_hwtstamp_set()
3851 struct net_device *netdev = bp->dev; in macb_set_rxcsum_feature()
3858 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC)) in macb_set_rxcsum_feature()
3879 netdev_features_t changed = features ^ netdev->features; in macb_set_features()
3898 struct net_device *netdev = bp->dev; in macb_restore_features()
3899 netdev_features_t features = netdev->features; in macb_restore_features()
3909 list_for_each_entry(item, &bp->rx_fs_list.list, list) in macb_restore_features()
3910 gem_prog_cmp_regs(bp, &item->fs); in macb_restore_features()
3943 bp->caps = dt_conf->caps; in macb_configure_caps()
3945 if (hw_is_gem(bp->regs, bp->native_io)) { in macb_configure_caps()
3946 bp->caps |= MACB_CAPS_MACB_IS_GEM; in macb_configure_caps()
3950 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE; in macb_configure_caps()
3952 bp->caps |= MACB_CAPS_PCS; in macb_configure_caps()
3954 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1) in macb_configure_caps()
3955 bp->caps |= MACB_CAPS_HIGH_SPEED; in macb_configure_caps()
3958 bp->caps |= MACB_CAPS_FIFO_MODE; in macb_configure_caps()
3961 dev_err(&bp->pdev->dev, in macb_configure_caps()
3965 bp->hw_dma_cap |= HW_DMA_CAP_PTP; in macb_configure_caps()
3966 bp->ptp_info = &gem_ptp_info; in macb_configure_caps()
3972 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps); in macb_configure_caps()
3981 *num_queues = 1; in macb_probe_queues()
4018 pdata = dev_get_platdata(&pdev->dev); in macb_clk_init()
4020 *pclk = pdata->pclk; in macb_clk_init()
4021 *hclk = pdata->hclk; in macb_clk_init()
4023 *pclk = devm_clk_get(&pdev->dev, "pclk"); in macb_clk_init()
4024 *hclk = devm_clk_get(&pdev->dev, "hclk"); in macb_clk_init()
4028 return dev_err_probe(&pdev->dev, in macb_clk_init()
4029 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV, in macb_clk_init()
4033 return dev_err_probe(&pdev->dev, in macb_clk_init()
4034 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV, in macb_clk_init()
4037 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk"); in macb_clk_init()
4041 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk"); in macb_clk_init()
4045 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk"); in macb_clk_init()
4051 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err); in macb_clk_init()
4057 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err); in macb_clk_init()
4063 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in macb_clk_init()
4069 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); in macb_clk_init()
4075 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err); in macb_clk_init()
4105 bp->tx_ring_size = DEFAULT_TX_RING_SIZE; in macb_init()
4106 bp->rx_ring_size = DEFAULT_RX_RING_SIZE; in macb_init()
4113 if (!(bp->queue_mask & (1 << hw_q))) in macb_init()
4116 queue = &bp->queues[q]; in macb_init()
4117 queue->bp = bp; in macb_init()
4118 spin_lock_init(&queue->tx_ptr_lock); in macb_init()
4119 netif_napi_add(dev, &queue->napi_rx, macb_rx_poll); in macb_init()
4120 netif_napi_add(dev, &queue->napi_tx, macb_tx_poll); in macb_init()
4122 queue->ISR = GEM_ISR(hw_q - 1); in macb_init()
4123 queue->IER = GEM_IER(hw_q - 1); in macb_init()
4124 queue->IDR = GEM_IDR(hw_q - 1); in macb_init()
4125 queue->IMR = GEM_IMR(hw_q - 1); in macb_init()
4126 queue->TBQP = GEM_TBQP(hw_q - 1); in macb_init()
4127 queue->RBQP = GEM_RBQP(hw_q - 1); in macb_init()
4128 queue->RBQS = GEM_RBQS(hw_q - 1); in macb_init()
4130 if (bp->hw_dma_cap & HW_DMA_CAP_64B) { in macb_init()
4131 queue->TBQPH = GEM_TBQPH(hw_q - 1); in macb_init()
4132 queue->RBQPH = GEM_RBQPH(hw_q - 1); in macb_init()
4137 queue->ISR = MACB_ISR; in macb_init()
4138 queue->IER = MACB_IER; in macb_init()
4139 queue->IDR = MACB_IDR; in macb_init()
4140 queue->IMR = MACB_IMR; in macb_init()
4141 queue->TBQP = MACB_TBQP; in macb_init()
4142 queue->RBQP = MACB_RBQP; in macb_init()
4144 if (bp->hw_dma_cap & HW_DMA_CAP_64B) { in macb_init()
4145 queue->TBQPH = MACB_TBQPH; in macb_init()
4146 queue->RBQPH = MACB_RBQPH; in macb_init()
4156 queue->irq = platform_get_irq(pdev, q); in macb_init()
4157 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt, in macb_init()
4158 IRQF_SHARED, dev->name, queue); in macb_init()
4160 dev_err(&pdev->dev, in macb_init()
4162 queue->irq, err); in macb_init()
4166 INIT_WORK(&queue->tx_error_task, macb_tx_error_task); in macb_init()
4170 dev->netdev_ops = &macb_netdev_ops; in macb_init()
4174 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers; in macb_init()
4175 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers; in macb_init()
4176 bp->macbgem_ops.mog_init_rings = gem_init_rings; in macb_init()
4177 bp->macbgem_ops.mog_rx = gem_rx; in macb_init()
4178 dev->ethtool_ops = &gem_ethtool_ops; in macb_init()
4180 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers; in macb_init()
4181 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers; in macb_init()
4182 bp->macbgem_ops.mog_init_rings = macb_init_rings; in macb_init()
4183 bp->macbgem_ops.mog_rx = macb_rx; in macb_init()
4184 dev->ethtool_ops = &macb_ethtool_ops; in macb_init()
4189 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; in macb_init()
4192 dev->hw_features = NETIF_F_SG; in macb_init()
4196 dev->hw_features |= MACB_NETIF_LSO; in macb_init()
4199 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE)) in macb_init()
4200 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM; in macb_init()
4201 if (bp->caps & MACB_CAPS_SG_DISABLED) in macb_init()
4202 dev->hw_features &= ~NETIF_F_SG; in macb_init()
4203 dev->features = dev->hw_features; in macb_init()
4207 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs in macb_init()
4210 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3), in macb_init()
4212 INIT_LIST_HEAD(&bp->rx_fs_list.list); in macb_init()
4213 if (bp->max_tuples > 0) { in macb_init()
4221 dev->hw_features |= NETIF_F_NTUPLE; in macb_init()
4223 bp->rx_fs_list.count = 0; in macb_init()
4224 spin_lock_init(&bp->rx_fs_lock); in macb_init()
4226 bp->max_tuples = 0; in macb_init()
4229 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) { in macb_init()
4231 if (phy_interface_mode_is_rgmii(bp->phy_interface)) in macb_init()
4232 val = bp->usrio->rgmii; in macb_init()
4233 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII && in macb_init()
4234 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) in macb_init()
4235 val = bp->usrio->rmii; in macb_init()
4236 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII)) in macb_init()
4237 val = bp->usrio->mii; in macb_init()
4239 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN) in macb_init()
4240 val |= bp->usrio->refclk; in macb_init()
4248 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) in macb_init()
4272 struct macb_queue *q = &lp->queues[0]; in at91ether_alloc_coherent()
4274 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev, in at91ether_alloc_coherent()
4277 &q->rx_ring_dma, GFP_KERNEL); in at91ether_alloc_coherent()
4278 if (!q->rx_ring) in at91ether_alloc_coherent()
4279 return -ENOMEM; in at91ether_alloc_coherent()
4281 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev, in at91ether_alloc_coherent()
4284 &q->rx_buffers_dma, GFP_KERNEL); in at91ether_alloc_coherent()
4285 if (!q->rx_buffers) { in at91ether_alloc_coherent()
4286 dma_free_coherent(&lp->pdev->dev, in at91ether_alloc_coherent()
4289 q->rx_ring, q->rx_ring_dma); in at91ether_alloc_coherent()
4290 q->rx_ring = NULL; in at91ether_alloc_coherent()
4291 return -ENOMEM; in at91ether_alloc_coherent()
4299 struct macb_queue *q = &lp->queues[0]; in at91ether_free_coherent()
4301 if (q->rx_ring) { in at91ether_free_coherent()
4302 dma_free_coherent(&lp->pdev->dev, in at91ether_free_coherent()
4305 q->rx_ring, q->rx_ring_dma); in at91ether_free_coherent()
4306 q->rx_ring = NULL; in at91ether_free_coherent()
4309 if (q->rx_buffers) { in at91ether_free_coherent()
4310 dma_free_coherent(&lp->pdev->dev, in at91ether_free_coherent()
4313 q->rx_buffers, q->rx_buffers_dma); in at91ether_free_coherent()
4314 q->rx_buffers = NULL; in at91ether_free_coherent()
4321 struct macb_queue *q = &lp->queues[0]; in at91ether_start()
4331 addr = q->rx_buffers_dma; in at91ether_start()
4335 desc->ctrl = 0; in at91ether_start()
4340 desc->addr |= MACB_BIT(RX_WRAP); in at91ether_start()
4343 q->rx_tail = 0; in at91ether_start()
4346 macb_writel(lp, RBQP, q->rx_ring_dma); in at91ether_start()
4392 ret = pm_runtime_resume_and_get(&lp->pdev->dev); in at91ether_open()
4417 pm_runtime_put_sync(&lp->pdev->dev); in at91ether_open()
4428 phylink_stop(lp->phylink); in at91ether_close()
4429 phylink_disconnect_phy(lp->phylink); in at91ether_close()
4433 return pm_runtime_put(&lp->pdev->dev); in at91ether_close()
4448 lp->rm9200_txq[desc].skb = skb; in at91ether_start_xmit()
4449 lp->rm9200_txq[desc].size = skb->len; in at91ether_start_xmit()
4450 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data, in at91ether_start_xmit()
4451 skb->len, DMA_TO_DEVICE); in at91ether_start_xmit()
4452 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) { in at91ether_start_xmit()
4454 dev->stats.tx_dropped++; in at91ether_start_xmit()
4460 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping); in at91ether_start_xmit()
4462 macb_writel(lp, TCR, skb->len); in at91ether_start_xmit()
4478 struct macb_queue *q = &lp->queues[0]; in at91ether_rx()
4484 desc = macb_rx_desc(q, q->rx_tail); in at91ether_rx()
4485 while (desc->addr & MACB_BIT(RX_USED)) { in at91ether_rx()
4486 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ; in at91ether_rx()
4487 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl); in at91ether_rx()
4493 skb->protocol = eth_type_trans(skb, dev); in at91ether_rx()
4494 dev->stats.rx_packets++; in at91ether_rx()
4495 dev->stats.rx_bytes += pktlen; in at91ether_rx()
4498 dev->stats.rx_dropped++; in at91ether_rx()
4501 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH)) in at91ether_rx()
4502 dev->stats.multicast++; in at91ether_rx()
4505 desc->addr &= ~MACB_BIT(RX_USED); in at91ether_rx()
4508 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1) in at91ether_rx()
4509 q->rx_tail = 0; in at91ether_rx()
4511 q->rx_tail++; in at91ether_rx()
4513 desc = macb_rx_desc(q, q->rx_tail); in at91ether_rx()
4538 dev->stats.tx_errors++; in at91ether_interrupt()
4541 if (lp->rm9200_txq[desc].skb) { in at91ether_interrupt()
4542 dev_consume_skb_irq(lp->rm9200_txq[desc].skb); in at91ether_interrupt()
4543 lp->rm9200_txq[desc].skb = NULL; in at91ether_interrupt()
4544 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping, in at91ether_interrupt()
4545 lp->rm9200_txq[desc].size, DMA_TO_DEVICE); in at91ether_interrupt()
4546 dev->stats.tx_packets++; in at91ether_interrupt()
4547 dev->stats.tx_bytes += lp->rm9200_txq[desc].size; in at91ether_interrupt()
4552 /* Work-around for EMAC Errata section 41.3.1 */ in at91ether_interrupt()
4572 at91ether_interrupt(dev->irq, dev); in at91ether_poll_controller()
4604 *pclk = devm_clk_get(&pdev->dev, "ether_clk"); in at91ether_clk_init()
4610 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err); in at91ether_clk_init()
4623 bp->queues[0].bp = bp; in at91ether_init()
4625 dev->netdev_ops = &at91ether_netdev_ops; in at91ether_init()
4626 dev->ethtool_ops = &macb_ethtool_ops; in at91ether_init()
4628 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt, in at91ether_init()
4629 0, dev->name, dev); in at91ether_init()
4643 return mgmt->rate; in fu540_macb_tx_recalc_rate()
4676 iowrite32(1, mgmt->reg); in fu540_macb_tx_set_rate()
4678 iowrite32(0, mgmt->reg); in fu540_macb_tx_set_rate()
4679 mgmt->rate = rate; in fu540_macb_tx_set_rate()
4701 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL); in fu540_c000_clk_init()
4703 err = -ENOMEM; in fu540_c000_clk_init()
4707 init.name = "sifive-gemgxl-mgmt"; in fu540_c000_clk_init()
4712 mgmt->rate = 0; in fu540_c000_clk_init()
4713 mgmt->hw.init = &init; in fu540_c000_clk_init()
4715 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw); in fu540_c000_clk_init()
4723 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err); in fu540_c000_clk_init()
4727 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name); in fu540_c000_clk_init()
4740 mgmt->reg = devm_platform_ioremap_resource(pdev, 1); in fu540_c000_init()
4741 if (IS_ERR(mgmt->reg)) in fu540_c000_init()
4742 return PTR_ERR(mgmt->reg); in fu540_c000_init()
4753 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) { in init_reset_optional()
4755 bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL); in init_reset_optional()
4757 if (IS_ERR(bp->sgmii_phy)) in init_reset_optional()
4758 return dev_err_probe(&pdev->dev, PTR_ERR(bp->sgmii_phy), in init_reset_optional()
4761 ret = phy_init(bp->sgmii_phy); in init_reset_optional()
4763 return dev_err_probe(&pdev->dev, ret, in init_reset_optional()
4770 ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains", in init_reset_optional()
4773 dev_err(&pdev->dev, "Failed to read power management information\n"); in init_reset_optional()
4776 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0); in init_reset_optional()
4780 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1); in init_reset_optional()
4788 ret = device_reset_optional(&pdev->dev); in init_reset_optional()
4790 phy_exit(bp->sgmii_phy); in init_reset_optional()
4791 return dev_err_probe(&pdev->dev, ret, "failed to reset controller"); in init_reset_optional()
4798 phy_exit(bp->sgmii_phy); in init_reset_optional()
4805 .rmii = 1,
4956 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4958 { .compatible = "cdns,np4-macb", .data = &np4_config },
4959 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4961 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4962 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4963 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
4964 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4965 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4966 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4967 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4969 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
4970 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
4971 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4972 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
4973 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4974 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4975 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
4976 { .compatible = "xlnx,zynq-gem", .data = &zynq_config },
4977 { .compatible = "xlnx,versal-gem", .data = &versal_config},
4999 struct clk **) = macb_config->clk_init; in macb_probe()
5000 int (*init)(struct platform_device *) = macb_config->init; in macb_probe()
5001 struct device_node *np = pdev->dev.of_node; in macb_probe()
5022 if (match && match->data) { in macb_probe()
5023 macb_config = match->data; in macb_probe()
5024 clk_init = macb_config->clk_init; in macb_probe()
5025 init = macb_config->init; in macb_probe()
5033 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT); in macb_probe()
5034 pm_runtime_use_autosuspend(&pdev->dev); in macb_probe()
5035 pm_runtime_get_noresume(&pdev->dev); in macb_probe()
5036 pm_runtime_set_active(&pdev->dev); in macb_probe()
5037 pm_runtime_enable(&pdev->dev); in macb_probe()
5043 err = -ENOMEM; in macb_probe()
5047 dev->base_addr = regs->start; in macb_probe()
5049 SET_NETDEV_DEV(dev, &pdev->dev); in macb_probe()
5052 bp->pdev = pdev; in macb_probe()
5053 bp->dev = dev; in macb_probe()
5054 bp->regs = mem; in macb_probe()
5055 bp->native_io = native_io; in macb_probe()
5057 bp->macb_reg_readl = hw_readl_native; in macb_probe()
5058 bp->macb_reg_writel = hw_writel_native; in macb_probe()
5060 bp->macb_reg_readl = hw_readl; in macb_probe()
5061 bp->macb_reg_writel = hw_writel; in macb_probe()
5063 bp->num_queues = num_queues; in macb_probe()
5064 bp->queue_mask = queue_mask; in macb_probe()
5066 bp->dma_burst_length = macb_config->dma_burst_length; in macb_probe()
5067 bp->pclk = pclk; in macb_probe()
5068 bp->hclk = hclk; in macb_probe()
5069 bp->tx_clk = tx_clk; in macb_probe()
5070 bp->rx_clk = rx_clk; in macb_probe()
5071 bp->tsu_clk = tsu_clk; in macb_probe()
5073 bp->jumbo_max_len = macb_config->jumbo_max_len; in macb_probe()
5075 if (!hw_is_gem(bp->regs, bp->native_io)) in macb_probe()
5076 bp->max_tx_length = MACB_MAX_TX_LEN; in macb_probe()
5077 else if (macb_config->max_tx_length) in macb_probe()
5078 bp->max_tx_length = macb_config->max_tx_length; in macb_probe()
5080 bp->max_tx_length = GEM_MAX_TX_LEN; in macb_probe()
5082 bp->wol = 0; in macb_probe()
5083 device_set_wakeup_capable(&pdev->dev, 1); in macb_probe()
5085 bp->usrio = macb_config->usrio; in macb_probe()
5091 err = of_property_read_u32(bp->pdev->dev.of_node, in macb_probe()
5092 "cdns,rx-watermark", in macb_probe()
5093 &bp->rx_watermark); in macb_probe()
5099 wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1; in macb_probe()
5100 if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) { in macb_probe()
5101 dev_info(&bp->pdev->dev, "Invalid watermark value\n"); in macb_probe()
5102 bp->rx_watermark = 0; in macb_probe()
5106 spin_lock_init(&bp->lock); in macb_probe()
5107 spin_lock_init(&bp->stats_lock); in macb_probe()
5114 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); in macb_probe()
5115 bp->hw_dma_cap |= HW_DMA_CAP_64B; in macb_probe()
5120 dev->irq = platform_get_irq(pdev, 0); in macb_probe()
5121 if (dev->irq < 0) { in macb_probe()
5122 err = dev->irq; in macb_probe()
5126 /* MTU range: 68 - 1518 or 10240 */ in macb_probe()
5127 dev->min_mtu = GEM_MTU_MIN_SIZE; in macb_probe()
5128 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len) in macb_probe()
5129 dev->max_mtu = bp->jumbo_max_len - ETH_HLEN - ETH_FCS_LEN; in macb_probe()
5131 dev->max_mtu = 1536 - ETH_HLEN - ETH_FCS_LEN; in macb_probe()
5133 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) { in macb_probe()
5136 bp->rx_bd_rd_prefetch = (2 << (val - 1)) * in macb_probe()
5141 bp->tx_bd_rd_prefetch = (2 << (val - 1)) * in macb_probe()
5145 bp->rx_intr_mask = MACB_RX_INT_FLAGS; in macb_probe()
5146 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR) in macb_probe()
5147 bp->rx_intr_mask |= MACB_BIT(RXUBR); in macb_probe()
5149 err = of_get_ethdev_address(np, bp->dev); in macb_probe()
5150 if (err == -EPROBE_DEFER) in macb_probe()
5158 bp->phy_interface = PHY_INTERFACE_MODE_MII; in macb_probe()
5160 bp->phy_interface = interface; in macb_probe()
5175 dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); in macb_probe()
5179 INIT_WORK(&bp->hresp_err_bh_work, macb_hresp_error_task); in macb_probe()
5183 dev->base_addr, dev->irq, dev->dev_addr); in macb_probe()
5185 pm_runtime_mark_last_busy(&bp->pdev->dev); in macb_probe()
5186 pm_runtime_put_autosuspend(&bp->pdev->dev); in macb_probe()
5191 mdiobus_unregister(bp->mii_bus); in macb_probe()
5192 mdiobus_free(bp->mii_bus); in macb_probe()
5195 phy_exit(bp->sgmii_phy); in macb_probe()
5202 pm_runtime_disable(&pdev->dev); in macb_probe()
5203 pm_runtime_set_suspended(&pdev->dev); in macb_probe()
5204 pm_runtime_dont_use_autosuspend(&pdev->dev); in macb_probe()
5218 phy_exit(bp->sgmii_phy); in macb_remove()
5219 mdiobus_unregister(bp->mii_bus); in macb_remove()
5220 mdiobus_free(bp->mii_bus); in macb_remove()
5223 cancel_work_sync(&bp->hresp_err_bh_work); in macb_remove()
5224 pm_runtime_disable(&pdev->dev); in macb_remove()
5225 pm_runtime_dont_use_autosuspend(&pdev->dev); in macb_remove()
5226 if (!pm_runtime_suspended(&pdev->dev)) { in macb_remove()
5227 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, in macb_remove()
5228 bp->rx_clk, bp->tsu_clk); in macb_remove()
5229 pm_runtime_set_suspended(&pdev->dev); in macb_remove()
5231 phylink_destroy(bp->phylink); in macb_remove()
5248 if (!device_may_wakeup(&bp->dev->dev)) in macb_suspend()
5249 phy_exit(bp->sgmii_phy); in macb_suspend()
5254 if (bp->wol & MACB_WOL_ENABLED) { in macb_suspend()
5256 idev = __in_dev_get_rcu(bp->dev); in macb_suspend()
5258 ifa = rcu_dereference(idev->ifa_list); in macb_suspend()
5259 if ((bp->wolopts & WAKE_ARP) && !ifa) { in macb_suspend()
5261 return -EOPNOTSUPP; in macb_suspend()
5263 spin_lock_irqsave(&bp->lock, flags); in macb_suspend()
5270 for (q = 0, queue = bp->queues; q < bp->num_queues; in macb_suspend()
5273 if (bp->caps & MACB_CAPS_QUEUE_DISABLE) { in macb_suspend()
5278 lower_32_bits(bp->rx_ring_tieoff_dma)); in macb_suspend()
5281 upper_32_bits(bp->rx_ring_tieoff_dma)); in macb_suspend()
5285 queue_writel(queue, IDR, -1); in macb_suspend()
5287 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_suspend()
5288 queue_writel(queue, ISR, -1); in macb_suspend()
5293 macb_writel(bp, TSR, -1); in macb_suspend()
5294 macb_writel(bp, RSR, -1); in macb_suspend()
5296 tmp = (bp->wolopts & WAKE_MAGIC) ? MACB_BIT(MAG) : 0; in macb_suspend()
5297 if (bp->wolopts & WAKE_ARP) { in macb_suspend()
5300 tmp |= MACB_BFEXT(IP, be32_to_cpu(ifa->ifa_local)); in macb_suspend()
5306 devm_free_irq(dev, bp->queues[0].irq, bp->queues); in macb_suspend()
5308 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt, in macb_suspend()
5309 IRQF_SHARED, netdev->name, bp->queues); in macb_suspend()
5313 bp->queues[0].irq, err); in macb_suspend()
5314 spin_unlock_irqrestore(&bp->lock, flags); in macb_suspend()
5317 queue_writel(bp->queues, IER, GEM_BIT(WOL)); in macb_suspend()
5320 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt, in macb_suspend()
5321 IRQF_SHARED, netdev->name, bp->queues); in macb_suspend()
5325 bp->queues[0].irq, err); in macb_suspend()
5326 spin_unlock_irqrestore(&bp->lock, flags); in macb_suspend()
5329 queue_writel(bp->queues, IER, MACB_BIT(WOL)); in macb_suspend()
5332 spin_unlock_irqrestore(&bp->lock, flags); in macb_suspend()
5334 enable_irq_wake(bp->queues[0].irq); in macb_suspend()
5338 for (q = 0, queue = bp->queues; q < bp->num_queues; in macb_suspend()
5340 napi_disable(&queue->napi_rx); in macb_suspend()
5341 napi_disable(&queue->napi_tx); in macb_suspend()
5344 if (!(bp->wol & MACB_WOL_ENABLED)) { in macb_suspend()
5346 phylink_stop(bp->phylink); in macb_suspend()
5348 spin_lock_irqsave(&bp->lock, flags); in macb_suspend()
5350 spin_unlock_irqrestore(&bp->lock, flags); in macb_suspend()
5353 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) in macb_suspend()
5354 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO); in macb_suspend()
5356 if (netdev->hw_features & NETIF_F_NTUPLE) in macb_suspend()
5357 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT); in macb_suspend()
5359 if (bp->ptp_info) in macb_suspend()
5360 bp->ptp_info->ptp_remove(netdev); in macb_suspend()
5376 if (!device_may_wakeup(&bp->dev->dev)) in macb_resume()
5377 phy_init(bp->sgmii_phy); in macb_resume()
5385 if (bp->wol & MACB_WOL_ENABLED) { in macb_resume()
5386 spin_lock_irqsave(&bp->lock, flags); in macb_resume()
5389 queue_writel(bp->queues, IDR, GEM_BIT(WOL)); in macb_resume()
5392 queue_writel(bp->queues, IDR, MACB_BIT(WOL)); in macb_resume()
5396 queue_readl(bp->queues, ISR); in macb_resume()
5397 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) in macb_resume()
5398 queue_writel(bp->queues, ISR, -1); in macb_resume()
5400 devm_free_irq(dev, bp->queues[0].irq, bp->queues); in macb_resume()
5401 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt, in macb_resume()
5402 IRQF_SHARED, netdev->name, bp->queues); in macb_resume()
5406 bp->queues[0].irq, err); in macb_resume()
5407 spin_unlock_irqrestore(&bp->lock, flags); in macb_resume()
5410 spin_unlock_irqrestore(&bp->lock, flags); in macb_resume()
5412 disable_irq_wake(bp->queues[0].irq); in macb_resume()
5418 phylink_stop(bp->phylink); in macb_resume()
5422 for (q = 0, queue = bp->queues; q < bp->num_queues; in macb_resume()
5424 napi_enable(&queue->napi_rx); in macb_resume()
5425 napi_enable(&queue->napi_tx); in macb_resume()
5428 if (netdev->hw_features & NETIF_F_NTUPLE) in macb_resume()
5429 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2); in macb_resume()
5431 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) in macb_resume()
5432 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio); in macb_resume()
5440 phylink_start(bp->phylink); in macb_resume()
5444 if (bp->ptp_info) in macb_resume()
5445 bp->ptp_info->ptp_init(netdev); in macb_resume()
5456 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk); in macb_runtime_suspend()
5457 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) in macb_runtime_suspend()
5458 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk); in macb_runtime_suspend()
5469 clk_prepare_enable(bp->pclk); in macb_runtime_resume()
5470 clk_prepare_enable(bp->hclk); in macb_runtime_resume()
5471 clk_prepare_enable(bp->tx_clk); in macb_runtime_resume()
5472 clk_prepare_enable(bp->rx_clk); in macb_runtime_resume()
5473 clk_prepare_enable(bp->tsu_clk); in macb_runtime_resume()
5474 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) { in macb_runtime_resume()
5475 clk_prepare_enable(bp->tsu_clk); in macb_runtime_resume()