Lines Matching +full:0 +full:xc2000000
71 #define BAR_0 0
105 #define RESET_KIND_SHUTDOWN 0
109 #define TG3_DEF_RX_MODE 0
110 #define TG3_DEF_TX_MODE 0
195 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
201 #if (NET_IP_ALIGN != 0)
234 module_param(tg3_debug, int, 0);
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
445 #define TG3_NVRAM_TEST 0
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
543 (val == 0x1)) { in tg3_write_indirect_mbox()
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
657 *val = 0; in tg3_read_mem()
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
711 int ret = 0; in tg3_ape_lock()
715 return 0; in tg3_ape_lock()
720 return 0; in tg3_ape_lock()
752 for (i = 0; i < 100; i++) { in tg3_ape_lock()
826 return timeout_us ? 0 : -EBUSY; in tg3_ape_event_lock()
834 for (i = 0; i < timeout_us / 10; i++) { in tg3_ape_wait_for_event()
853 return 0; in tg3_ape_scratchpad_read()
900 for (i = 0; length; i += 4, length -= 4) { in tg3_ape_scratchpad_read()
907 return 0; in tg3_ape_scratchpad_read()
935 return 0; in tg3_ape_send_event()
1004 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1005 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1012 tp->irq_sync = 0; in tg3_enable_ints()
1019 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1031 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1036 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1043 unsigned int work_exists = 0; in tg3_has_work()
1052 if (sblk->idx[0].tx_consumer != tnapi->tx_cons) in tg3_has_work()
1096 0x1f); in tg3_switch_clocks()
1104 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { in tg3_switch_clocks()
1125 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1133 *val = 0x0; in __tg3_readphy()
1144 while (loops != 0) { in __tg3_readphy()
1148 if ((frame_val & MI_COM_BUSY) == 0) { in __tg3_readphy()
1157 if (loops != 0) { in __tg3_readphy()
1159 ret = 0; in __tg3_readphy()
1162 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1186 return 0; in __tg3_writephy()
1188 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1206 while (loops != 0) { in __tg3_writephy()
1209 if ((frame_val & MI_COM_BUSY) == 0) { in __tg3_writephy()
1218 if (loops != 0) in __tg3_writephy()
1219 ret = 0; in __tg3_writephy()
1221 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1362 if (err != 0) in tg3_bmcr_reset()
1368 if (err != 0) in tg3_bmcr_reset()
1371 if ((phy_control & BMCR_RESET) == 0) { in tg3_bmcr_reset()
1377 if (limit < 0) in tg3_bmcr_reset()
1380 return 0; in tg3_bmcr_reset()
1401 u32 ret = 0; in tg3_mdio_write()
1527 if (addr < 0) in tg3_mdio_init()
1536 return 0; in tg3_mdio_init()
1560 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1602 return 0; in tg3_mdio_init()
1639 if (time_remain < 0) in tg3_wait_for_event_ack()
1648 for (i = 0; i < delay_cnt; i++) { in tg3_wait_for_event_ack()
1663 val = 0; in tg3_phy_gather_ump_data()
1667 val |= (reg & 0xffff); in tg3_phy_gather_ump_data()
1670 val = 0; in tg3_phy_gather_ump_data()
1674 val |= (reg & 0xffff); in tg3_phy_gather_ump_data()
1677 val = 0; in tg3_phy_gather_ump_data()
1682 val |= (reg & 0xffff); in tg3_phy_gather_ump_data()
1689 val = 0; in tg3_phy_gather_ump_data()
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); in tg3_ump_link_report()
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); in tg3_ump_link_report()
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); in tg3_ump_link_report()
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); in tg3_ump_link_report()
1813 return 0; in tg3_poll_fw()
1817 return 0; in tg3_poll_fw()
1822 for (i = 0; i < 200; i++) { in tg3_poll_fw()
1824 return 0; in tg3_poll_fw()
1834 for (i = 0; i < 100000; i++) { in tg3_poll_fw()
1868 return 0; in tg3_poll_fw()
1903 u32 flowctrl = 0; in tg3_decode_flowctrl_1000T()
1926 miireg = 0; in tg3_advert_flowctrl_1000X()
1933 u32 flowctrl = 0; in tg3_decode_flowctrl_1000X()
1947 u8 cap = 0; in tg3_resolve_flowctrl_1000X()
1964 u8 flowctrl = 0; in tg3_setup_flow_control()
2002 u8 oldflowctrl, linkmesg = 0; in tg3_adjust_link()
2015 lcl_adv = 0; in tg3_adjust_link()
2016 rmt_adv = 0; in tg3_adjust_link()
2061 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); in tg3_adjust_link()
2089 return 0; in tg3_phy_init()
2127 return 0; in tg3_phy_init()
2175 return 0; in tg3_phy_set_extloopbk()
2182 0x4c20); in tg3_phy_set_extloopbk()
2361 dest->eee_active = 0; in tg3_eee_pull_config()
2379 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2389 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2413 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); in tg3_phy_eee_adjust()
2449 if ((tmp32 & 0x1000) == 0) in tg3_wait_macro_done()
2453 if (limit < 0) in tg3_wait_macro_done()
2456 return 0; in tg3_wait_macro_done()
2462 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, in tg3_phy_write_and_check_testpat()
2463 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, in tg3_phy_write_and_check_testpat()
2464 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, in tg3_phy_write_and_check_testpat()
2465 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } in tg3_phy_write_and_check_testpat()
2469 for (chan = 0; chan < 4; chan++) { in tg3_phy_write_and_check_testpat()
2473 (chan * 0x2000) | 0x0200); in tg3_phy_write_and_check_testpat()
2474 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2476 for (i = 0; i < 6; i++) in tg3_phy_write_and_check_testpat()
2480 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2487 (chan * 0x2000) | 0x0200); in tg3_phy_write_and_check_testpat()
2488 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2494 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2500 for (i = 0; i < 6; i += 2) { in tg3_phy_write_and_check_testpat()
2509 low &= 0x7fff; in tg3_phy_write_and_check_testpat()
2510 high &= 0x000f; in tg3_phy_write_and_check_testpat()
2513 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2515 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2522 return 0; in tg3_phy_write_and_check_testpat()
2529 for (chan = 0; chan < 4; chan++) { in tg3_phy_reset_chanpat()
2533 (chan * 0x2000) | 0x0200); in tg3_phy_reset_chanpat()
2534 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2535 for (i = 0; i < 6; i++) in tg3_phy_reset_chanpat()
2536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2542 return 0; in tg3_phy_reset_chanpat()
2557 do_phy_reset = 0; in tg3_phy_reset_5703_4_5()
2564 reg32 |= 0x3000; in tg3_phy_reset_5703_4_5()
2583 tg3_phydsp_write(tp, 0x8005, 0x0800); in tg3_phy_reset_5703_4_5()
2594 tg3_phydsp_write(tp, 0x8005, 0x0000); in tg3_phy_reset_5703_4_5()
2596 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2597 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2607 reg32 &= ~0x3000; in tg3_phy_reset_5703_4_5()
2610 return 0; in tg3_phy_reset_5703_4_5()
2641 if (err != 0) in tg3_phy_reset()
2658 cpmuctrl = 0; in tg3_phy_reset()
2691 return 0; in tg3_phy_reset()
2703 tg3_phydsp_write(tp, 0x201f, 0x2aaa); in tg3_phy_reset()
2704 tg3_phydsp_write(tp, 0x000a, 0x0323); in tg3_phy_reset()
2709 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2710 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2715 tg3_phydsp_write(tp, 0x000a, 0x310b); in tg3_phy_reset()
2716 tg3_phydsp_write(tp, 0x201f, 0x9506); in tg3_phy_reset()
2717 tg3_phydsp_write(tp, 0x401f, 0x14e2); in tg3_phy_reset()
2722 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2724 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2726 MII_TG3_TEST1_TRIM_EN | 0x4); in tg3_phy_reset()
2728 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2738 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_phy_reset()
2748 /* Set phy register 0x10 bit 0 to high fifo elasticity to support in tg3_phy_reset()
2759 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
2763 tg3_phydsp_write(tp, 0xffb, 0x4000); in tg3_phy_reset()
2767 return 0; in tg3_phy_reset()
2770 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2771 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2781 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2812 return 0; in tg3_pwrsrc_switch_to_vmain()
2831 return 0; in tg3_pwrsrc_switch_to_vmain()
2874 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ in tg3_pwrsrc_switch_to_vaux()
2893 u32 grc_local_ctrl = 0; in tg3_pwrsrc_switch_to_vaux()
2937 u32 msg = 0; in tg3_frob_aux_power_5717()
2972 tg3_flag(tp, WOL_ENABLE) != 0 : 0); in tg3_frob_aux_power()
3014 return 0; in tg3_5700_link_polarity()
3087 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3136 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3138 for (i = 0; i < 8000; i++) { in tg3_nvram_lock()
3150 return 0; in tg3_nvram_lock()
3157 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3159 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3190 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) in tg3_nvram_read_using_eeprom()
3198 (0 << EEPROM_ADDR_DEVID_SHIFT) | in tg3_nvram_read_using_eeprom()
3203 for (i = 0; i < 1000; i++) { in tg3_nvram_read_using_eeprom()
3221 return 0; in tg3_nvram_read_using_eeprom()
3231 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { in tg3_nvram_exec_cmd()
3242 return 0; in tg3_nvram_exec_cmd()
3303 if (ret == 0) in tg3_nvram_read()
3326 int i, j, rc = 0; in tg3_nvram_write_block_using_eeprom()
3329 for (i = 0; i < len; i += 4) { in tg3_nvram_write_block_using_eeprom()
3351 (0 << EEPROM_ADDR_DEVID_SHIFT) | in tg3_nvram_write_block_using_eeprom()
3356 for (j = 0; j < 1000; j++) { in tg3_nvram_write_block_using_eeprom()
3376 int ret = 0; in tg3_nvram_write_block_unbuffered()
3392 for (j = 0; j < pagesize; j += 4) { in tg3_nvram_write_block_unbuffered()
3438 for (j = 0; j < pagesize; j += 4) { in tg3_nvram_write_block_unbuffered()
3450 if (j == 0) in tg3_nvram_write_block_unbuffered()
3475 int i, ret = 0; in tg3_nvram_write_block_buffered()
3477 for (i = 0; i < len; i += 4, offset += 4) { in tg3_nvram_write_block_buffered()
3490 if (page_off == 0 || i == 0) in tg3_nvram_write_block_buffered()
3548 tw32(NVRAM_WRITE1, 0x406); in tg3_nvram_write_block()
3576 #define RX_CPU_SCRATCH_BASE 0x30000
3577 #define RX_CPU_SCRATCH_SIZE 0x04000
3578 #define TX_CPU_SCRATCH_BASE 0x34000
3579 #define TX_CPU_SCRATCH_SIZE 0x04000
3587 for (i = 0; i < iters; i++) { in tg3_pause_cpu()
3588 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_pause_cpu()
3596 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu()
3604 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); in tg3_rxcpu_pause()
3620 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_resume_cpu()
3621 tw32_f(cpu_base + CPU_MODE, 0x00000000); in tg3_resume_cpu()
3641 return 0; in tg3_halt_cpu()
3651 return 0; in tg3_halt_cpu()
3665 return 0; in tg3_halt_cpu()
3682 * the main header, the length field is unused and set to 0xffffffff. in tg3_fw_data_len()
3687 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3727 for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) in tg3_load_firmware_cpu()
3728 write_op(tp, cpu_scratch_base + i, 0); in tg3_load_firmware_cpu()
3729 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_load_firmware_cpu()
3742 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++) in tg3_load_firmware_cpu()
3744 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + in tg3_load_firmware_cpu()
3753 } while (total_len > 0); in tg3_load_firmware_cpu()
3755 err = 0; in tg3_load_firmware_cpu()
3767 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_pause_cpu_and_set_pc()
3770 for (i = 0; i < iters; i++) { in tg3_pause_cpu_and_set_pc()
3773 tw32(cpu_base + CPU_STATE, 0xffffffff); in tg3_pause_cpu_and_set_pc()
3779 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu_and_set_pc()
3821 return 0; in tg3_load_5701_a0_firmware_fix()
3833 for (i = 0; i < iters; i++) { in tg3_validate_rxcpu_state()
3846 if (val & 0xff) { in tg3_validate_rxcpu_state()
3852 return 0; in tg3_validate_rxcpu_state()
3875 * here is unused and set to 0xffffffff. in tg3_load_57766_firmware()
3891 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr); in tg3_load_57766_firmware()
3904 return 0; in tg3_load_tso_firmware()
3943 return 0; in tg3_load_tso_firmware()
3952 addr_high = ((mac_addr[0] << 8) | mac_addr[1]); in __tg3_set_one_mac_addr()
3972 for (i = 0; i < 4; i++) { in __tg3_set_mac_addr()
3984 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
4046 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising) = { 0, }; in tg3_power_down_prepare()
4114 for (i = 0; i < 200; i++) { in tg3_power_down_prepare()
4249 u32 val = tr32(0x7d00); in tg3_power_down_prepare()
4252 tw32(0x7d00, val); in tg3_power_down_prepare()
4325 int err = 0; in tg3_phy_autoneg_cfg()
4359 val = 0; in tg3_phy_autoneg_cfg()
4366 val = 0; in tg3_phy_autoneg_cfg()
4454 bmcr = 0; in tg3_phy_copper_begin()
4475 for (i = 0; i < 1500; i++) { in tg3_phy_copper_begin()
4504 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4510 case 0: in tg3_phy_pull_config()
4539 err = 0; in tg3_phy_pull_config()
4596 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_init_5401phy_dsp()
4598 err |= tg3_phydsp_write(tp, 0x0012, 0x1804); in tg3_init_5401phy_dsp()
4599 err |= tg3_phydsp_write(tp, 0x0013, 0x1204); in tg3_init_5401phy_dsp()
4600 err |= tg3_phydsp_write(tp, 0x8006, 0x0132); in tg3_init_5401phy_dsp()
4601 err |= tg3_phydsp_write(tp, 0x8006, 0x0232); in tg3_init_5401phy_dsp()
4602 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); in tg3_init_5401phy_dsp()
4678 u32 lpeth = 0; in tg3_phy_copper_fetch_rmtadv()
4718 tw32(MAC_EVENT, 0); in tg3_clear_mac_status()
4743 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4753 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4757 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4775 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4781 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); in tg3_setup_copper_phy()
4802 bmsr = 0; in tg3_setup_copper_phy()
4810 for (i = 0; i < 1000; i++) { in tg3_setup_copper_phy()
4833 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4834 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4835 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4836 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4846 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4854 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
4861 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4875 bmsr = 0; in tg3_setup_copper_phy()
4876 for (i = 0; i < 100; i++) { in tg3_setup_copper_phy()
4888 for (i = 0; i < 2000; i++) { in tg3_setup_copper_phy()
4899 bmcr = 0; in tg3_setup_copper_phy()
4900 for (i = 0; i < 200; i++) { in tg3_setup_copper_phy()
4904 if (bmcr && bmcr != 0x7fff) in tg3_setup_copper_phy()
4909 lcl_adv = 0; in tg3_setup_copper_phy()
4910 rmt_adv = 0; in tg3_setup_copper_phy()
5041 tw32_f(MAC_EVENT, 0); in tg3_setup_copper_phy()
5074 return 0; in tg3_setup_copper_phy()
5079 #define ANEG_STATE_UNKNOWN 0
5097 #define MR_AN_ENABLE 0x00000001
5098 #define MR_RESTART_AN 0x00000002
5099 #define MR_AN_COMPLETE 0x00000004
5100 #define MR_PAGE_RX 0x00000008
5101 #define MR_NP_LOADED 0x00000010
5102 #define MR_TOGGLE_TX 0x00000020
5103 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5104 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5105 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5106 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5107 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5108 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5109 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5110 #define MR_TOGGLE_RX 0x00002000
5111 #define MR_NP_RX 0x00004000
5113 #define MR_LINK_OK 0x80000000
5123 #define ANEG_CFG_NP 0x00000080
5124 #define ANEG_CFG_ACK 0x00000040
5125 #define ANEG_CFG_RF2 0x00000020
5126 #define ANEG_CFG_RF1 0x00000010
5127 #define ANEG_CFG_PS2 0x00000001
5128 #define ANEG_CFG_PS1 0x00008000
5129 #define ANEG_CFG_HD 0x00004000
5130 #define ANEG_CFG_FD 0x00002000
5131 #define ANEG_CFG_INVAL 0x00001f06
5134 #define ANEG_OK 0
5150 ap->rxconfig = 0; in tg3_fiber_aneg_smachine()
5151 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5152 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5153 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5154 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5155 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5156 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5157 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5166 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5167 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5177 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5179 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5182 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5183 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5184 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5185 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5187 rx_cfg_reg = 0; in tg3_fiber_aneg_smachine()
5202 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5203 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5204 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5205 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5206 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5207 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5208 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5219 ap->txconfig = 0; in tg3_fiber_aneg_smachine()
5220 tw32(MAC_TX_AUTO_NEG, 0); in tg3_fiber_aneg_smachine()
5258 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
5273 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
5280 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5281 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5318 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
5329 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5330 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5339 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
5360 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5361 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5395 int res = 0; in fiber_autoneg()
5401 tw32_f(MAC_TX_AUTO_NEG, 0); in fiber_autoneg()
5410 memset(&aninfo, 0, sizeof(aninfo)); in fiber_autoneg()
5413 aninfo.cur_time = 0; in fiber_autoneg()
5414 tick = 0; in fiber_autoneg()
5449 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5456 for (i = 0; i < 500; i++) in tg3_init_bcm8002()
5460 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5463 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5465 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5466 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5469 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5471 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5473 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5475 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5479 for (i = 0; i < 15000; i++) in tg3_init_bcm8002()
5485 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5496 serdes_cfg = 0; in tg3_setup_fiber_hw_autoneg()
5497 workaround = 0; in tg3_setup_fiber_hw_autoneg()
5505 port_a = 0; in tg3_setup_fiber_hw_autoneg()
5507 /* preserve bits 0-11,13,14 for signal pre-emphasis */ in tg3_setup_fiber_hw_autoneg()
5509 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; in tg3_setup_fiber_hw_autoneg()
5520 val |= 0xc010000; in tg3_setup_fiber_hw_autoneg()
5522 val |= 0x4010000; in tg3_setup_fiber_hw_autoneg()
5529 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5556 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); in tg3_setup_fiber_hw_autoneg()
5570 u32 local_adv = 0, remote_adv = 0; in tg3_setup_fiber_hw_autoneg()
5587 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5597 val |= 0xc010000; in tg3_setup_fiber_hw_autoneg()
5599 val |= 0x4010000; in tg3_setup_fiber_hw_autoneg()
5613 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5644 u32 local_adv = 0, remote_adv = 0; in tg3_setup_fiber_by_hand()
5663 for (i = 0; i < 30; i++) { in tg3_setup_fiber_by_hand()
5671 MAC_STATUS_CFG_CHANGED)) == 0) in tg3_setup_fiber_by_hand()
5681 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_by_hand()
5722 return 0; in tg3_setup_fiber_phy()
5726 tw32_f(MAC_TX_AUTO_NEG, 0); in tg3_setup_fiber_phy()
5740 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5748 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5750 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5752 for (i = 0; i < 100; i++) { in tg3_setup_fiber_phy()
5758 MAC_STATUS_LNKSTATE_CHANGED)) == 0) in tg3_setup_fiber_phy()
5763 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { in tg3_setup_fiber_phy()
5766 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5796 return 0; in tg3_setup_fiber_phy()
5801 int err = 0; in tg3_setup_fiber_mii_phy()
5856 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5947 local_adv = 0; in tg3_setup_fiber_mii_phy()
5948 remote_adv = 0; in tg3_setup_fiber_mii_phy()
6009 /* Select shadow register 0x1f */ in tg3_serdes_parallel_detect()
6010 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6019 if ((phy1 & 0x10) && !(phy2 & 0x20)) { in tg3_serdes_parallel_detect()
6040 if (phy2 & 0x20) { in tg3_serdes_parallel_detect()
6092 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)); in tg3_setup_phy()
6102 tw32(HOSTCC_STAT_COAL_TICKS, 0); in tg3_setup_phy()
6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff); in tg3_refclk_write()
6166 return 0; in tg3_get_ts_info()
6182 tg3_full_lock(tp, 0); in tg3_ptp_adjfine()
6187 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | in tg3_ptp_adjfine()
6190 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0); in tg3_ptp_adjfine()
6194 return 0; in tg3_ptp_adjfine()
6201 tg3_full_lock(tp, 0); in tg3_ptp_adjtime()
6205 return 0; in tg3_ptp_adjtime()
6214 tg3_full_lock(tp, 0); in tg3_ptp_gettimex()
6221 return 0; in tg3_ptp_gettimex()
6232 tg3_full_lock(tp, 0); in tg3_ptp_settime()
6234 tp->ptp_adjust = 0; in tg3_ptp_settime()
6237 return 0; in tg3_ptp_settime()
6245 int rval = 0; in tg3_ptp_enable()
6253 if (rq->perout.index != 0) in tg3_ptp_enable()
6256 tg3_full_lock(tp, 0); in tg3_ptp_enable()
6268 "Device supports only a one-shot timesync output, period must be 0\n"); in tg3_ptp_enable()
6280 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff)); in tg3_ptp_enable()
6288 tw32(TG3_EAV_WATCHDOG0_MSB, 0); in tg3_ptp_enable()
6306 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps)); in tg3_hwclock_to_timestamp()
6338 tp->ptp_txts_retrycnt = 0; in tg3_ptp_ts_aux_work()
6339 tp->pre_tx_ts = 0; in tg3_ptp_ts_aux_work()
6347 .n_alarm = 0,
6348 .n_ext_ts = 0,
6350 .n_pins = 0,
6351 .pps = 0,
6368 tp->ptp_adjust = 0; in tg3_ptp_init()
6379 tp->ptp_adjust = 0; in tg3_ptp_resume()
6389 tp->ptp_adjust = 0; in tg3_ptp_fini()
6404 for (i = 0; i < len; i += sizeof(u32)) in tg3_rd32_loop()
6410 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); in tg3_dump_legacy_regs()
6411 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); in tg3_dump_legacy_regs()
6412 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); in tg3_dump_legacy_regs()
6413 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); in tg3_dump_legacy_regs()
6414 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); in tg3_dump_legacy_regs()
6415 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); in tg3_dump_legacy_regs()
6416 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); in tg3_dump_legacy_regs()
6417 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); in tg3_dump_legacy_regs()
6418 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); in tg3_dump_legacy_regs()
6419 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); in tg3_dump_legacy_regs()
6420 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); in tg3_dump_legacy_regs()
6421 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); in tg3_dump_legacy_regs()
6422 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); in tg3_dump_legacy_regs()
6423 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); in tg3_dump_legacy_regs()
6424 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); in tg3_dump_legacy_regs()
6425 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); in tg3_dump_legacy_regs()
6426 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); in tg3_dump_legacy_regs()
6427 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); in tg3_dump_legacy_regs()
6428 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); in tg3_dump_legacy_regs()
6431 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); in tg3_dump_legacy_regs()
6433 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); in tg3_dump_legacy_regs()
6434 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); in tg3_dump_legacy_regs()
6435 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6436 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6437 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6438 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6439 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6440 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); in tg3_dump_legacy_regs()
6443 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6444 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6445 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6448 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); in tg3_dump_legacy_regs()
6449 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); in tg3_dump_legacy_regs()
6450 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); in tg3_dump_legacy_regs()
6451 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); in tg3_dump_legacy_regs()
6452 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); in tg3_dump_legacy_regs()
6455 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); in tg3_dump_legacy_regs()
6463 /* If it is a PCI error, all registers will be 0xffff, in tg3_dump_state()
6477 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32)) in tg3_dump_state()
6482 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) { in tg3_dump_state()
6483 if (!regs[i + 0] && !regs[i + 1] && in tg3_dump_state()
6487 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6489 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]); in tg3_dump_state()
6494 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6506 tnapi->hw_status->idx[0].rx_producer, in tg3_dump_state()
6507 tnapi->hw_status->idx[0].tx_consumer); in tg3_dump_state()
6557 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_tx()
6561 unsigned int pkts_compl = 0, bytes_compl = 0; in tg3_tx()
6572 int i, tx_bug = 0; in tg3_tx()
6587 tp->pre_tx_ts = 0; in tg3_tx()
6607 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in tg3_tx()
6632 ptp_schedule_worker(tp->ptp_clock, 0); in tg3_tx()
6684 /* Returns size of skb allocated or < 0 on error.
6737 *frag_size = 0; in tg3_alloc_rx_data()
6753 desc->addr_lo = ((u64)mapping & 0xffffffff); in tg3_alloc_rx_data()
6770 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6835 u32 work_mask, rx_std_posted = 0; in tg3_rx()
6848 work_mask = 0; in tg3_rx()
6849 received = 0; in tg3_rx()
6852 while (sw_idx != hw_idx && budget > 0) { in tg3_rx()
6860 u64 tstamp = 0; in tg3_rx()
6865 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6871 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6908 if (skb_size < 0) in tg3_rx()
6926 tg3_frag_free(frag_size != 0, data); in tg3_rx()
6957 >> RXD_TCPCSUM_SHIFT) == 0xffff)) in tg3_rx()
6990 rx_std_posted = 0; in tg3_rx()
7046 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7071 int i, err = 0; in tg3_rx_prodring_xfer()
7117 for (i = 0; i < cpycnt; i++, di++, si++) { in tg3_rx_prodring_xfer()
7175 for (i = 0; i < cpycnt; i++, di++, si++) { in tg3_rx_prodring_xfer()
7197 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
7214 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7215 int i, err = 0; in tg3_poll_work()
7258 int work_done = 0; in tg3_poll_msix()
7279 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
7352 int work_done = 0; in tg3_poll()
7404 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_napi_disable()
7422 int txq_idx = 0, rxq_idx = 0; in tg3_napi_enable()
7426 for (i = 0; i < tp->irq_cnt; i++) { in tg3_napi_enable()
7448 for (i = 0; i < tp->irq_cnt; i++) { in tg3_napi_init()
7460 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7487 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7504 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7558 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_msi()
7560 * Writing non-zero to intr-mbox-0 additional tells the in tg3_msi()
7564 tw32_mailbox(tnapi->int_mbox, 0x00000001); in tg3_msi()
7586 handled = 0; in tg3_interrupt()
7592 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt()
7594 * Writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt()
7602 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); in tg3_interrupt()
7614 0x00000000); in tg3_interrupt()
7635 handled = 0; in tg3_interrupt_tagged()
7641 * writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt_tagged()
7643 * writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt_tagged()
7651 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); in tg3_interrupt_tagged()
7684 return IRQ_RETVAL(0); in tg3_test_isr()
7696 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7716 u32 base = (u32) mapping & 0xffffffff; in tg3_4g_overflow_test()
7728 u32 base = (u32) mapping & 0xffffffff; in tg3_4g_tso_overflow_test()
7730 return ((base + len + (mss & 0x3fff)) < base); in tg3_4g_tso_overflow_test()
7732 return 0; in tg3_4g_tso_overflow_test()
7742 return 0; in tg3_40bit_overflow_test()
7744 return 0; in tg3_40bit_overflow_test()
7753 txbd->addr_lo = ((u64) mapping & 0xffffffff); in tg3_tx_set_bd()
7754 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); in tg3_tx_set_bd()
7839 for (i = 0; i <= last; i++) { in tg3_tx_skb_unmap()
7865 dma_addr_t new_addr = 0; in tigon3_dma_hwbug_workaround()
7866 int ret = 0; in tigon3_dma_hwbug_workaround()
7969 u32 len, entry, base_flags, mss, vlan = 0; in __tg3_start_xmit()
7978 __sum16 tcp_csum = 0, ip_csum = 0; in __tg3_start_xmit()
7979 __be16 ip_tot_len = 0; in __tg3_start_xmit()
8005 base_flags = 0; in __tg3_start_xmit()
8011 if (skb_cow_head(skb, 0)) in __tg3_start_xmit()
8038 iph->check = 0; in __tg3_start_xmit()
8051 tcph->check = 0; in __tg3_start_xmit()
8055 0, IPPROTO_TCP, 0); in __tg3_start_xmit()
8059 mss |= (hdr_len & 0xc) << 12; in __tg3_start_xmit()
8060 if (hdr_len & 0x10) in __tg3_start_xmit()
8061 base_flags |= 0x00000010; in __tg3_start_xmit()
8062 base_flags |= (hdr_len & 0x3e0) << 5; in __tg3_start_xmit()
8105 tg3_full_lock(tp, 0); in __tg3_start_xmit()
8125 would_hit_hwbug = 0; in __tg3_start_xmit()
8131 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), in __tg3_start_xmit()
8134 } else if (skb_shinfo(skb)->nr_frags > 0) { in __tg3_start_xmit()
8140 tmp_mss = 0; in __tg3_start_xmit()
8146 for (i = 0; i <= last; i++) { in __tg3_start_xmit()
8150 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in __tg3_start_xmit()
8162 ((i == last) ? TXD_FLAG_END : 0), in __tg3_start_xmit()
8293 u32 val, bmcr, mac_mode, ptest = 0; in tg3_phy_lpbk_set()
8381 return 0; in tg3_phy_lpbk_set()
8428 return 0; in tg3_set_features()
8436 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8454 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8459 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8477 tpr->rx_std_cons_idx = 0; in tg3_rx_prodring_alloc()
8478 tpr->rx_std_prod_idx = 0; in tg3_rx_prodring_alloc()
8479 tpr->rx_jmb_cons_idx = 0; in tg3_rx_prodring_alloc()
8480 tpr->rx_jmb_prod_idx = 0; in tg3_rx_prodring_alloc()
8482 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8483 memset(&tpr->rx_std_buffers[0], 0, in tg3_rx_prodring_alloc()
8486 memset(&tpr->rx_jmb_buffers[0], 0, in tg3_rx_prodring_alloc()
8492 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8504 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8515 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8519 &frag_size) < 0) { in tg3_rx_prodring_alloc()
8524 if (i == 0) in tg3_rx_prodring_alloc()
8534 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8539 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8550 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8554 &frag_size) < 0) { in tg3_rx_prodring_alloc()
8559 if (i == 0) in tg3_rx_prodring_alloc()
8567 return 0; in tg3_rx_prodring_alloc()
8622 return 0; in tg3_rx_prodring_init()
8640 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8648 for (i = 0; i < TG3_TX_RING_SIZE; i++) { in tg3_free_rings()
8677 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8680 tnapi->last_tag = 0; in tg3_init_rings()
8681 tnapi->last_irq_tag = 0; in tg3_init_rings()
8682 tnapi->hw_status->status = 0; in tg3_init_rings()
8683 tnapi->hw_status->status_tag = 0; in tg3_init_rings()
8684 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_init_rings()
8686 tnapi->tx_prod = 0; in tg3_init_rings()
8687 tnapi->tx_cons = 0; in tg3_init_rings()
8689 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); in tg3_init_rings()
8691 tnapi->rx_rcb_ptr = 0; in tg3_init_rings()
8693 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8702 return 0; in tg3_init_rings()
8709 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8726 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8728 /* If multivector TSS is enabled, vector 0 does not handle in tg3_mem_tx_acquire()
8734 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8749 return 0; in tg3_mem_tx_acquire()
8760 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8788 for (i = 0; i < limit; i++) { in tg3_mem_rx_acquire()
8794 /* If multivector RSS is enabled, vector 0 in tg3_mem_rx_acquire()
8809 return 0; in tg3_mem_rx_acquire()
8824 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8863 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8887 prodptr = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8901 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8908 return 0; in tg3_alloc_consistent()
8935 return 0; in tg3_stop_block()
8946 for (i = 0; i < MAX_WAIT_CNT; i++) { in tg3_stop_block()
8957 if ((val & enable_bit) == 0) in tg3_stop_block()
8968 return 0; in tg3_stop_block()
9011 for (i = 0; i < MAX_WAIT_CNT; i++) { in tg3_abort_hw()
9027 tw32(FTQ_RESET, 0xffffffff); in tg3_abort_hw()
9028 tw32(FTQ_RESET, 0x00000000); in tg3_abort_hw()
9034 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
9037 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
9172 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9182 tw32(GRC_FASTBOOT_PC, 0); in tg3_chip_reset()
9201 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9204 tnapi->hw_status->status = 0; in tg3_chip_reset()
9205 tnapi->hw_status->status_tag = 0; in tg3_chip_reset()
9207 tnapi->last_tag = 0; in tg3_chip_reset()
9208 tnapi->last_irq_tag = 0; in tg3_chip_reset()
9214 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9217 tg3_full_lock(tp, 0); in tg3_chip_reset()
9296 for (j = 0; j < 5000; j++) in tg3_chip_reset()
9299 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9300 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9327 val = 0; in tg3_chip_reset()
9334 tw32(0x5000, 0x400); in tg3_chip_reset()
9354 val = tr32(0xc4); in tg3_chip_reset()
9356 tw32(0xc4, val | (1 << 15)); in tg3_chip_reset()
9359 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9374 val = 0; in tg3_chip_reset()
9387 val = tr32(0x7c00); in tg3_chip_reset()
9389 tw32(0x7c00, val | (1 << 25)); in tg3_chip_reset()
9428 return 0; in tg3_chip_reset()
9458 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9460 for (i = 0; i < TG3_IRQ_MAX_VECS; ++i) { in tg3_halt()
9463 tnapi->rx_dropped = 0; in tg3_halt()
9464 tnapi->tx_dropped = 0; in tg3_halt()
9475 int err = 0; in tg3_set_mac_addr()
9484 return 0; in tg3_set_mac_addr()
9496 !(addr1_high == 0 && addr1_low == 0)) in tg3_set_mac_addr()
9517 ((u64) mapping & 0xffffffff)); in tg3_set_bdinfo()
9531 int i = 0; in tg3_coal_tx_init()
9538 tw32(HOSTCC_TXCOL_TICKS, 0); in tg3_coal_tx_init()
9539 tw32(HOSTCC_TXMAX_FRAMES, 0); in tg3_coal_tx_init()
9540 tw32(HOSTCC_TXCOAL_MAXF_INT, 0); in tg3_coal_tx_init()
9545 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; in tg3_coal_tx_init()
9547 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; in tg3_coal_tx_init()
9549 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; in tg3_coal_tx_init()
9555 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); in tg3_coal_tx_init()
9556 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); in tg3_coal_tx_init()
9557 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); in tg3_coal_tx_init()
9563 int i = 0; in tg3_coal_rx_init()
9572 tw32(HOSTCC_RXCOL_TICKS, 0); in tg3_coal_rx_init()
9573 tw32(HOSTCC_RXMAX_FRAMES, 0); in tg3_coal_rx_init()
9574 tw32(HOSTCC_RXCOAL_MAXF_INT, 0); in tg3_coal_rx_init()
9580 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; in tg3_coal_rx_init()
9582 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; in tg3_coal_rx_init()
9584 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; in tg3_coal_rx_init()
9589 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); in tg3_coal_rx_init()
9590 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); in tg3_coal_rx_init()
9591 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); in tg3_coal_rx_init()
9607 val = 0; in __tg3_set_coalesce()
9638 int i = 0; in tg3_tx_rcbs_init()
9682 int i = 0; in tg3_rx_ret_rcbs_init()
9696 BDINFO_FLAGS_MAXLEN_SHIFT, 0); in tg3_rx_ret_rcbs_init()
9705 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9712 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9713 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9714 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9715 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9720 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9721 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9723 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9724 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9726 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9727 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9728 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9731 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9733 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9734 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9735 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9736 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9742 for (i = 0; i < 16; i++) in tg3_rings_reset()
9743 tw32_tx_mbox(mbox + i * 8, 0); in tg3_rings_reset()
9747 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9753 ((u64) tnapi->status_mapping & 0xffffffff)); in tg3_rings_reset()
9760 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); in tg3_rings_reset()
9764 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9816 reg = 0xffffffff; in calc_crc()
9818 for (j = 0; j < len; j++) { in calc_crc()
9821 for (k = 0; k < 8; k++) { in calc_crc()
9822 tmp = reg & 0x01; in calc_crc()
9837 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); in tg3_set_multi()
9838 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); in tg3_set_multi()
9839 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); in tg3_set_multi()
9840 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); in tg3_set_multi()
9867 tg3_set_multi(tp, 0); in __tg3_set_rx_mode()
9871 u32 mc_filter[4] = { 0, }; in __tg3_set_rx_mode()
9878 bit = ~crc & 0x7f; in __tg3_set_rx_mode()
9879 regidx = (bit & 0x60) >> 5; in __tg3_set_rx_mode()
9880 bit &= 0x1f; in __tg3_set_rx_mode()
9884 tw32(MAC_HASH_REG_0, mc_filter[0]); in __tg3_set_rx_mode()
9894 int i = 0; in __tg3_set_rx_mode()
9915 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) in tg3_rss_init_dflt_indir_tbl()
9927 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9932 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { in tg3_rss_check_indir_tbl()
9943 int i = 0; in tg3_rss_write_indir_tbl()
9971 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
10196 val &= ~0xff; in tg3_reset_hw()
10215 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); in tg3_reset_hw()
10219 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); in tg3_reset_hw()
10251 for (i = 0; i < 2000; i++) { in tg3_reset_hw()
10262 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); in tg3_reset_hw()
10286 ((u64) tpr->rx_std_mapping & 0xffffffff)); in tg3_reset_hw()
10306 ((u64) tpr->rx_jmb_mapping & 0xffffffff)); in tg3_reset_hw()
10336 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10365 tw32(RCVLPC_CONFIG, 0x0181); in tg3_reset_hw()
10400 tp->dma_limit = 0; in tg3_reset_hw()
10473 tw32(RCVLPC_STATS_ENABLE, 0xffffff); in tg3_reset_hw()
10476 tw32(SNDDATAI_STATSENAB, 0xffffff); in tg3_reset_hw()
10482 tw32(HOSTCC_MODE, 0); in tg3_reset_hw()
10483 for (i = 0; i < 2000; i++) { in tg3_reset_hw()
10499 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10508 tg3_write_mem(tp, i, 0); in tg3_reset_hw()
10634 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) { in tg3_reset_hw()
10666 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); in tg3_reset_hw()
10715 for (i = 0; i < 10 ; i++) in tg3_reset_hw()
10753 val &= 0xfffff000; in tg3_reset_hw()
10754 val |= 0x880; in tg3_reset_hw()
10758 tw32(MAC_SERDES_CFG, 0x616000); in tg3_reset_hw()
10811 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); in tg3_reset_hw()
10812 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); in tg3_reset_hw()
10813 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); in tg3_reset_hw()
10814 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); in tg3_reset_hw()
10824 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); in tg3_reset_hw()
10827 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); in tg3_reset_hw()
10830 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); in tg3_reset_hw()
10833 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); in tg3_reset_hw()
10836 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); in tg3_reset_hw()
10839 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); in tg3_reset_hw()
10842 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); in tg3_reset_hw()
10845 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); in tg3_reset_hw()
10848 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); in tg3_reset_hw()
10851 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); in tg3_reset_hw()
10854 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); in tg3_reset_hw()
10857 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); in tg3_reset_hw()
10860 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ in tg3_reset_hw()
10862 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ in tg3_reset_hw()
10877 return 0; in tg3_reset_hw()
10894 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_init_hw()
10905 for (i = 0, off = 0; i < TG3_SD_NUM_RECS; i++, ocir++, off += len) { in tg3_sd_scan_scratchpad()
10910 memset(ocir, 0, len); in tg3_sd_scan_scratchpad()
10956 u32 size = 0; in tg3_hwmon_open()
10962 for (i = 0; i < TG3_SD_NUM_RECS; i++) { in tg3_hwmon_open()
10991 } while (0)
11047 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0; in tg3_periodic_fetch_stats()
11063 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
11073 tg3_msi(0, tnapi); in tg3_chk_missed_msi()
11076 tnapi->chk_msi_cnt = 0; in tg3_chk_missed_msi()
11107 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11136 phy_event = 0; in tg3_timer()
11147 int need_setup = 0; in tg3_timer()
11241 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11276 tp->irq_sync = 0; in tg3_restart_hw()
11281 tg3_full_lock(tp, 0); in tg3_restart_hw()
11292 tg3_full_lock(tp, 0); in tg3_reset_task()
11318 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_reset_task()
11322 tp->irq_sync = 0; in tg3_reset_task()
11352 name = &tnapi->irq_lbl[0]; in tg3_request_irq()
11371 flags = 0; in tg3_request_irq()
11384 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11386 int err, i, intr_ok = 0; in tg3_test_interrupt()
11416 for (i = 0; i < 5; i++) { in tg3_test_interrupt()
11422 if ((int_mbox != 0) || in tg3_test_interrupt()
11439 err = tg3_request_irq(tp, 0); in tg3_test_interrupt()
11450 return 0; in tg3_test_interrupt()
11456 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11465 return 0; in tg3_test_msi()
11479 return 0; in tg3_test_msi()
11490 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11495 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11497 err = tg3_request_irq(tp, 0); in tg3_test_msi()
11512 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11545 return 0; in tg3_request_firmware()
11585 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11587 msix_ent[i].vector = 0; in tg3_enable_msix()
11591 if (rc < 0) { in tg3_enable_msix()
11602 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11637 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11651 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11701 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11704 for (i--; i >= 0; i--) { in tg3_start()
11713 tg3_full_lock(tp, 0); in tg3_start()
11733 tg3_full_lock(tp, 0); in tg3_start()
11753 tg3_full_lock(tp, 0); in tg3_start()
11772 return 0; in tg3_start()
11775 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11814 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11865 tg3_full_lock(tp, 0); in tg3_open()
11900 return 0; in tg3_close()
11922 val = 0; in tg3_calc_crc_errors()
12084 for (i = 0; i < tp->irq_cnt; i++) { in tg3_get_nstats()
12105 regs->version = 0; in tg3_get_regs()
12107 memset(_p, 0, TG3_REG_BLK_SIZE); in tg3_get_regs()
12112 tg3_full_lock(tp, 0); in tg3_get_regs()
12129 int ret, cpmu_restore = 0; in tg3_get_eeprom()
12131 u32 i, offset, len, b_offset, b_count, cpmu_val = 0; in tg3_get_eeprom()
12139 eeprom->len = 0; in tg3_get_eeprom()
12175 for (i = 0; i < (len - (len & 3)); i += 4) { in tg3_get_eeprom()
12206 ret = 0; in tg3_get_eeprom()
12223 __be32 start = 0, end; in tg3_set_eeprom()
12243 odd_len = 0; in tg3_set_eeprom()
12286 return 0; in tg3_get_link_ksettings()
12345 return 0; in tg3_get_link_ksettings()
12418 tg3_full_lock(tp, 0); in tg3_set_link_ksettings()
12427 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12441 return 0; in tg3_set_link_ksettings()
12460 wol->supported = 0; in tg3_get_wol()
12461 wol->wolopts = 0; in tg3_get_wol()
12464 memset(&wol->sopass, 0, sizeof(wol->sopass)); in tg3_get_wol()
12485 return 0; in tg3_set_wol()
12528 r = 0; in tg3_nway_reset()
12547 ering->rx_jumbo_max_pending = 0; in tg3_get_ringparam()
12555 ering->rx_jumbo_pending = 0; in tg3_get_ringparam()
12557 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12566 int i, irq_sync = 0, err = 0; in tg3_set_ringparam()
12595 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12629 epause->rx_pause = 0; in tg3_get_pauseparam()
12634 epause->tx_pause = 0; in tg3_get_pauseparam()
12640 int err = 0; in tg3_set_pauseparam()
12654 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12680 return 0; in tg3_set_pauseparam()
12684 tg3_setup_flow_control(tp, 0, 0); in tg3_set_pauseparam()
12687 int irq_sync = 0; in tg3_set_pauseparam()
12762 return 0; in tg3_get_rxnfc()
12771 u32 size = 0; in tg3_get_rxfh_indir_size()
12787 return 0; in tg3_get_rxfh()
12789 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) in tg3_get_rxfh()
12792 return 0; in tg3_get_rxfh()
12810 return 0; in tg3_set_rxfh()
12812 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) in tg3_set_rxfh()
12816 return 0; in tg3_set_rxfh()
12821 tg3_full_lock(tp, 0); in tg3_set_rxfh()
12825 return 0; in tg3_set_rxfh()
12869 return 0; in tg3_set_channels()
12877 return 0; in tg3_set_channels()
12924 return 0; in tg3_set_phys_id()
12935 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats)); in tg3_get_ethtool_stats()
12942 u32 offset = 0, len = 0; in tg3_vpd_readblock()
12945 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) in tg3_vpd_readblock()
12977 for (i = 0; i < len; i += 4) { in tg3_vpd_readblock()
12999 #define NVRAM_TEST_SIZE 0x100
13000 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
13001 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
13002 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
13003 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
13004 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
13005 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
13006 #define NVRAM_SELFBOOT_HW_SIZE 0x20
13007 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
13013 int i, j, k, err = 0, size; in tg3_test_nvram()
13017 return 0; in tg3_test_nvram()
13019 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_test_nvram()
13050 return 0; in tg3_test_nvram()
13061 for (i = 0, j = 0; i < size; i += 4, j++) { in tg3_test_nvram()
13070 magic = be32_to_cpu(buf[0]); in tg3_test_nvram()
13073 u8 *buf8 = (u8 *) buf, csum8 = 0; in tg3_test_nvram()
13078 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) in tg3_test_nvram()
13083 for (i = 0; i < size; i++) in tg3_test_nvram()
13087 if (csum8 == 0) { in tg3_test_nvram()
13088 err = 0; in tg3_test_nvram()
13103 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { in tg3_test_nvram()
13104 if ((i == 0) || (i == 8)) { in tg3_test_nvram()
13108 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) in tg3_test_nvram()
13115 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) in tg3_test_nvram()
13119 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) in tg3_test_nvram()
13127 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { in tg3_test_nvram()
13130 if ((hw8 & 0x1) && parity[i]) in tg3_test_nvram()
13132 else if (!(hw8 & 0x1) && !parity[i]) in tg3_test_nvram()
13135 err = 0; in tg3_test_nvram()
13141 /* Bootstrap checksum at offset 0x10 */ in tg3_test_nvram()
13142 csum = calc_crc((unsigned char *) buf, 0x10); in tg3_test_nvram()
13145 if (csum != le32_to_cpu((__force __le32)buf[0x10 / 4])) in tg3_test_nvram()
13148 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ in tg3_test_nvram()
13149 csum = calc_crc((unsigned char *)&buf[0x74 / 4], 0x88); in tg3_test_nvram()
13152 if (csum != le32_to_cpu((__force __le32)buf[0xfc / 4])) in tg3_test_nvram()
13164 err = 0; in tg3_test_nvram()
13185 for (i = 0; i < max; i++) { in tg3_test_link()
13187 return 0; in tg3_test_link()
13204 #define TG3_FL_5705 0x1 in tg3_test_registers()
13205 #define TG3_FL_NOT_5705 0x2 in tg3_test_registers()
13206 #define TG3_FL_NOT_5788 0x4 in tg3_test_registers()
13207 #define TG3_FL_NOT_5750 0x8 in tg3_test_registers()
13213 0x00000000, 0x00ef6f8c }, in tg3_test_registers()
13215 0x00000000, 0x01ef6b8c }, in tg3_test_registers()
13217 0x03800107, 0x00000000 }, in tg3_test_registers()
13219 0x03800100, 0x00000000 }, in tg3_test_registers()
13220 { MAC_ADDR_0_HIGH, 0x0000, in tg3_test_registers()
13221 0x00000000, 0x0000ffff }, in tg3_test_registers()
13222 { MAC_ADDR_0_LOW, 0x0000, in tg3_test_registers()
13223 0x00000000, 0xffffffff }, in tg3_test_registers()
13224 { MAC_RX_MTU_SIZE, 0x0000, in tg3_test_registers()
13225 0x00000000, 0x0000ffff }, in tg3_test_registers()
13226 { MAC_TX_MODE, 0x0000, in tg3_test_registers()
13227 0x00000000, 0x00000070 }, in tg3_test_registers()
13228 { MAC_TX_LENGTHS, 0x0000, in tg3_test_registers()
13229 0x00000000, 0x00003fff }, in tg3_test_registers()
13231 0x00000000, 0x000007fc }, in tg3_test_registers()
13233 0x00000000, 0x000007dc }, in tg3_test_registers()
13234 { MAC_HASH_REG_0, 0x0000, in tg3_test_registers()
13235 0x00000000, 0xffffffff }, in tg3_test_registers()
13236 { MAC_HASH_REG_1, 0x0000, in tg3_test_registers()
13237 0x00000000, 0xffffffff }, in tg3_test_registers()
13238 { MAC_HASH_REG_2, 0x0000, in tg3_test_registers()
13239 0x00000000, 0xffffffff }, in tg3_test_registers()
13240 { MAC_HASH_REG_3, 0x0000, in tg3_test_registers()
13241 0x00000000, 0xffffffff }, in tg3_test_registers()
13244 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, in tg3_test_registers()
13245 0x00000000, 0xffffffff }, in tg3_test_registers()
13247 0x00000000, 0xffffffff }, in tg3_test_registers()
13249 0x00000000, 0x00000003 }, in tg3_test_registers()
13250 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, in tg3_test_registers()
13251 0x00000000, 0xffffffff }, in tg3_test_registers()
13252 { RCVDBDI_STD_BD+0, 0x0000, in tg3_test_registers()
13253 0x00000000, 0xffffffff }, in tg3_test_registers()
13254 { RCVDBDI_STD_BD+4, 0x0000, in tg3_test_registers()
13255 0x00000000, 0xffffffff }, in tg3_test_registers()
13256 { RCVDBDI_STD_BD+8, 0x0000, in tg3_test_registers()
13257 0x00000000, 0xffff0002 }, in tg3_test_registers()
13258 { RCVDBDI_STD_BD+0xc, 0x0000, in tg3_test_registers()
13259 0x00000000, 0xffffffff }, in tg3_test_registers()
13263 0x00000000, 0xffffffff }, in tg3_test_registers()
13265 0x00000000, 0x000003ff }, in tg3_test_registers()
13267 0x00000000, 0xffffffff }, in tg3_test_registers()
13271 0x00000000, 0x00000004 }, in tg3_test_registers()
13273 0x00000000, 0x000000f6 }, in tg3_test_registers()
13275 0x00000000, 0xffffffff }, in tg3_test_registers()
13277 0x00000000, 0x000003ff }, in tg3_test_registers()
13279 0x00000000, 0xffffffff }, in tg3_test_registers()
13281 0x00000000, 0x000003ff }, in tg3_test_registers()
13283 0x00000000, 0xffffffff }, in tg3_test_registers()
13285 0x00000000, 0x000000ff }, in tg3_test_registers()
13287 0x00000000, 0xffffffff }, in tg3_test_registers()
13289 0x00000000, 0x000000ff }, in tg3_test_registers()
13291 0x00000000, 0xffffffff }, in tg3_test_registers()
13293 0x00000000, 0xffffffff }, in tg3_test_registers()
13295 0x00000000, 0xffffffff }, in tg3_test_registers()
13297 0x00000000, 0x000000ff }, in tg3_test_registers()
13299 0x00000000, 0xffffffff }, in tg3_test_registers()
13301 0x00000000, 0x000000ff }, in tg3_test_registers()
13303 0x00000000, 0xffffffff }, in tg3_test_registers()
13305 0x00000000, 0xffffffff }, in tg3_test_registers()
13307 0x00000000, 0xffffffff }, in tg3_test_registers()
13308 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, in tg3_test_registers()
13309 0x00000000, 0xffffffff }, in tg3_test_registers()
13310 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, in tg3_test_registers()
13311 0x00000000, 0xffffffff }, in tg3_test_registers()
13312 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, in tg3_test_registers()
13313 0xffffffff, 0x00000000 }, in tg3_test_registers()
13314 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, in tg3_test_registers()
13315 0xffffffff, 0x00000000 }, in tg3_test_registers()
13319 0x00000000, 0x007fff80 }, in tg3_test_registers()
13321 0x00000000, 0x007fffff }, in tg3_test_registers()
13322 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, in tg3_test_registers()
13323 0x00000000, 0x0000003f }, in tg3_test_registers()
13324 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, in tg3_test_registers()
13325 0x00000000, 0x000001ff }, in tg3_test_registers()
13326 { BUFMGR_MB_HIGH_WATER, 0x0000, in tg3_test_registers()
13327 0x00000000, 0x000001ff }, in tg3_test_registers()
13329 0xffffffff, 0x00000000 }, in tg3_test_registers()
13331 0xffffffff, 0x00000000 }, in tg3_test_registers()
13334 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, in tg3_test_registers()
13335 0x00000000, 0x000001ff }, in tg3_test_registers()
13337 0x00000000, 0x000001ff }, in tg3_test_registers()
13338 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, in tg3_test_registers()
13339 0x00000000, 0x000007ff }, in tg3_test_registers()
13340 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, in tg3_test_registers()
13341 0x00000000, 0x000001ff }, in tg3_test_registers()
13343 { 0xffff, 0x0000, 0x00000000, 0x00000000 }, in tg3_test_registers()
13346 is_5705 = is_5750 = 0; in tg3_test_registers()
13353 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in tg3_test_registers()
13380 tw32(offset, 0); in tg3_test_registers()
13407 return 0; in tg3_test_registers()
13419 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; in tg3_do_mem_test()
13423 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { in tg3_do_mem_test()
13424 for (j = 0; j < len; j += 4) { in tg3_do_mem_test()
13433 return 0; in tg3_do_mem_test()
13442 { 0x00000000, 0x00b50}, in tg3_test_memory()
13443 { 0x00002000, 0x1c000}, in tg3_test_memory()
13444 { 0xffffffff, 0x00000} in tg3_test_memory()
13446 { 0x00000100, 0x0000c}, in tg3_test_memory()
13447 { 0x00000200, 0x00008}, in tg3_test_memory()
13448 { 0x00004000, 0x00800}, in tg3_test_memory()
13449 { 0x00006000, 0x01000}, in tg3_test_memory()
13450 { 0x00008000, 0x02000}, in tg3_test_memory()
13451 { 0x00010000, 0x0e000}, in tg3_test_memory()
13452 { 0xffffffff, 0x00000} in tg3_test_memory()
13454 { 0x00000200, 0x00008}, in tg3_test_memory()
13455 { 0x00004000, 0x00800}, in tg3_test_memory()
13456 { 0x00006000, 0x00800}, in tg3_test_memory()
13457 { 0x00008000, 0x02000}, in tg3_test_memory()
13458 { 0x00010000, 0x0c000}, in tg3_test_memory()
13459 { 0xffffffff, 0x00000} in tg3_test_memory()
13461 { 0x00000200, 0x00008}, in tg3_test_memory()
13462 { 0x00004000, 0x00400}, in tg3_test_memory()
13463 { 0x00006000, 0x00400}, in tg3_test_memory()
13464 { 0x00008000, 0x01000}, in tg3_test_memory()
13465 { 0x00010000, 0x01000}, in tg3_test_memory()
13466 { 0xffffffff, 0x00000} in tg3_test_memory()
13468 { 0x00000200, 0x00008}, in tg3_test_memory()
13469 { 0x00010000, 0x0a000}, in tg3_test_memory()
13470 { 0x00020000, 0x13c00}, in tg3_test_memory()
13471 { 0xffffffff, 0x00000} in tg3_test_memory()
13473 { 0x00000200, 0x00008}, in tg3_test_memory()
13474 { 0x00004000, 0x00800}, in tg3_test_memory()
13475 { 0x00006000, 0x09800}, in tg3_test_memory()
13476 { 0x00010000, 0x0a000}, in tg3_test_memory()
13477 { 0xffffffff, 0x00000} in tg3_test_memory()
13480 int err = 0; in tg3_test_memory()
13497 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { in tg3_test_memory()
13513 0x08, 0x00,
13514 0x45, 0x00, 0x00, 0x00,
13515 0x00, 0x00, 0x40, 0x00,
13516 0x40, 0x06, 0x00, 0x00,
13517 0x0a, 0x00, 0x00, 0x01,
13518 0x0a, 0x00, 0x00, 0x02,
13519 0x0d, 0x00, 0xe0, 0x00,
13520 0x00, 0x00, 0x01, 0x00,
13521 0x00, 0x00, 0x02, 0x00,
13522 0x80, 0x10, 0x10, 0x00,
13523 0x14, 0x09, 0x00, 0x00,
13524 0x01, 0x01, 0x08, 0x0a,
13525 0x11, 0x11, 0x11, 0x11,
13526 0x11, 0x11, 0x11, 0x11,
13532 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val; in tg3_run_loopback()
13540 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13542 tnapi = &tp->napi[0]; in tg3_run_loopback()
13543 rnapi = &tp->napi[0]; in tg3_run_loopback()
13561 memset(tx_data + ETH_ALEN, 0x0, 8); in tg3_run_loopback()
13590 th->check = 0; in tg3_run_loopback()
13595 mss |= (hdr_len & 0xc) << 12; in tg3_run_loopback()
13596 if (hdr_len & 0x10) in tg3_run_loopback()
13597 base_flags |= 0x00000010; in tg3_run_loopback()
13598 base_flags |= (hdr_len & 0x3e0) << 5; in tg3_run_loopback()
13619 tx_data[i] = (u8) (i & 0xff); in tg3_run_loopback()
13636 rx_start_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13640 base_flags | TXD_FLAG_END, mss, 0)) { in tg3_run_loopback()
13657 for (i = 0; i < 35; i++) { in tg3_run_loopback()
13663 tx_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_run_loopback()
13664 rx_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13685 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
13705 >> RXD_TCPCSUM_SHIFT != 0xffff) { in tg3_run_loopback()
13725 if (*(rx_data + i) != (u8) (val & 0xff)) in tg3_run_loopback()
13730 err = 0; in tg3_run_loopback()
13780 tw32(i, 0x0); in tg3_test_loopback()
13806 tg3_phy_lpbk_set(tp, 0, false); in tg3_test_loopback()
13809 for (i = 0; i < 100; i++) { in tg3_test_loopback()
13825 tg3_phy_lpbk_set(tp, 0, true); in tg3_test_loopback()
13852 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; in tg3_test_loopback()
13875 memset(data, 0, sizeof(u64) * TG3_NUM_TEST); in tg3_self_test()
13877 if (tg3_test_nvram(tp) != 0) { in tg3_self_test()
13886 int err, err2 = 0, irq_sync = 0; in tg3_self_test()
13906 if (tg3_test_registers(tp) != 0) { in tg3_self_test()
13911 if (tg3_test_memory(tp) != 0) { in tg3_self_test()
13924 if (tg3_test_interrupt(tp) != 0) { in tg3_self_test()
13930 tg3_full_lock(tp, 0); in tg3_self_test()
13968 tp->rxptpctl = 0; in tg3_hwtstamp_set()
14032 -EFAULT : 0; in tg3_hwtstamp_set()
14043 stmpconf.flags = 0; in tg3_hwtstamp_get()
14048 case 0: in tg3_hwtstamp_get()
14093 -EFAULT : 0; in tg3_hwtstamp_get()
14125 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14126 data->reg_num & 0x1f, &mii_regval); in tg3_ioctl()
14142 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14143 data->reg_num & 0x1f, data->val_in); in tg3_ioctl()
14169 return 0; in tg3_get_coalesce()
14178 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; in tg3_set_coalesce()
14179 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; in tg3_set_coalesce()
14214 tg3_full_lock(tp, 0); in tg3_set_coalesce()
14218 return 0; in tg3_set_coalesce()
14251 tg3_full_lock(tp, 0); in tg3_set_eee()
14257 return 0; in tg3_set_eee()
14271 return 0; in tg3_get_eee()
14339 tg3_full_lock(tp, 0); in tg3_set_rx_mode()
14376 return 0; in tg3_change_mtu()
14437 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_get_eeprom_size()
14450 cursize = 0x10; in tg3_get_eeprom_size()
14453 if (tg3_nvram_read(tp, cursize, &val) != 0) in tg3_get_eeprom_size()
14469 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) in tg3_get_nvram_size()
14478 if (tg3_nvram_read(tp, 0xf0, &val) == 0) { in tg3_get_nvram_size()
14479 if (val != 0) { in tg3_get_nvram_size()
14481 * 16-bit value at offset 0xf2. The tg3_nvram_read() in tg3_get_nvram_size()
14491 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14619 u32 nvcfg1, protect = 0; in tg3_get_5755_nvram_info()
14641 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14644 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14647 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14713 u32 nvcfg1, protect = 0; in tg3_get_5761_nvram_info()
14983 * to read the actual size from location 0xf0. in tg3_get_5720_nvram_info()
15099 if (tg3_nvram_read(tp, 0, &val)) in tg3_get_5720_nvram_info()
15143 tp->nvram_size = 0; in tg3_nvram_init()
15169 if (tp->nvram_size == 0) in tg3_nvram_init()
15197 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
15203 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
15219 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15241 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15249 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15256 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { in tg3_lookup_by_subsys()
15296 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0; in tg3_get_eeprom_hw_cfg()
15298 int eeprom_phy_serdes = 0; in tg3_get_eeprom_hw_cfg()
15308 (ver > 0) && (ver < 0x100)) in tg3_get_eeprom_hw_cfg()
15324 if (nic_phy_id != 0) { in tg3_get_eeprom_hw_cfg()
15329 eeprom_phy_id |= (id2 & 0xfc00) << 16; in tg3_get_eeprom_hw_cfg()
15330 eeprom_phy_id |= (id2 & 0x03ff) << 0; in tg3_get_eeprom_hw_cfg()
15332 eeprom_phy_id = 0; in tg3_get_eeprom_hw_cfg()
15361 /* Default to PHY_1_MODE if 0 (MAC_MODE) is in tg3_get_eeprom_hw_cfg()
15409 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15410 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15440 /* serdes signal pre-emphasis in register 0x590 set by */ in tg3_get_eeprom_hw_cfg()
15498 for (i = 0; i < 100; i++) { in tg3_ape_otp_read()
15507 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0); in tg3_ape_otp_read()
15511 return 0; in tg3_ape_otp_read()
15525 for (i = 0; i < 100; i++) { in tg3_issue_otp_command()
15532 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; in tg3_issue_otp_command()
15546 return 0; in tg3_read_otp_phycfg()
15551 return 0; in tg3_read_otp_phycfg()
15558 return 0; in tg3_read_otp_phycfg()
15562 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); in tg3_read_otp_phycfg()
15606 case 0: in tg3_phy_probe()
15633 err = 0; in tg3_phy_probe()
15645 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; in tg3_phy_probe()
15646 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; in tg3_phy_probe()
15647 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; in tg3_phy_probe()
15673 /* For now we saw the IDs 0xbc050cd0, in tg3_phy_probe()
15674 * 0xbc050f80 and 0xbc050c30 on devices in tg3_phy_probe()
15764 if (i < 0) in tg3_read_vpd()
15772 if (i < 0) in tg3_read_vpd()
15775 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15781 if (i < 0) in tg3_read_vpd()
15791 if (tp->board_part_number[0]) in tg3_read_vpd()
15853 (val & 0xfc000000) != 0x0c000000 || in tg3_fw_img_is_valid()
15855 val != 0) in tg3_fw_img_is_valid()
15856 return 0; in tg3_fw_img_is_valid()
15867 if (tg3_nvram_read(tp, 0xc, &offset) || in tg3_read_bc_ver()
15868 tg3_nvram_read(tp, 0x4, &start)) in tg3_read_bc_ver()
15876 if ((val & 0xfc000000) == 0x0c000000) { in tg3_read_bc_ver()
15880 if (val == 0) in tg3_read_bc_ver()
15892 for (i = 0; i < 16; i += 4) { in tg3_read_bc_ver()
15926 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15977 if (build > 0) { in tg3_read_sb_ver()
16003 start = 0x08000000; in tg3_read_mgmtfw_ver()
16019 for (i = 0; i < 4; i++) { in tg3_read_mgmtfw_ver()
16088 u32 ver = 0; in tg3_read_otp_ver()
16091 for (i = 0; i < 7; i++) { in tg3_read_otp_ver()
16092 if ((val64 & 0xff) == 0) in tg3_read_otp_ver()
16094 ver = val64 & 0xff; in tg3_read_otp_ver()
16107 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
16116 if (tg3_nvram_read(tp, 0, &val)) in tg3_read_fw_ver()
16136 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16161 for (func = 0; func < 8; func++) { in tg3_find_peer()
16278 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || in tg3_10_100_only_device()
16356 0xa }, in tg3_get_invariants()
16361 struct tg3_dev_id *pci_id = &ich_chipsets[0]; in tg3_get_invariants()
16364 while (pci_id->vendor != 0) { in tg3_get_invariants()
16394 struct tg3_dev_id *pci_id = &bridge_chipsets[0]; in tg3_get_invariants()
16397 while (pci_id->vendor != 0) { in tg3_get_invariants()
16640 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; in tg3_get_invariants()
16652 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) in tg3_get_invariants()
16654 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) in tg3_get_invariants()
16737 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16747 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16882 if (tp->phy_otp == 0) in tg3_get_invariants()
16891 tp->coalesce_mode = 0; in tg3_get_invariants()
16930 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_get_invariants()
16933 tw32(TG3PCI_REG_BASE_ADDR, 0); in tg3_get_invariants()
16937 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && in tg3_get_invariants()
16951 writel(0x00000000, sram_base); in tg3_get_invariants()
16952 writel(0x00000000, sram_base + 4); in tg3_get_invariants()
16953 writel(0xffffffff, sram_base + 4); in tg3_get_invariants()
16954 if (readl(sram_base) != 0x00000000) in tg3_get_invariants()
16991 tp->mac_mode = 0; in tg3_get_invariants()
17050 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
17078 int addr_ok = 0; in tg3_get_device_address()
17082 return 0; in tg3_get_device_address()
17087 return 0; in tg3_get_device_address()
17090 mac_offset = 0x7c; in tg3_get_device_address()
17094 mac_offset = 0xcc; in tg3_get_device_address()
17101 mac_offset = 0xcc; in tg3_get_device_address()
17103 mac_offset += 0x18c; in tg3_get_device_address()
17105 mac_offset = 0x10; in tg3_get_device_address()
17109 if ((hi >> 16) == 0x484b) { in tg3_get_device_address()
17110 addr[0] = (hi >> 8) & 0xff; in tg3_get_device_address()
17111 addr[1] = (hi >> 0) & 0xff; in tg3_get_device_address()
17114 addr[2] = (lo >> 24) & 0xff; in tg3_get_device_address()
17115 addr[3] = (lo >> 16) & 0xff; in tg3_get_device_address()
17116 addr[4] = (lo >> 8) & 0xff; in tg3_get_device_address()
17117 addr[5] = (lo >> 0) & 0xff; in tg3_get_device_address()
17119 /* Some old bootcode may report a 0 MAC address in SRAM */ in tg3_get_device_address()
17127 !tg3_nvram_read_be32(tp, mac_offset + 0, &be_hi) && in tg3_get_device_address()
17129 memcpy(&addr[0], ((char *)&be_hi) + 2, 2); in tg3_get_device_address()
17137 addr[5] = lo & 0xff; in tg3_get_device_address()
17138 addr[4] = (lo >> 8) & 0xff; in tg3_get_device_address()
17139 addr[3] = (lo >> 16) & 0xff; in tg3_get_device_address()
17140 addr[2] = (lo >> 24) & 0xff; in tg3_get_device_address()
17141 addr[1] = hi & 0xff; in tg3_get_device_address()
17142 addr[0] = (hi >> 8) & 0xff; in tg3_get_device_address()
17148 return 0; in tg3_get_device_address()
17161 if (byte == 0) in tg3_calc_dma_bndry()
17180 goal = 0; in tg3_calc_dma_bndry()
17185 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; in tg3_calc_dma_bndry()
17304 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); in tg3_do_test_dma()
17305 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); in tg3_do_test_dma()
17306 tw32(RDMAC_STATUS, 0); in tg3_do_test_dma()
17307 tw32(WDMAC_STATUS, 0); in tg3_do_test_dma()
17309 tw32(BUFMGR_MODE, 0); in tg3_do_test_dma()
17310 tw32(FTQ_RESET, 0); in tg3_do_test_dma()
17313 test_desc.addr_lo = buf_dma & 0xffffffff; in tg3_do_test_dma()
17314 test_desc.nic_mbuf = 0x00002100; in tg3_do_test_dma()
17340 test_desc.flags = 0x00000005; in tg3_do_test_dma()
17342 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { in tg3_do_test_dma()
17350 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17358 for (i = 0; i < 40; i++) { in tg3_do_test_dma()
17365 if ((val & 0xffff) == sram_dma_descs) { in tg3_do_test_dma()
17366 ret = 0; in tg3_do_test_dma()
17376 #define TEST_BUFFER_SIZE 0x2000
17387 int ret = 0; in tg3_test_dma()
17396 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17397 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); in tg3_test_dma()
17406 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17410 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17412 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17416 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); in tg3_test_dma()
17417 u32 read_water = 0x7; in tg3_test_dma()
17425 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17426 else if (ccval == 0x6 || ccval == 0x7) in tg3_test_dma()
17434 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | in tg3_test_dma()
17438 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17441 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17443 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17451 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17488 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) in tg3_test_dma()
17509 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { in tg3_test_dma()
17530 ret = 0; in tg3_test_dma()
17640 case 0: return "serdes"; in tg3_phy_string()
17651 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; in tg3_bus_string()
17659 else if (clock_ctrl == 0) in tg3_bus_string()
17685 memset(ec, 0, sizeof(*ec)); in tg3_init_coal()
17706 ec->rx_coalesce_usecs_irq = 0; in tg3_init_coal()
17707 ec->tx_coalesce_usecs_irq = 0; in tg3_init_coal()
17708 ec->stats_block_coalesce_usecs = 0; in tg3_init_coal()
17721 netdev_features_t features = 0; in tg3_init_one()
17754 if (tg3_debug > 0) in tg3_init_one()
17871 if (err < 0) { in tg3_init_one()
17959 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17966 intmbx += 0x8; in tg3_init_one()
17989 rcvmbx += 0x8; in tg3_init_one()
17991 if (sndmbx & 0x4) in tg3_init_one()
17992 sndmbx -= 0x4; in tg3_init_one()
17994 sndmbx += 0xc; in tg3_init_one()
18004 tg3_full_lock(tp, 0); in tg3_init_one()
18062 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
18063 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
18067 (dev->features & NETIF_F_RXCSUM) != 0, in tg3_init_one()
18068 tg3_flag(tp, USE_LINKCHG_REG) != 0, in tg3_init_one()
18069 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
18070 tg3_flag(tp, ENABLE_ASF) != 0, in tg3_init_one()
18071 tg3_flag(tp, TSO_CAPABLE) != 0); in tg3_init_one()
18079 return 0; in tg3_init_one()
18161 tg3_full_lock(tp, 0); in tg3_suspend()
18170 return 0; in tg3_suspend()
18177 int err = 0; in tg3_resume()
18187 tg3_full_lock(tp, 0); in tg3_resume()
18334 tg3_full_lock(tp, 0); in tg3_io_error_detected()
18335 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_io_error_detected()
18426 tg3_full_lock(tp, 0); in tg3_io_resume()