Lines Matching full:rw

12  * by size in bits. For example [RW 32]. The access types are:
15  * RW - Read/Write
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
38 /* [RW 5] Parity mask register #0 read/write */
44 /* [RW 19] Interrupt mask register #0 read/write */
48 /* [RW 4] Parity mask register #0 read/write */
54 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
62 /* [RW 10] The number of free blocks below which the full signal to class 0
66 /* [RW 11] The number of free blocks above which the full signal to class 0
70 /* [RW 11] The number of free blocks below which the full signal to class 1
74 /* [RW 11] The number of free blocks above which the full signal to class 1
78 /* [RW 11] The number of free blocks below which the full signal to the LB
81 /* [RW 10] The number of free blocks above which the full signal to the LB
84 /* [RW 10] The number of free blocks above which the High_llfc signal to
87 /* [RW 10] The number of free blocks below which the High_llfc signal to
90 /* [RW 11] The number of blocks guarantied for the LB port */
92 /* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
95 /* [RW 24] LL RAM data. */
97 /* [RW 10] The number of free blocks above which the Low_llfc signal to
100 /* [RW 10] The number of free blocks below which the Low_llfc signal to
103 /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
106 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
110 /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
113 /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
117 /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
120 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
124 /* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
127 /* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
131 /* [RW 11] The number of blocks guarantied for the MAC port. The register is
146 /* [RW 10] The number of free blocks below which the pause signal to class 0
150 /* [RW 11] The number of free blocks above which the pause signal to class 0
154 /* [RW 11] The number of free blocks below which the pause signal to class 1
158 /* [RW 11] The number of free blocks above which the pause signal to class 1
162 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
165 /* [RW 10] Write client 0: Assert pause threshold. */
167 /* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
173 /* [RW 1] Reset the design by software. */
177 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
181 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
185 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
188 /* [RW 11] Interrupt mask register #0 read/write */
192 /* [RW 27] Parity mask register #0 read/write */
198 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
203 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
207 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
211 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
215 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
219 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
223 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
227 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
231 /* [RW 2] Auxiliary counter flag Q number 1. */
233 /* [RW 2] Auxiliary counter flag Q number 2. */
235 /* [RW 28] The CM header value for QM request (primary). */
237 /* [RW 28] The CM header value for QM request (secondary). */
239 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
243 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
247 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
251 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
255 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
262 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
266 /* [RW 28] The CM header for QM formatting in case of an error in the QM
269 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
271 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
275 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
279 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
285 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
290 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
295 /* [RW 2] General flags index. */
297 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
307 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
314 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
332 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
339 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
344 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
351 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
355 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
362 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
366 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
373 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
377 /* [RW 19] Indirect access to the descriptor table of the XX protection
384 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
390 /* [RW 7] The maximum number of pending messages; which may be stored in XX
395 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
397 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
406 /* [RW 7] Interrupt mask register #0 read/write */
410 /* [RW 5] Parity mask register #0 read/write */
427 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
432 /* [RW 13] activity counter ram access */
437 /* [RW 2] Interrupt mask register #0 read/write */
443 /* [RW 4] Parity mask register #0 read/write */
449 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
453 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
465 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
469 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
482 /* [RW 8] The event id for aggregated interrupt 0 */
499 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
512 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
514 /* [RW 16] The maximum value of the completion counter #0 */
516 /* [RW 16] The maximum value of the completion counter #1 */
518 /* [RW 16] The maximum value of the completion counter #2 */
520 /* [RW 16] The maximum value of the completion counter #3 */
522 /* [RW 13] The start address in the internal RAM for the completion
525 /* [RW 32] Interrupt mask register #0 read/write */
531 /* [RW 11] Parity mask register #0 read/write */
541 /* [RW 4] The initial number of messages that can be sent to the pxp control
572 /* [RW 13] The start address in the internal RAM for queue counters */
580 /* [RW 32] Tick for timer counter. Applicable only when
583 /* [RW 5] The number of time_slots in the arbitration cycle */
585 /* [RW 3] The source that is associated with arbitration element 0. Source
589 /* [RW 3] The source that is associated with arbitration element 1. Source
594 /* [RW 3] The source that is associated with arbitration element 2. Source
600 /* [RW 3] The source that is associated with arbitration element 3. Source
607 /* [RW 3] The source that is associated with arbitration element 4. Source
615 /* [RW 32] Interrupt mask register #0 read/write */
621 /* [RW 32] Parity mask register #0 read/write */
632 /* [RW 32] This address space contains all registers and memories that are
637 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
640 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
643 /* [RW 15] Interrupt table Read and write access to it is not possible in
664 /* [RW 1] Disables input messages from the passive buffer May be updated
675 /* [RW 16] List of free threads . There is a bit per thread. */
677 /* [RW 3] The arbitration scheme of time_slot 0 */
679 /* [RW 3] The arbitration scheme of time_slot 10 */
681 /* [RW 3] The arbitration scheme of time_slot 11 */
683 /* [RW 3] The arbitration scheme of time_slot 12 */
685 /* [RW 3] The arbitration scheme of time_slot 13 */
687 /* [RW 3] The arbitration scheme of time_slot 14 */
689 /* [RW 3] The arbitration scheme of time_slot 15 */
691 /* [RW 3] The arbitration scheme of time_slot 16 */
693 /* [RW 3] The arbitration scheme of time_slot 17 */
695 /* [RW 3] The arbitration scheme of time_slot 18 */
697 /* [RW 3] The arbitration scheme of time_slot 1 */
699 /* [RW 3] The arbitration scheme of time_slot 2 */
701 /* [RW 3] The arbitration scheme of time_slot 3 */
703 /* [RW 3] The arbitration scheme of time_slot 4 */
705 /* [RW 3] The arbitration scheme of time_slot 5 */
707 /* [RW 3] The arbitration scheme of time_slot 6 */
709 /* [RW 3] The arbitration scheme of time_slot 7 */
711 /* [RW 3] The arbitration scheme of time_slot 8 */
713 /* [RW 3] The arbitration scheme of time_slot 9 */
718 /* [RW 1] Parity mask register #0 read/write */
724 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
728 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
732 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
735 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
738 /* [RW 2] Interrupt mask register #0 read/write */
740 /* [RW 4] Parity mask register #0 read/write */
746 /* [RW 1] Command 0 go. */
748 /* [RW 1] Command 1 go. */
750 /* [RW 1] Command 10 go. */
752 /* [RW 1] Command 11 go. */
754 /* [RW 1] Command 12 go. */
756 /* [RW 1] Command 13 go. */
758 /* [RW 1] Command 14 go. */
760 /* [RW 1] Command 15 go. */
762 /* [RW 1] Command 2 go. */
764 /* [RW 1] Command 3 go. */
766 /* [RW 1] Command 4 go. */
768 /* [RW 1] Command 5 go. */
770 /* [RW 1] Command 6 go. */
772 /* [RW 1] Command 7 go. */
774 /* [RW 1] Command 8 go. */
776 /* [RW 1] Command 9 go. */
778 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
782 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
786 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
790 /* [RW 8] Aggregation command. */
792 /* [RW 8] Aggregation command. */
794 /* [RW 8] Aggregation command. */
796 /* [RW 8] Aggregation command. */
798 /* [RW 28] UCM Header. */
800 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
802 /* [RW 5] Interrupt mask register #0 read/write */
808 /* [RW 2] Parity mask register #0 read/write */
814 /* [RW 8] The address to write the DPM CID to STORM. */
816 /* [RW 5] The DPM mode CID extraction offset. */
818 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
820 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
829 /* [RW 28] The value sent to CM header in the case of CFC load error. */
834 /* [RW 5] The normal mode CID extraction offset. */
836 /* [RW 28] TCM Header when only TCP context is loaded. */
838 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
851 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
861 /* [RW 10] VF type validation mask value */
863 /* [RW 17] VF type validation Min MCID value */
865 /* [RW 17] VF type validation Max MCID value */
867 /* [RW 10] VF type validation comp value */
873 /* [RW 4] Initial activity counter value on the load request; when the
876 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
899 /* [RW 3] Parity mask register #0 read/write */
946 /* [RW 11] Parity mask register #0 read/write */
955 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
971 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
984 /* [RW 6] Write one for each bit will reset the appropriate memory. When the
995 /* [RW 16] Number of command that were dropped without causing an interrupt
1000 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
1004 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
1161 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1181 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1201 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1216 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1231 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1246 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1261 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1276 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1291 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1306 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1321 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1336 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1351 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1369 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1387 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1401 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1415 /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
1421 /* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
1427 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1443 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1458 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1473 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1477 /* [RW 1] If set a system kill occurred */
1479 /* [RW 32] Represent the status of the input vector to the AEU when a system
1512 /* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled
1516 /* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI
1519 /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
1570 /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
1622 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1626 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
1630 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1648 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1653 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1661 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1667 /* [RW 32] Debug only: spare RW register reset by core reset */
1670 /* [RW 32] Debug only: spare RW register reset by por reset */
1672 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1682 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1699 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1704 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1734 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1740 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1770 /* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
1773 /* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
1775 /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
1778 /* [RW 4] Interrupt mask register #0 read/write */
1780 /* [RW 1] Parity mask register #0 read/write */
1791 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1814 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1820 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1836 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1839 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1865 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1869 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1885 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1889 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1895 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1901 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1909 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1915 /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
1923 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
1929 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1932 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1946 /* [RW 1] Input enable for RX_BMAC0 IF */
1948 /* [RW 1] output enable for TX_BMAC0 IF */
1950 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1952 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1954 /* [RW 1] output enable for RX BRB1 port0 IF */
1956 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1958 /* [RW 1] output enable for RX BRB1 port1 IF */
1960 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1962 /* [RW 1] output enable for RX BRB1 LP IF */
1968 /* [RW 1] Input enable for TX Debug packet */
1970 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1975 /* [RW 1] Output enable to EMAC0 */
1977 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1980 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1982 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1984 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1986 /* [RW 1] Input enable for RX_EMAC0 IF */
1988 /* [RW 1] output enable for TX EMAC pause port 0 IF */
2006 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
2009 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
2013 /* [RW 27] Latch for each interrupt from Unicore.b[0]
2027 /* [RW 1] led 10g for port 0 */
2029 /* [RW 1] led 10g for port 1 */
2031 /* [RW 1] Port0: This bit is set to enable the use of the
2036 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
2040 /* [RW 1] Port0: If set along with the
2048 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
2053 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
2060 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
2063 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
2067 /* [RW 1] SAFC enable for port0. This register may get 1 only when
2072 /* [RW 16] classes are high-priority for port0 */
2075 /* [RW 16] classes are low-priority for port0 */
2078 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
2085 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
2087 /* [RW 2] Determine the classification participants. 0: no classification.1:
2091 /* [RW 32] cm header for llh0 */
2095 /* [RW 16] destination TCP address 1. The LLH will look for this address in
2098 /* [RW 16] destination UDP address 1 The LLH will look for this address in
2102 /* [RW 8] event id for llh0 */
2108 /* [RW 1] Determine the IP version to look for in
2111 /* [RW 1] t bit for llh0 */
2113 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
2115 /* [RW 8] init credit counter for port0 in LLH */
2119 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
2121 /* [RW 2] Determine the classification participants. 0: no classification.1:
2125 /* [RW 32] cm header for llh1 */
2128 /* [RW 8] event id for llh1 */
2134 /* [RW 1] When this bit is set; the LLH will classify the packet before
2138 /* [RW 8] init credit counter for port1 in LLH */
2141 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
2144 /* [RW 16] Outer VLAN type identifier for multi-function mode. In non
2148 /* [RW 1] When this bit is set; the LLH will classify the packet before
2153 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
2155 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
2157 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
2167 /* [RW 32] Parity mask register #0 read/write */
2184 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2187 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
2193 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2207 /* [RW 11] Mask register for the various parameters used in determining PTP
2217 /* [RW 14] Mask register for the rules used in detecting PTP packets. Set
2230 /* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
2232 /* [RW 1] Input enable for RX MAC interface. */
2234 /* [RW 1] Output enable for TX MAC interface */
2236 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2238 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2244 /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
2255 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2260 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2265 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2270 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2275 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2280 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2286 /* [RW 15] Specify which of the credit registers the client is to be mapped
2291 /* [RW 32] Specify which of the credit registers the client is to be mapped
2301 /* [RW 4] Specify which of the credit registers the client is to be mapped
2311 /* [RW 5] Specify whether the client competes directly in the strict
2316 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
2321 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2332 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2343 /* [RW 12] Specify the number of strict priority arbitration slots between
2348 /* [RW 15] Specify the client number to be assigned to each priority of the
2357 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2362 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2376 /* [RW 11] Mask register for the various parameters used in determining PTP
2386 /* [RW 14] Mask register for the rules used in detecting PTP packets. Set
2399 /* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
2401 /* [RW 32] Specify the client number to be assigned to each priority of the
2411 /* [RW 4] Specify the client number to be assigned to each priority of the
2421 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2432 /* [RW 1] Output enable for TX MAC interface */
2434 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */
2436 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2442 /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
2453 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2458 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2463 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2472 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2488 /* [RW 11] Mask register for the various parameters used in determining PTP
2498 /* [RW 14] Mask register for the rules used in detecting PTP packets. Set
2508 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2524 /* [RW 11] Mask register for the various parameters used in determining PTP
2534 /* [RW 14] Mask register for the rules used in detecting PTP packets. Set
2544 /* [RW 32] Specify which of the credit registers the client is to be mapped
2557 /* [RW 4] Specify which of the credit registers the client is to be mapped
2570 /* [RW 9] Specify whether the client competes directly in the strict
2577 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
2590 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2598 /* [RW 12] Specify the number of strict priority arbitration slots between
2603 /* [RW 32] Specify the client number to be assigned to each priority of the
2615 /* [RW 4] Specify the client number to be assigned to each priority of the
2629 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2638 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2640 /* [RW 1] Pause enable for port0. This register may get 1 only when
2645 /* [RW 1] Input enable for RX PBF LP IF */
2647 /* [RW 1] Value of this register will be transmitted to port swap when
2650 /* [RW 1] PPP enable for port0. This register may get 1 only when
2655 /* [RW 1] output enable for RX parser descriptor IF */
2657 /* [RW 1] Input enable for RX parser request IF */
2659 /* [RW 5] control to serdes - CL45 DEVAD */
2661 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2663 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2692 /* [RW 1] port swap mux selection. If this register equal to 0 then port
2700 /* [RW 1] output enable for RX_XCM0 IF */
2702 /* [RW 1] output enable for RX_XCM1 IF */
2704 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2706 /* [RW 5] control to xgxs - CL45 DEVAD */
2708 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2710 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2716 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2718 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2725 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2727 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2730 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
2733 /* [RW 31] The weight of COS0 in the ETS command arbiter. */
2735 /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2737 /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
2739 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2741 /* [RW 31] The weight of COS1 in the ETS command arbiter. */
2743 /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2745 /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
2747 /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2749 /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
2751 /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2753 /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2755 /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2766 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2769 /* [RW 1] Disable processing further tasks from port 1 (after ending the
2772 /* [RW 1] Disable processing further tasks from port 4 (after ending the
2777 /* [RW 18] For port 0: For each client that is subject to WFQ (the
2782 /* [RW 9] For port 1: For each client that is subject to WFQ (the
2787 /* [RW 6] For port 0: Bit per client to indicate if the client competes in
2792 /* [RW 3] For port 1: Bit per client to indicate if the client competes in
2797 /* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2800 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2803 /* [RW 16] For port 0: The number of strict priority arbitration slots
2808 /* [RW 16] For port 1: The number of strict priority arbitration slots
2813 /* [RW 18] For port 0: Indicates which client is connected to each priority
2818 /* [RW 9] For port 1: Indicates which client is connected to each priority
2823 /* [RW 1] Indicates that ETS is performed between the COSes in the command
2827 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2830 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2836 /* [RW 1] Init bit. When set the initial credits are copied to the credit
2840 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2843 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2846 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2849 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2853 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2857 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2870 /* [RW 1] Enable for mac interface 0. */
2872 /* [RW 1] Enable for mac interface 1. */
2874 /* [RW 1] Enable for the loopback interface. */
2876 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2878 /* [RW 16] The number of strict priority arbitration slots between 2 RR
2882 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2887 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2920 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2933 /* [RW 5] Interrupt mask register #0 read/write */
2937 /* [RW 20] Parity mask register #0 read/write */
2943 /* [RW 16] The Ethernet type value for L2 tag 0 */
2945 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2964 /* [RW 16] One of 8 values that should be compared to type in Ethernet
2970 /* [RW 2] Interrupt mask register #0 read/write */
2974 /* [RW 4] Parity mask register #0 read/write */
2999 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
3002 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
3005 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
3008 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
3010 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
3012 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
3014 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3044  * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
3045  * arrived with a correctable error. Bit 3 - Configuration RW arrived with
3071 /* [RW 2] Parity mask register #0 read/write */
3106 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
3109 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
3111 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
3113 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
3115 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3150 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
3160 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
3163 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
3166 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
3169 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
3171 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
3173 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
3175 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3237 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
3240 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
3242 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
3244 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
3246 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3253 /* [RW 6] The initial credit for the search message to the CFC interface.
3256 /* [RW 24] CID for port 0 if no match */
3258 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3267 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
3276 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
3282 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
3289 /* [RW 32] The CM header in case there was not a match on the connection */
3291 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
3293 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
3298 /* [RW 16] The Ethernet type value for FCoE */
3300 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
3310 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3313 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3319 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
3323 /* [RW 4] The increment value to send in the CFC load request message */
3325 /* [RW 6] Bit-map indicating which headers must appear in the packet */
3327 /* [RW 6] Bit-map indicating which headers must appear in the packet for
3332 /* [RW 8] The 8-bit event ID for cases where there is no match on the
3344 /* [RW 8] Context region for received Ethernet packet with a match and
3360 /* [RW 8] Parity mask register #0 read/write */
3366 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
3379 /* [RW 16] The Ethernet type value for L2 tag 0 */
3381 /* [RW 4] The length of the info field for L2 tag 0. The length is between
3388 /* [RW 16] One of 8 values that should be compared to type in Ethernet
3428 /* [RW 32] third dword data of expansion rom request. this register is
3433 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3443 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3453 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3463 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3473 /* [RW 3] this field allows one function to pretend being another function
3533 /* [RW 32] Interrupt mask register #0 read/write */
3540 /* [RW 32] Parity mask register #0 read/write */
3554 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
3557 /* [RW 2] CDU byte swapping mode configuration for master read requests */
3559 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
3563 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3566 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3569 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3572 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3575 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3578 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3581 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3584 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3587 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
3590 /* [RW 2] PBF byte swapping mode configuration for master read requests */
3595 /* [RW 2] QM byte swapping mode configuration for master read requests */
3599 /* [RW 2] SRC byte swapping mode configuration for master read requests */
3601 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3604 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
3606 /* [RW 2] TM byte swapping mode configuration for master read requests */
3608 /* [RW 10] Bandwidth addition to VQ0 write requests */
3610 /* [RW 10] Bandwidth addition to VQ12 read requests */
3612 /* [RW 10] Bandwidth addition to VQ13 read requests */
3614 /* [RW 10] Bandwidth addition to VQ14 read requests */
3616 /* [RW 10] Bandwidth addition to VQ15 read requests */
3618 /* [RW 10] Bandwidth addition to VQ16 read requests */
3620 /* [RW 10] Bandwidth addition to VQ17 read requests */
3622 /* [RW 10] Bandwidth addition to VQ18 read requests */
3624 /* [RW 10] Bandwidth addition to VQ19 read requests */
3626 /* [RW 10] Bandwidth addition to VQ20 read requests */
3628 /* [RW 10] Bandwidth addition to VQ22 read requests */
3630 /* [RW 10] Bandwidth addition to VQ23 read requests */
3632 /* [RW 10] Bandwidth addition to VQ24 read requests */
3634 /* [RW 10] Bandwidth addition to VQ25 read requests */
3636 /* [RW 10] Bandwidth addition to VQ26 read requests */
3638 /* [RW 10] Bandwidth addition to VQ27 read requests */
3640 /* [RW 10] Bandwidth addition to VQ4 read requests */
3642 /* [RW 10] Bandwidth addition to VQ5 read requests */
3644 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
3646 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
3648 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
3650 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
3652 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
3654 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
3656 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
3658 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
3660 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
3662 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
3664 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
3666 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
3668 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
3670 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
3672 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
3674 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
3676 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
3678 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3680 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
3682 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
3684 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
3686 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
3688 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
3690 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
3692 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
3694 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
3696 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
3698 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
3700 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
3702 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
3704 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
3706 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
3708 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
3710 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
3712 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
3714 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
3716 /* [RW 10] Bandwidth addition to VQ29 write requests */
3718 /* [RW 10] Bandwidth addition to VQ30 write requests */
3720 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
3722 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
3724 /* [RW 7] Bandwidth upper bound for VQ29 */
3726 /* [RW 7] Bandwidth upper bound for VQ30 */
3728 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3730 /* [RW 2] Endian mode for cdu */
3734 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3740 /* [RW 2] Endian mode for debug */
3742 /* [RW 1] When '1'; requests will enter input buffers but wont get out
3745 /* [RW 4] Determines alignment of write SRs when a request is split into
3749 /* [RW 4] Determines alignment of read SRs when a request is split into
3753 /* [RW 1] when set the new alignment method (E2) will be applied; when reset
3756 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
3759 /* [RW 2] Endian mode for hc */
3761 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3768 /* [RW 13] Pending read limiter threshold; in Dwords */
3770 /* [RW 2] Endian mode for qm */
3774 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3777 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
3779 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3782 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3785 /* [RW 2] Endian mode for src */
3789 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3792 /* [RW 2] Endian mode for tm */
3796 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3801 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3867 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3870 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3873 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3876 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3879 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3882 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3885 /* [RW 10] if Number of entries in dmae fifo will be higher than this
3889 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3892 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3895 /* [RW 1] 0 - working in A0 mode;  - working in B0 mode */
3897 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3900 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3903 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3906 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3910 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3913 /* [RW 2] 0 - 128B;  - 256B;  - 512B;  - 1024B; when the payload in the
3921 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3928 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
3938 /* [RW 7] Indirect access to the permission table. The fields are : {Valid;
3942 /* [RW 32] Interrupt mask register #0 read/write */
3951 /* [RW 27] Parity mask register #0 read/write */
3957 /* [RW 4] The activity counter initial increment value sent in the load
3963 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3968 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3973 /* [RW 16] The byte credit cost for each task. This value is for both ports */
3975 /* [RW 16] The initial byte credit value for both ports. */
3977 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3980 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3983 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3986 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3989 /* [RW 16] The byte credit value that if above the QM is considered almost
3992 /* [RW 4] The initial credit for interface */
4002 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
4005 /* [RW 12] A bit vector which indicates which one of the queues are tied to
4015 /* [RW 20] The number of connections divided by 16 which dictates the size
4020 /* [RW 8] The context regions sent in the CFC load request */
4025 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
4028 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
4031 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
4034 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
4037 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
4040 /* [RW 4] If cleared then the secondary interface will not be served by the
4043 /* [RW 32] NA */
4045 /* [RW 32] NA */
4047 /* [RW 32] A mask register to mask the Almost empty signals which will not
4050 /* [RW 32] A mask register to mask the Almost empty signals which will not
4053 /* [RW 32] A mask register to mask the Almost empty signals which will not
4056 /* [RW 32] A mask register to mask the Almost empty signals which will not
4059 /* [RW 4] The number of outstanding request to CFC */
4082 /* [RW 2] The PCI attributes field used in the PCI request. */
4092 /* [RW 3] pci function number of queues 15-0 */
4109 /* [RW 2] Interrupt mask register #0 read/write */
4113 /* [RW 12] Parity mask register #0 read/write */
4131 /* [RW 4] Queue tied to VOQ */
4247 /* [RW 1] Initialization bit command */
4249 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
4265 /* [RW 16] The credit value that if above the QM is considered almost full */
4267 /* [RW 16] The init and maximum credit for each VoQ */
4273 /* [RW 1] The port of which VOQ belongs */
4277 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4279 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4281 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4283 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4285 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4287 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4289 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4291 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4293 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4295 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4297 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4299 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4301 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4303 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4305 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4307 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4309 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4311 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4313 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4315 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4317 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4319 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4321 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4323 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4325 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4327 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4329 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4331 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4333 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4335 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4337 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4339 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4341 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4343 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4345 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4347 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4349 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4351 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4353 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4355 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4357 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4359 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4361 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4363 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4365 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4367 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4369 /* [RW 32] Wrr weights */
4407 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
4426 /* [RW 1] Reset internal state machines. */
4430 /* [RW 3] Parity mask register #0 read/write */
4438 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4442 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4446 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4450 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4454 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4458 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4462 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4469 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4473 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
4475 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4477 /* [RW 8] The Event ID for Timers expiration. */
4479 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4483 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4487 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4492 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4496 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4500 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4511 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4518 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4530 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4537 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4541 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4546 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4550 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4554 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4558 /* [RW 11] Interrupt mask register #0 read/write */
4562 /* [RW 27] Parity mask register #0 read/write */
4568 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4573 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4577 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4581 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4585 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4587 /* [RW 28] The CM header for Timers expiration command. */
4589 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4593 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4597 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4601 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4605 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4609 /* [RW 28] The CM header value for QM request (primary). */
4611 /* [RW 28] The CM header value for QM request (secondary). */
4613 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4617 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4624 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4628 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4635 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4639 /* [RW 21] Indirect access to the descriptor table of the XX protection
4646 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4652 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
4655 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4658 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4660 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4664 /* [RW 4] Load value for cfc ac credit cnt. */
4666 /* [RW 4] Load value for cfc cld credit cnt. */
4668 /* [RW 8] Client0 context region. */
4670 /* [RW 8] Client1 context region. */
4672 /* [RW 8] Client2 context region. */
4674 /* [RW 2] Client in High priority client number. */
4676 /* [RW 4] Load value for clout0 cred cnt. */
4678 /* [RW 4] Load value for clout1 cred cnt. */
4680 /* [RW 4] Load value for clout2 cred cnt. */
4682 /* [RW 1] Enable client0 input. */
4684 /* [RW 1] Enable client1 input. */
4686 /* [RW 1] Enable client2 input. */
4689 /* [RW 1] Enable real time counter. */
4691 /* [RW 1] Enable for Timers state machines. */
4693 /* [RW 4] Load value for expiration credit cnt. CFC max number of
4696 /* [RW 32] Linear0 logic address. */
4698 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
4704 /* [RW 1] Linear0 physical address valid. */
4707 /* [RW 24] Linear0 array scan timeout. */
4710 /* [RW 32] Linear1 logic address. */
4714 /* [RW 1] Linear1 physical address valid. */
4716 /* [RW 6] Linear timer set_clear fifo threshold. */
4718 /* [RW 2] Load value for pci arbiter credit cnt. */
4720 /* [RW 20] The amount of hardware cycles for each timer tick. */
4722 /* [RW 8] Timers Context region. */
4724 /* [RW 1] Interrupt mask register #0 read/write */
4728 /* [RW 7] Parity mask register #0 read/write */
4734 /* [RW 8] The event id for aggregated interrupt 0 */
4740 /* [RW 1] The T bit for aggregated interrupt 0 */
4743 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4745 /* [RW 16] The maximum value of the completion counter #0 */
4747 /* [RW 16] The maximum value of the completion counter #1 */
4749 /* [RW 16] The maximum value of the completion counter #2 */
4751 /* [RW 16] The maximum value of the completion counter #3 */
4753 /* [RW 13] The start address in the internal RAM for the completion
4760 /* [RW 4] The initial number of messages that can be sent to the pxp control
4791 /* [RW 13] The start address in the internal RAM for the packet end message */
4793 /* [RW 13] The start address in the internal RAM for queue counters */
4801 /* [RW 32] Tick for timer counter. Applicable only when
4804 /* [RW 32] Interrupt mask register #0 read/write */
4810 /* [RW 11] Parity mask register #0 read/write */
4816 /* [RW 5] The number of time_slots in the arbitration cycle */
4818 /* [RW 3] The source that is associated with arbitration element 0. Source
4822 /* [RW 3] The source that is associated with arbitration element 1. Source
4827 /* [RW 3] The source that is associated with arbitration element 2. Source
4833 /* [RW 3] The source that is associated with arbitration element 3. Source
4840 /* [RW 3] The source that is associated with arbitration element 4. Source
4850 /* [RW 32] This address space contains all registers and memories that are
4855 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4858 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4861 /* [RW 15] Interrupt table Read and write access to it is not possible in
4882 /* [RW 1] Disables input messages from the passive buffer May be updated
4893 /* [RW 8] List of free threads . There is a bit per thread. */
4898 /* [RW 3] The arbitration scheme of time_slot 0 */
4900 /* [RW 3] The arbitration scheme of time_slot 10 */
4902 /* [RW 3] The arbitration scheme of time_slot 11 */
4904 /* [RW 3] The arbitration scheme of time_slot 12 */
4906 /* [RW 3] The arbitration scheme of time_slot 13 */
4908 /* [RW 3] The arbitration scheme of time_slot 14 */
4910 /* [RW 3] The arbitration scheme of time_slot 15 */
4912 /* [RW 3] The arbitration scheme of time_slot 16 */
4914 /* [RW 3] The arbitration scheme of time_slot 17 */
4916 /* [RW 3] The arbitration scheme of time_slot 18 */
4918 /* [RW 3] The arbitration scheme of time_slot 1 */
4920 /* [RW 3] The arbitration scheme of time_slot 2 */
4922 /* [RW 3] The arbitration scheme of time_slot 3 */
4924 /* [RW 3] The arbitration scheme of time_slot 4 */
4926 /* [RW 3] The arbitration scheme of time_slot 5 */
4928 /* [RW 3] The arbitration scheme of time_slot 6 */
4930 /* [RW 3] The arbitration scheme of time_slot 7 */
4932 /* [RW 3] The arbitration scheme of time_slot 8 */
4934 /* [RW 3] The arbitration scheme of time_slot 9 */
4936 /* [RW 32] Interrupt mask register #0 read/write */
4942 /* [RW 32] Parity mask register #0 read/write */
4951 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4958 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4962 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4966 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4970 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4974 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4978 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4982 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4989 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4993 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5000 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5004 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
5006 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
5008 /* [RW 8] The Event ID for Timers expiration. */
5010 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5014 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5018 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
5023 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5027 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5031 /* [RW 2] The queue index for invalidate counter flag decision. */
5033 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5052 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
5057 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5061 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5065 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5069 /* [RW 28] The CM header for Timers expiration command. */
5071 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5075 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5079 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5086 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5090 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5094 /* [RW 11] Interrupt mask register #0 read/write */
5098 /* [RW 27] Parity mask register #0 read/write */
5104 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
5109 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5113 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5117 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5121 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5125 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5127 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5131 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5135 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5139 /* [RW 28] The CM header value for QM request (primary). */
5141 /* [RW 28] The CM header value for QM request (secondary). */
5143 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5147 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5154 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5158 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
5165 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
5169 /* [RW 20] Indirect access to the descriptor table of the XX protection
5176 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
5181 /* [RW 6] The maximum number of pending messages; which may be stored in XX
5184 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5186 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
5201 /* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE
5205 /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
5208 /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
5211 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
5216 /* [RW 8] The event id for aggregated interrupt 0 */
5223 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5230 /* [RW 1] The T bit for aggregated interrupt 5 */
5233 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5235 /* [RW 16] The maximum value of the completion counter #0 */
5237 /* [RW 16] The maximum value of the completion counter #1 */
5239 /* [RW 16] The maximum value of the completion counter #2 */
5241 /* [RW 16] The maximum value of the completion counter #3 */
5243 /* [RW 13] The start address in the internal RAM for the completion
5250 /* [RW 4] The initial number of messages that can be sent to the pxp control
5283 /* [RW 13] The start address in the internal RAM for the packet end message */
5285 /* [RW 13] The start address in the internal RAM for queue counters */
5293 /* [RW 32] Tick for timer counter. Applicable only when
5296 /* [RW 32] Interrupt mask register #0 read/write */
5302 /* [RW 11] Parity mask register #0 read/write */
5308 /* [RW 5] The number of time_slots in the arbitration cycle */
5310 /* [RW 3] The source that is associated with arbitration element 0. Source
5314 /* [RW 3] The source that is associated with arbitration element 1. Source
5319 /* [RW 3] The source that is associated with arbitration element 2. Source
5325 /* [RW 3] The source that is associated with arbitration element 3. Source
5332 /* [RW 3] The source that is associated with arbitration element 4. Source
5342 /* [RW 32] This address space contains all registers and memories that are
5347 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5350 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5353 /* [RW 15] Interrupt table Read and write access to it is not possible in
5374 /* [RW 1] Disables input messages from the passive buffer May be updated
5385 /* [RW 16] List of free threads . There is a bit per thread. */
5387 /* [RW 3] The arbitration scheme of time_slot 0 */
5389 /* [RW 3] The arbitration scheme of time_slot 10 */
5391 /* [RW 3] The arbitration scheme of time_slot 11 */
5393 /* [RW 3] The arbitration scheme of time_slot 12 */
5395 /* [RW 3] The arbitration scheme of time_slot 13 */
5397 /* [RW 3] The arbitration scheme of time_slot 14 */
5399 /* [RW 3] The arbitration scheme of time_slot 15 */
5401 /* [RW 3] The arbitration scheme of time_slot 16 */
5403 /* [RW 3] The arbitration scheme of time_slot 17 */
5405 /* [RW 3] The arbitration scheme of time_slot 18 */
5407 /* [RW 3] The arbitration scheme of time_slot 1 */
5409 /* [RW 3] The arbitration scheme of time_slot 2 */
5411 /* [RW 3] The arbitration scheme of time_slot 3 */
5413 /* [RW 3] The arbitration scheme of time_slot 4 */
5415 /* [RW 3] The arbitration scheme of time_slot 5 */
5417 /* [RW 3] The arbitration scheme of time_slot 6 */
5419 /* [RW 3] The arbitration scheme of time_slot 7 */
5421 /* [RW 3] The arbitration scheme of time_slot 8 */
5423 /* [RW 3] The arbitration scheme of time_slot 9 */
5425 /* [RW 32] Interrupt mask register #0 read/write */
5431 /* [RW 32] Parity mask register #0 read/write */
5446 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
5451 /* [RW 2] The queue index for registration on Aux1 counter flag. */
5453 /* [RW 2] Per each decision rule the queue index to register to. */
5457 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5461 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5465 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5469 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5473 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
5477 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5481 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
5488 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
5492 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5499 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5503 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
5505 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
5507 /* [RW 8] The Event ID for Timers expiration. */
5509 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5513 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5521 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5526 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5530 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5534 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5541 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
5545 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5552 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5563 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5570 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
5576 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
5581 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5585 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5589 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5593 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5597 /* [RW 28] The CM header for Timers expiration command. */
5599 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5603 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5610 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5614 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
5616 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
5623 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5639 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5643 /* [RW 14] Interrupt mask register #0 read/write */
5647 /* [RW 30] Parity mask register #0 read/write */
5654 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5659 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5663 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5667 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5671 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5675 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
5677 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
5679 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5683 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5687 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5691 /* [RW 28] The CM header value for QM request (primary). */
5693 /* [RW 28] The CM header value for QM request (secondary). */
5695 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5699 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5706 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5710 /* [RW 17] Indirect access to the descriptor table of the XX protection
5717 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
5723 /* [RW 6] The maximum number of pending messages; which may be stored in XX
5726 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
5744 /* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5747 /* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC
5757 /* [RW 14] Maximum packet size in receive direction; exclusive of preamble &
5763 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
5767 /* [RW 8] The event id for aggregated interrupt 0 */
5783 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5787 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
5789 /* [RW 16] The maximum value of the completion counter #0 */
5791 /* [RW 16] The maximum value of the completion counter #1 */
5793 /* [RW 16] The maximum value of the completion counter #2 */
5795 /* [RW 16] The maximum value of the completion counter #3 */
5797 /* [RW 13] The start address in the internal RAM for the completion
5804 /* [RW 4] The initial number of messages that can be sent to the pxp control
5835 /* [RW 13] The start address in the internal RAM for queue counters */
5847 /* [RW 32] Tick for timer counter. Applicable only when
5850 /* [RW 32] Interrupt mask register #0 read/write */
5856 /* [RW 11] Parity mask register #0 read/write */
5862 /* [RW 5] The number of time_slots in the arbitration cycle */
5864 /* [RW 3] The source that is associated with arbitration element 0. Source
5868 /* [RW 3] The source that is associated with arbitration element 1. Source
5873 /* [RW 3] The source that is associated with arbitration element 2. Source
5879 /* [RW 3] The source that is associated with arbitration element 3. Source
5886 /* [RW 3] The source that is associated with arbitration element 4. Source
5896 /* [RW 32] This address space contains all registers and memories that are
5901 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5904 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5907 /* [RW 15] Interrupt table Read and write access to it is not possible in
5928 /* [RW 1] Disables input messages from the passive buffer May be updated
5939 /* [RW 16] List of free threads . There is a bit per thread. */
5941 /* [RW 3] The arbitration scheme of time_slot 0 */
5943 /* [RW 3] The arbitration scheme of time_slot 10 */
5945 /* [RW 3] The arbitration scheme of time_slot 11 */
5947 /* [RW 3] The arbitration scheme of time_slot 12 */
5949 /* [RW 3] The arbitration scheme of time_slot 13 */
5951 /* [RW 3] The arbitration scheme of time_slot 14 */
5953 /* [RW 3] The arbitration scheme of time_slot 15 */
5955 /* [RW 3] The arbitration scheme of time_slot 16 */
5957 /* [RW 3] The arbitration scheme of time_slot 17 */
5959 /* [RW 3] The arbitration scheme of time_slot 18 */
5961 /* [RW 3] The arbitration scheme of time_slot 1 */
5963 /* [RW 3] The arbitration scheme of time_slot 2 */
5965 /* [RW 3] The arbitration scheme of time_slot 3 */
5967 /* [RW 3] The arbitration scheme of time_slot 4 */
5969 /* [RW 3] The arbitration scheme of time_slot 5 */
5971 /* [RW 3] The arbitration scheme of time_slot 6 */
5973 /* [RW 3] The arbitration scheme of time_slot 7 */
5975 /* [RW 3] The arbitration scheme of time_slot 8 */
5977 /* [RW 3] The arbitration scheme of time_slot 9 */
5982 /* [RW 32] Interrupt mask register #0 read/write */
5988 /* [RW 32] Parity mask register #0 read/write */