Lines Matching +full:hw +full:- +full:gro
3 * Copyright (c) 2007-2013 Broadcom Corporation
32 extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
39 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
55 void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
64 void *x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
80 * bnx2x_send_unload_req - request unload mode from the MCP.
90 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
98 * bnx2x_config_rss_pf - configure RSS parameters in a PF.
103 * @config_hash: re-configure RSS hash keys configuration
110 * bnx2x__init_func_obj - init function object
121 * bnx2x_setup_queue - setup eth queue.
132 * bnx2x_setup_leading - bring up a leading eth queue.
139 * bnx2x_fw_command - send the MCP a request
150 * bnx2x_initial_phy_init - initialize link parameters structure variables.
158 * bnx2x_link_set - configure hw according to link parameters structure.
165 * bnx2x_force_link_reset - Forces link reset, and put the PHY
173 * bnx2x_link_test - query link status.
183 * bnx2x_drv_pulse - write driver pulse to shmem
187 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
193 * bnx2x_igu_ack_sb - update IGU with current SB value
200 * @update: is HW update required
210 * bnx2x__link_status_update - handles link status change.
217 * bnx2x_link_report - report link status to upper layer.
223 /* None-atomic version of bnx2x_link_report() */
227 * bnx2x_get_mf_speed - calculate MF speed.
236 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
244 * bnx2x_interrupt - non MSI-X interrupt handler
252 * bnx2x_cnic_notify - send command to cnic driver
260 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
267 * bnx2x_setup_cnic_info - provides cnic with updated info
274 * bnx2x_int_enable - enable HW interrupts.
281 * bnx2x_int_disable_sync - disable interrupts.
284 * @disable_hw: true, disable HW interrupts.
292 * bnx2x_nic_init_cnic - init driver internals for cnic.
298 * - rings
299 * - status blocks
300 * - etc.
305 * bnx2x_preirq_nic_init - init driver internals.
310 * - fastpath object
311 * - fastpath rings
317 * bnx2x_postirq_nic_init - init driver internals.
323 * - status blocks
324 * - slowpath rings
325 * - etc.
329 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic.
335 * bnx2x_alloc_mem - allocate driver's memory.
342 * bnx2x_free_mem_cnic - release driver's memory for cnic.
348 * bnx2x_free_mem - release driver's memory.
355 * bnx2x_set_num_queues - set number of queues according to mode.
362 * bnx2x_chip_cleanup - cleanup chip internals.
368 * - Cleanup MAC configuration.
369 * - Closes clients.
370 * - etc.
375 * bnx2x_acquire_hw_lock - acquire HW lock.
383 * bnx2x_release_hw_lock - release HW lock.
391 * bnx2x_release_leader_lock - release recovery leader lock
398 * bnx2x_set_eth_mac - configure eth MAC address in the HW
403 * Configures according to the value in netdev->dev_addr.
408 * bnx2x_set_rx_mode - set MAC filtering configurations.
413 * If bp->state is OPEN, should be called with
431 * bnx2x_sp_event - handle ramrods completion.
439 * bnx2x_ilt_set_info - prepare ILT configurations.
446 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC
454 * bnx2x_dcbx_init - initialize dcbx protocol.
461 * bnx2x_set_power_state - set power state to the requested value.
471 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
521 * This is only applicable for weak-ordered memory model archs such in bnx2x_update_rx_prod()
522 * as IA-64. The following barrier is also mandatory since FW will in bnx2x_update_rx_prod()
528 REG_WR_RELAXED(bp, fp->ustorm_rx_prods_offset + i * 4, in bnx2x_update_rx_prod()
533 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); in bnx2x_update_rx_prod()
558 * bnx2x_enable_msix - set msix configuration.
568 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
575 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
582 * bnx2x_free_mem_bp - release memories outsize main driver structure
589 * bnx2x_change_mtu - change mtu netdev callback
599 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
614 * bnx2x_tx_timeout - tx timeout netdev callback
620 /** bnx2x_get_c2s_mapping - read inner-to-outer vlan configuration
624 * @c2s_default: entry for non-tagged configuration
633 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; in bnx2x_update_fpsb_idx()
679 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_ack_sb()
686 else if (igu_sb_id != bp->igu_dsb_id) in bnx2x_ack_sb()
721 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_ack_int()
731 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; in bnx2x_has_tx_work_unload()
741 prod = txdata->tx_bd_prod; in bnx2x_tx_avail()
742 cons = txdata->tx_bd_cons; in bnx2x_tx_avail()
748 WARN_ON(used > txdata->tx_ring_size); in bnx2x_tx_avail()
749 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); in bnx2x_tx_avail()
752 return (s16)(txdata->tx_ring_size) - used; in bnx2x_tx_avail()
761 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); in bnx2x_tx_queue_has_work()
762 return hw_cons != txdata->tx_pkt_cons; in bnx2x_tx_queue_has_work()
769 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) in bnx2x_has_tx_work()
774 #define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0)
775 #define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF)
782 cons = RCQ_BD(fp->rx_comp_cons); in bnx2x_has_rx_work()
783 cqe = &fp->rx_comp_ring[cons]; in bnx2x_has_rx_work()
784 cqe_fp = &cqe->fast_path_cqe; in bnx2x_has_rx_work()
789 * bnx2x_tx_disable - disables tx from stack point of view
795 netif_tx_disable(bp->dev); in bnx2x_tx_disable()
796 netif_carrier_off(bp->dev); in bnx2x_tx_disable()
802 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; in bnx2x_free_rx_sge()
803 struct page *page = sw_buf->page; in bnx2x_free_rx_sge()
804 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; in bnx2x_free_rx_sge()
813 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), in bnx2x_free_rx_sge()
818 sw_buf->page = NULL; in bnx2x_free_rx_sge()
819 sge->addr_hi = 0; in bnx2x_free_rx_sge()
820 sge->addr_lo = 0; in bnx2x_free_rx_sge()
847 if (bp->flags & USING_MSIX_FLAG) { in bnx2x_disable_msi()
848 pci_disable_msix(bp->pdev); in bnx2x_disable_msi()
849 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); in bnx2x_disable_msi()
850 } else if (bp->flags & USING_MSI_FLAG) { in bnx2x_disable_msi()
851 pci_disable_msi(bp->pdev); in bnx2x_disable_msi()
852 bp->flags &= ~USING_MSI_FLAG; in bnx2x_disable_msi()
861 int idx = RX_SGE_CNT * i - 1; in bnx2x_clear_sge_mask_next_elems()
864 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); in bnx2x_clear_sge_mask_next_elems()
865 idx--; in bnx2x_clear_sge_mask_next_elems()
872 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ in bnx2x_init_sge_ring_bit_mask()
873 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); in bnx2x_init_sge_ring_bit_mask()
890 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; in bnx2x_reuse_rx_data()
891 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; in bnx2x_reuse_rx_data()
892 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; in bnx2x_reuse_rx_data()
893 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; in bnx2x_reuse_rx_data()
897 prod_rx_buf->data = cons_rx_buf->data; in bnx2x_reuse_rx_data()
911 return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true); in bnx2x_config_rss_eth()
915 * bnx2x_func_start - init function
931 func_params.f_obj = &bp->func_obj; in bnx2x_func_start()
935 start_params->mf_mode = bp->mf_mode; in bnx2x_func_start()
936 start_params->sd_vlan_tag = bp->mf_ov; in bnx2x_func_start()
941 start_params->sd_vlan_eth_type = ETH_P_8021AD; in bnx2x_func_start()
946 bnx2x_get_c2s_mapping(bp, start_params->c2s_pri, in bnx2x_func_start()
947 &start_params->c2s_pri_default); in bnx2x_func_start()
948 start_params->c2s_pri_valid = 1; in bnx2x_func_start()
951 "Inner-to-Outer priority: %02x %02x %02x %02x %02x %02x %02x %02x [Default %02x]\n", in bnx2x_func_start()
952 start_params->c2s_pri[0], start_params->c2s_pri[1], in bnx2x_func_start()
953 start_params->c2s_pri[2], start_params->c2s_pri[3], in bnx2x_func_start()
954 start_params->c2s_pri[4], start_params->c2s_pri[5], in bnx2x_func_start()
955 start_params->c2s_pri[6], start_params->c2s_pri[7], in bnx2x_func_start()
956 start_params->c2s_pri_default); in bnx2x_func_start()
960 start_params->network_cos_mode = STATIC_COS; in bnx2x_func_start()
962 start_params->network_cos_mode = FW_WRR; in bnx2x_func_start()
963 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]) { in bnx2x_func_start()
964 port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN]; in bnx2x_func_start()
965 start_params->vxlan_dst_port = port; in bnx2x_func_start()
967 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]) { in bnx2x_func_start()
968 port = bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE]; in bnx2x_func_start()
969 start_params->geneve_dst_port = port; in bnx2x_func_start()
972 start_params->inner_rss = 1; in bnx2x_func_start()
975 start_params->class_fail_ethtype = ETH_P_FIP; in bnx2x_func_start()
976 start_params->class_fail = 1; in bnx2x_func_start()
977 start_params->no_added_tags = 1; in bnx2x_func_start()
984 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
1005 put_page(pool->page); in bnx2x_free_rx_mem_pool()
1007 pool->page = NULL; in bnx2x_free_rx_mem_pool()
1015 if (!fp->page_pool.page) in bnx2x_free_rx_sge_range()
1018 if (fp->mode == TPA_MODE_DISABLED) in bnx2x_free_rx_sge_range()
1024 bnx2x_free_rx_mem_pool(bp, &fp->page_pool); in bnx2x_free_rx_sge_range()
1034 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; in bnx2x_set_next_page_rx_bd()
1035 rx_bd->addr_hi = in bnx2x_set_next_page_rx_bd()
1036 cpu_to_le32(U64_HI(fp->rx_desc_mapping + in bnx2x_set_next_page_rx_bd()
1038 rx_bd->addr_lo = in bnx2x_set_next_page_rx_bd()
1039 cpu_to_le32(U64_LO(fp->rx_desc_mapping + in bnx2x_set_next_page_rx_bd()
1049 struct bnx2x *bp = fp->bp; in bnx2x_stats_id()
1053 return bp->cnic_base_cl_id + (bp->pf_num >> 1); in bnx2x_stats_id()
1054 return fp->cl_id; in bnx2x_stats_id()
1056 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; in bnx2x_stats_id()
1062 struct bnx2x *bp = fp->bp; in bnx2x_init_vlan_mac_fp_objs()
1065 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, in bnx2x_init_vlan_mac_fp_objs()
1066 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), in bnx2x_init_vlan_mac_fp_objs()
1069 &bp->sp_state, obj_type, in bnx2x_init_vlan_mac_fp_objs()
1070 &bp->macs_pool); in bnx2x_init_vlan_mac_fp_objs()
1074 fp->cl_id, fp->cid, BP_FUNC(bp), in bnx2x_init_vlan_mac_fp_objs()
1078 &bp->sp_state, obj_type, in bnx2x_init_vlan_mac_fp_objs()
1079 &bp->vlans_pool); in bnx2x_init_vlan_mac_fp_objs()
1083 * bnx2x_get_path_func_num - get number of active functions
1094 /* 57710 has only one function per-port */ in bnx2x_get_path_func_num()
1125 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); in bnx2x_init_bp_objs()
1128 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, in bnx2x_init_bp_objs()
1132 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, in bnx2x_init_bp_objs()
1136 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), in bnx2x_init_bp_objs()
1139 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_FUNC(bp), in bnx2x_init_bp_objs()
1143 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, in bnx2x_init_bp_objs()
1144 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), in bnx2x_init_bp_objs()
1147 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, in bnx2x_init_bp_objs()
1150 bp->vlan_credit = PF_VLAN_CREDIT_E2(bp, bnx2x_get_path_func_num(bp)); in bnx2x_init_bp_objs()
1155 if (CHIP_IS_E1x(fp->bp)) in bnx2x_fp_qzone_id()
1156 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; in bnx2x_fp_qzone_id()
1158 return fp->cl_id; in bnx2x_fp_qzone_id()
1166 txdata->cid = cid; in bnx2x_init_txdata()
1167 txdata->txq_index = txq_index; in bnx2x_init_txdata()
1168 txdata->tx_cons_sb = tx_cons_sb; in bnx2x_init_txdata()
1169 txdata->parent_fp = fp; in bnx2x_init_txdata()
1170 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; in bnx2x_init_txdata()
1173 txdata->cid, txdata->txq_index); in bnx2x_init_txdata()
1178 return bp->cnic_base_cl_id + cl_idx + in bnx2x_cnic_eth_cl_id()
1179 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; in bnx2x_cnic_eth_cl_id()
1185 return bp->base_fw_ndsb; in bnx2x_cnic_fw_sb_id()
1190 return bp->igu_base_sb; in bnx2x_cnic_igu_sb_id()
1200 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", in bnx2x_clean_tx_queue()
1201 txdata->txq_index, txdata->tx_pkt_prod, in bnx2x_clean_tx_queue()
1202 txdata->tx_pkt_cons); in bnx2x_clean_tx_queue()
1205 return -EBUSY; in bnx2x_clean_tx_queue()
1210 cnt--; in bnx2x_clean_tx_queue()
1228 * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
1237 while (tout--) { in bnx2x_wait_sp_comp()
1239 netif_addr_lock_bh(bp->dev); in bnx2x_wait_sp_comp()
1240 if (!(bp->sp_state & mask)) { in bnx2x_wait_sp_comp()
1241 netif_addr_unlock_bh(bp->dev); in bnx2x_wait_sp_comp()
1244 netif_addr_unlock_bh(bp->dev); in bnx2x_wait_sp_comp()
1251 netif_addr_lock_bh(bp->dev); in bnx2x_wait_sp_comp()
1252 if (bp->sp_state & mask) { in bnx2x_wait_sp_comp()
1254 bp->sp_state, mask); in bnx2x_wait_sp_comp()
1255 netif_addr_unlock_bh(bp->dev); in bnx2x_wait_sp_comp()
1258 netif_addr_unlock_bh(bp->dev); in bnx2x_wait_sp_comp()
1264 * bnx2x_set_ctx_validation - set CDU context validation values
1279 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
1291 "Max BW configured to 0 - using 100 instead\n"); in bnx2x_extract_max_cfg()
1297 /* checks if HW supports GRO for given MTU */
1300 /* gro frags per page */ in bnx2x_mtu_allows_gro()
1301 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); in bnx2x_mtu_allows_gro()
1311 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
1319 * bnx2x_link_sync_notify - send notification to other functions.
1341 * bnx2x_update_drv_flags - update flags in shmem
1369 * bnx2x_fill_fw_str - Fill buffer with FW version string
1385 * bnx2x_set_os_driver_state - write driver state for management FW usage
1393 * bnx2x_nvram_read - reads data from nvram [might sleep]