Lines Matching +full:0 +full:x0001
43 #define PCI_REG_COMMAND 0x04 /* PCI Command Register */
44 #define CMD_IO_SPACE 0x0001
45 #define CMD_MEMORY_SPACE 0x0002
46 #define CMD_BUS_MASTER 0x0004
48 #define BAR_0 0
53 #define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
54 #define AT_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
55 #define AT_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
56 #define AT_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */
57 #define AT_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
59 #define SPEED_0 0xffff
74 #define MAX_JUMBO_FRAME_SIZE 0x2000
81 _vlan = (((_tpd) >> 8) | (((_tpd) & 0x77) << 9) |\
82 (((_tdp) & 0x88) << 5))
87 #define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
88 #define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
105 #define TPD_BUFLEN_MASK 0x3FFF
106 #define TPD_BUFLEN_SHIFT 0
107 #define TPD_DMAINT_MASK 0x0001
109 #define TPD_PKTNT_MASK 0x0001
111 #define TPD_VLANTAG_MASK 0xFFFF
114 /* tpd word 3 bits 0:4 */
115 #define TPD_EOP_MASK 0x0001
116 #define TPD_EOP_SHIFT 0
117 #define TPD_IP_VERSION_MASK 0x0001
118 #define TPD_IP_VERSION_SHIFT 1 /* 0 : IPV4, 1 : IPV6 */
119 #define TPD_INS_VL_TAG_MASK 0x0001
121 #define TPD_CC_SEGMENT_EN_MASK 0x0001
123 #define TPD_SEGMENT_EN_MASK 0x0001
126 /* tdp word 3 bits 5:7 if ip version is 0 */
127 #define TPD_IP_CSUM_MASK 0x0001
129 #define TPD_TCP_CSUM_MASK 0x0001
131 #define TPD_UDP_CSUM_MASK 0x0001
135 #define TPD_V6_IPHLLO_MASK 0x0007
139 #define TPD_VL_TAGGED_MASK 0x0001
141 #define TPD_ETHTYPE_MASK 0x0001
144 /* tdp word 3 bits 10:13 if ip version is 0 */
145 #define TDP_V4_IPHL_MASK 0x000F
149 #define TPD_V6_IPHLHI_MASK 0x000F
153 #define TPD_TCPHDRLEN_MASK 0x000F
155 #define TPD_HDRFLAG_MASK 0x0001
157 #define TPD_MSS_MASK 0x1FFF
161 #define TPD_PLOADOFFSET_MASK 0x00FF
163 #define TPD_CCSUMOFFSET_MASK 0x00FF
172 /* how about 0x2000 */
173 #define MAX_TX_BUF_LEN 0x2000
175 #define MAX_TSO_SEG_SIZE 0x3c00
177 /* rrs word 1 bit 0:31 */
178 #define RRS_RX_CSUM_MASK 0xFFFF
179 #define RRS_RX_CSUM_SHIFT 0
180 #define RRS_PKT_SIZE_MASK 0x3FFF
182 #define RRS_CPU_NUM_MASK 0x0003
185 #define RRS_IS_RSS_IPV4 0x0001
186 #define RRS_IS_RSS_IPV4_TCP 0x0002
187 #define RRS_IS_RSS_IPV6 0x0004
188 #define RRS_IS_RSS_IPV6_TCP 0x0008
189 #define RRS_IS_IPV6 0x0010
190 #define RRS_IS_IP_FRAG 0x0020
191 #define RRS_IS_IP_DF 0x0040
192 #define RRS_IS_802_3 0x0080
193 #define RRS_IS_VLAN_TAG 0x0100
194 #define RRS_IS_ERR_FRAME 0x0200
195 #define RRS_IS_IPV4 0x0400
196 #define RRS_IS_UDP 0x0800
197 #define RRS_IS_TCP 0x1000
198 #define RRS_IS_BCAST 0x2000
199 #define RRS_IS_MCAST 0x4000
200 #define RRS_IS_PAUSE 0x8000
202 #define RRS_ERR_BAD_CRC 0x0001
203 #define RRS_ERR_CODE 0x0002
204 #define RRS_ERR_DRIBBLE 0x0004
205 #define RRS_ERR_RUNT 0x0008
206 #define RRS_ERR_RX_OVERFLOW 0x0010
207 #define RRS_ERR_TRUNC 0x0020
208 #define RRS_ERR_IP_CSUM 0x0040
209 #define RRS_ERR_L4_CSUM 0x0080
210 #define RRS_ERR_LENGTH 0x0100
211 #define RRS_ERR_DES_ADDR 0x0200
224 atl1e_dma_req_128 = 0,
233 atl1e_rrs_disable = 0,
241 athr_l1e = 0,
320 #define MEDIA_TYPE_AUTO_SENSOR 0
327 #define ADVERTISE_10_HALF 0x0001
328 #define ADVERTISE_10_FULL 0x0002
329 #define ADVERTISE_100_HALF 0x0004
330 #define ADVERTISE_100_FULL 0x0008
331 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
332 #define ADVERTISE_1000_FULL 0x0020
367 #define ATL1E_TX_PCIMAP_SINGLE 0x0001
368 #define ATL1E_TX_PCIMAP_PAGE 0x0002
369 #define ATL1E_TX_PCIMAP_TYPE_MASK 0x0003
377 } while (0)
448 #define __AT_TESTING 0x0001
449 #define __AT_RESETTING 0x0002
450 #define __AT_DOWN 0x0003