127 #define XGBE_PHY_PORT_SPEED_10		BIT(0)
133 #define XGBE_MUTEX_RELEASE		0x80000000
138 #define XGBE_SFP_SERIAL_ID_ADDRESS	0x50
139 #define XGBE_SFP_DIAG_INFO_ADDRESS	0x51
140 #define XGBE_SFP_PHY_ADDRESS		0x56
141 #define XGBE_GPIO_ADDRESS_PCA9555	0x20
144 #define XGBE_GPIO_NO_TX_FAULT		BIT(0)
161 	XGBE_PORT_MODE_RSVD = 0,
175 	XGBE_CONN_TYPE_NONE = 0,
185 	XGBE_SFP_COMM_DIRECT = 0,
190 	XGBE_SFP_CABLE_UNKNOWN = 0,
197 	XGBE_SFP_BASE_UNKNOWN = 0,
210 	XGBE_SFP_SPEED_UNKNOWN = 0,
216 /* SFP Serial ID Base ID values relative to an offset of 0 */
217 #define XGBE_SFP_BASE_ID			0
218 #define XGBE_SFP_ID_SFP				0x03
221 #define XGBE_SFP_EXT_ID_SFP			0x04
230 #define XGBE_SFP_BASE_1GBE_CC_SX		BIT(0)
240 #define XGBE_SFP_BASE_BR_1GBE_MIN		0x0a
241 #define XGBE_SFP_BASE_BR_10GBE_MIN		0x64
300 	XGBE_MDIO_RESET_NONE = 0,
308 	XGBE_PHY_REDRV_IF_MDIO = 0,
314 	XGBE_PHY_REDRV_MODEL_4223 = 0,
324 #define XGBE_PHY_REDRV_MODE_REG	0x12b0
413 	redrv_data[0] = ((reg >> 8) & 0xff) << 1;  in xgbe_phy_redrv_write()
414 	redrv_data[1] = reg & 0xff;  in xgbe_phy_redrv_write()
419 	csum = 0;  in xgbe_phy_redrv_write()
420 	for (i = 0; i < 4; i++) {  in xgbe_phy_redrv_write()
455 	if (redrv_data[0] != 0xff) {  in xgbe_phy_redrv_write()
527 		return 0;  in xgbe_phy_sfp_put_mux()
530 	mux_channel = 0;  in xgbe_phy_sfp_put_mux()
546 		return 0;  in xgbe_phy_sfp_get_mux()
580 	mutex_id = 0;  in xgbe_phy_get_comm_ownership()
597 		return 0;  in xgbe_phy_get_comm_ownership()
640 	mii_data[0] = reg & 0xff;  in xgbe_phy_i2c_mii_write()
932 	if ((phy_id & 0xfffffff0) != 0x01ff0cc0)  in xgbe_phy_finisar_phy_quirks()
936 	phy_write(phy_data->phydev, 0x16, 0x0001);  in xgbe_phy_finisar_phy_quirks()
937 	phy_write(phy_data->phydev, 0x00, 0x9140);  in xgbe_phy_finisar_phy_quirks()
938 	phy_write(phy_data->phydev, 0x16, 0x0000);  in xgbe_phy_finisar_phy_quirks()
941 	phy_write(phy_data->phydev, 0x1b, 0x9084);  in xgbe_phy_finisar_phy_quirks()
942 	phy_write(phy_data->phydev, 0x09, 0x0e00);  in xgbe_phy_finisar_phy_quirks()
943 	phy_write(phy_data->phydev, 0x00, 0x8140);  in xgbe_phy_finisar_phy_quirks()
944 	phy_write(phy_data->phydev, 0x04, 0x0d01);  in xgbe_phy_finisar_phy_quirks()
945 	phy_write(phy_data->phydev, 0x00, 0x9140);  in xgbe_phy_finisar_phy_quirks()
978 	if ((phy_id & 0xfffffff0) != 0x03625d10)  in xgbe_phy_belfuse_phy_quirks()
985 	phy_write(phy_data->phydev, 0x18, 0x7007);  in xgbe_phy_belfuse_phy_quirks()
986 	reg = phy_read(phy_data->phydev, 0x18);  in xgbe_phy_belfuse_phy_quirks()
987 	phy_write(phy_data->phydev, 0x18, reg & ~0x0080);  in xgbe_phy_belfuse_phy_quirks()
990 	phy_write(phy_data->phydev, 0x1c, 0x7c00);  in xgbe_phy_belfuse_phy_quirks()
991 	reg = phy_read(phy_data->phydev, 0x1c);  in xgbe_phy_belfuse_phy_quirks()
992 	reg &= 0x03ff;  in xgbe_phy_belfuse_phy_quirks()
993 	reg &= ~0x0001;  in xgbe_phy_belfuse_phy_quirks()
994 	phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0001);  in xgbe_phy_belfuse_phy_quirks()
997 	reg = phy_read(phy_data->phydev, 0x00);  in xgbe_phy_belfuse_phy_quirks()
998 	phy_write(phy_data->phydev, 0x00, reg | 0x00800);  in xgbe_phy_belfuse_phy_quirks()
1001 	phy_write(phy_data->phydev, 0x1c, 0x7c00);  in xgbe_phy_belfuse_phy_quirks()
1002 	reg = phy_read(phy_data->phydev, 0x1c);  in xgbe_phy_belfuse_phy_quirks()
1003 	reg &= 0x03ff;  in xgbe_phy_belfuse_phy_quirks()
1004 	reg &= ~0x0006;  in xgbe_phy_belfuse_phy_quirks()
1005 	phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg | 0x0004);  in xgbe_phy_belfuse_phy_quirks()
1008 	reg = phy_read(phy_data->phydev, 0x00);  in xgbe_phy_belfuse_phy_quirks()
1009 	phy_write(phy_data->phydev, 0x00, reg & ~0x00800);  in xgbe_phy_belfuse_phy_quirks()
1012 	phy_write(phy_data->phydev, 0x1c, 0x7c00);  in xgbe_phy_belfuse_phy_quirks()
1013 	reg = phy_read(phy_data->phydev, 0x1c);  in xgbe_phy_belfuse_phy_quirks()
1014 	reg &= 0x03ff;  in xgbe_phy_belfuse_phy_quirks()
1015 	reg &= ~0x0001;  in xgbe_phy_belfuse_phy_quirks()
1016 	phy_write(phy_data->phydev, 0x1c, 0x8000 | 0x7c00 | reg);  in xgbe_phy_belfuse_phy_quirks()
1019 	reg = phy_read(phy_data->phydev, 0x00);  in xgbe_phy_belfuse_phy_quirks()
1020 	phy_write(phy_data->phydev, 0x00, reg & ~0x00800);  in xgbe_phy_belfuse_phy_quirks()
1049 		return 0;  in xgbe_phy_find_phy_device()
1052 	pdata->an_again = 0;  in xgbe_phy_find_phy_device()
1056 		return 0;  in xgbe_phy_find_phy_device()
1061 		return 0;  in xgbe_phy_find_phy_device()
1109 	return 0;  in xgbe_phy_find_phy_device()
1120 	phy_data->sfp_phy_avail = 0;  in xgbe_phy_sfp_external_phy()
1127 	if (ret < 0)  in xgbe_phy_sfp_external_phy()
1256 	sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';  in xgbe_phy_sfp_eeprom_info()
1262 	sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';  in xgbe_phy_sfp_eeprom_info()
1268 	sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';  in xgbe_phy_sfp_eeprom_info()
1274 	sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';  in xgbe_phy_sfp_eeprom_info()
1283 	for (cc = 0; len; buf++, len--)  in xgbe_phy_sfp_verify_eeprom()
1304 	eeprom_addr = 0;  in xgbe_phy_sfp_read_eeprom()
1340 		phy_data->sfp_changed = 0;  in xgbe_phy_sfp_read_eeprom()
1356 	gpio_reg = 0;  in xgbe_phy_sfp_signals()
1366 	phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];  in xgbe_phy_sfp_signals()
1378 	phy_data->sfp_phy_avail = 0;  in xgbe_phy_sfp_mod_absent()
1379 	memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));  in xgbe_phy_sfp_mod_absent()
1384 	phy_data->sfp_rx_los = 0;  in xgbe_phy_sfp_reset()
1385 	phy_data->sfp_tx_fault = 0;  in xgbe_phy_sfp_reset()
1479 	eeprom_addr = 0;  in xgbe_phy_module_eeprom()
1494 		eeprom_addr = 0;  in xgbe_phy_module_eeprom()
1507 	for (i = 0, j = eeprom->offset; i < eeprom->len; i++, j++) {  in xgbe_phy_module_eeprom()
1550 	return 0;  in xgbe_phy_module_info()
1557 	u16 lcl_adv = 0, rmt_adv = 0;  in xgbe_phy_phydev_flowctrl()
1560 	pdata->phy.tx_pause = 0;  in xgbe_phy_phydev_flowctrl()
1561 	pdata->phy.rx_pause = 0;  in xgbe_phy_phydev_flowctrl()
1646 	if (lp_reg & 0x100)  in xgbe_phy_an37_outcome()
1648 	if (lp_reg & 0x80)  in xgbe_phy_an37_outcome()
1653 		pdata->phy.tx_pause = 0;  in xgbe_phy_an37_outcome()
1654 		pdata->phy.rx_pause = 0;  in xgbe_phy_an37_outcome()
1656 		if (ad_reg & lp_reg & 0x100) {  in xgbe_phy_an37_outcome()
1659 		} else if (ad_reg & lp_reg & 0x80) {  in xgbe_phy_an37_outcome()
1660 			if (ad_reg & 0x100)  in xgbe_phy_an37_outcome()
1662 			else if (lp_reg & 0x100)  in xgbe_phy_an37_outcome()
1667 	if (lp_reg & 0x20)  in xgbe_phy_an37_outcome()
1672 	mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;  in xgbe_phy_an37_outcome()
1694 	if (lp_reg & 0x80)  in xgbe_phy_an73_redrv_outcome()
1696 	if (lp_reg & 0x20)  in xgbe_phy_an73_redrv_outcome()
1700 	if (ad_reg & 0x80) {  in xgbe_phy_an73_redrv_outcome()
1710 	} else if (ad_reg & 0x20) {  in xgbe_phy_an73_redrv_outcome()
1757 	if (lp_reg & 0xc000)  in xgbe_phy_an73_redrv_outcome()
1775 	if (lp_reg & 0x400)  in xgbe_phy_an73_outcome()
1777 	if (lp_reg & 0x800)  in xgbe_phy_an73_outcome()
1782 		pdata->phy.tx_pause = 0;  in xgbe_phy_an73_outcome()
1783 		pdata->phy.rx_pause = 0;  in xgbe_phy_an73_outcome()
1785 		if (ad_reg & lp_reg & 0x400) {  in xgbe_phy_an73_outcome()
1788 		} else if (ad_reg & lp_reg & 0x800) {  in xgbe_phy_an73_outcome()
1789 			if (ad_reg & 0x400)  in xgbe_phy_an73_outcome()
1791 			else if (lp_reg & 0x400)  in xgbe_phy_an73_outcome()
1799 	if (lp_reg & 0x80)  in xgbe_phy_an73_outcome()
1801 	if (lp_reg & 0x20)  in xgbe_phy_an73_outcome()
1805 	if (ad_reg & 0x80)  in xgbe_phy_an73_outcome()
1807 	else if (ad_reg & 0x20)  in xgbe_phy_an73_outcome()
1815 	if (lp_reg & 0xc000)  in xgbe_phy_an73_outcome()
1913 		return 0;  in xgbe_phy_an_config()
1981 	redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);  in xgbe_phy_set_redrv_mode_mdio()
1996 	redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);  in xgbe_phy_set_redrv_mode_i2c()
2038 		pdata->rx_adapt_retries = 0;  in xgbe_set_rx_adap_mode()
2107 			pdata->rx_adapt_retries = 0;  in xgbe_phy_rx_adaptation()
2156 	unsigned int s0 = 0;  in xgbe_phy_perform_ratechange()
2175 	XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);  in xgbe_phy_perform_ratechange()
2239 	/* Rx-Adaptation is not supported on older platforms(< 0x30H) */  in enable_rx_adap()
2241 	if (ver < 0x30)  in enable_rx_adap()
2267 		pdata->en_rx_adap = 0;  in xgbe_phy_sfi_mode()
2772 		return (ver == 0x21 || ver >= 0x30);  in xgbe_phy_valid_speed_baset_mode()
2796 		return ((ver == 0x21 || ver >= 0x30) &&  in xgbe_phy_valid_speed_sfp_mode()
2861 	*an_restart = 0;  in xgbe_phy_link_status()
2869 			return 0;  in xgbe_phy_link_status()
2875 			return 0;  in xgbe_phy_link_status()
2882 		if (ret < 0)  in xgbe_phy_link_status()
2883 			return 0;  in xgbe_phy_link_status()
2887 			return 0;  in xgbe_phy_link_status()
2890 			return 0;  in xgbe_phy_link_status()
2933 		phy_data->rrc_count = 0;  in xgbe_phy_link_status()
2937 	return 0;  in xgbe_phy_link_status()
3034 	gpio_data[0] = 2;  in xgbe_phy_i2c_mdio_reset()
3035 	gpio_data[1] = gpio_ports[0];  in xgbe_phy_i2c_mdio_reset()
3069 		return 0;  in xgbe_phy_mdio_reset()
3114 		return 0;  in xgbe_phy_mdio_reset_setup()
3139 	return 0;  in xgbe_phy_mdio_reset_setup()
3149 	if ((ver < 0x30 && ver != 0x21) && (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10))  in xgbe_phy_port_mode_mismatch()
3263 	phy_data->phy_cdr_notrack = 0;  in xgbe_phy_cdr_track()
3406 	return 0;  in xgbe_phy_start()
3426 		return 0;  in xgbe_phy_reset()
3689 		dev_dbg(pdata->dev, "phy supported=0x%*pb\n",  in xgbe_phy_init()
3732 	mii->phy_mask = ~0;  in xgbe_phy_init()
3741 	return 0;  in xgbe_phy_init()