Lines Matching +full:flow +full:- +full:level
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #define OWL_EMAC_DRVNAME "owl-emac"
49 #define OWL_EMAC_VAL_MAC_CSR5_TS_DATA 0x03 /* Transferring data HOST -> FIFO */
55 #define OWL_EMAC_VAL_MAC_CSR5_RS_DATA 0x07 /* Transferring data FIFO -> HOST */
59 #define OWL_EMAC_BIT_MAC_CSR5_GTE BIT(11) /* General-purpose timer expiration */
98 #define OWL_EMAC_BIT_MAC_CSR7_GTE BIT(11) /* General-purpose timer overflow */
140 /* General-purpose timer and interrupt mitigation control register */
153 #define OWL_EMAC_OFF_MAC_CSR18_CPTL 24 /* Cache pause threshold level */
154 #define OWL_EMAC_OFF_MAC_CSR18_CRTL 16 /* Cache restart threshold level */
155 #define OWL_EMAC_OFF_MAC_CSR18_PQT 0 /* Flow control pause quanta time */
159 #define OWL_EMAC_OFF_MAC_CSR19_FPTL 16 /* FIFO pause threshold level */
160 #define OWL_EMAC_OFF_MAC_CSR19_FRTL 0 /* FIFO restart threshold level */
162 /* Flow control setup & status register */
164 #define OWL_EMAC_BIT_MAC_CSR20_FCE BIT(31) /* Flow Control Enable */
165 #define OWL_EMAC_BIT_MAC_CSR20_TUE BIT(30) /* Transmit Un-pause frames Enable */
168 #define OWL_EMAC_BIT_MAC_CSR20_BPE BIT(27) /* Back pressure (half-duplex) Enable */
276 u32 msg_enable; /* Debug message level */